JP2008269199A - Integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit device for voice reproduction, capable of easily controlling the time of processing voice data, and easily performing switching between a mode for reproducing a plurality of voices with superimposing and a normal reproduction mode. <P>SOLUTION: The integrated circuit device 1 comprises four or more buffers 20, a buffer control part 30 which controls write processing of data to the buffers and read processing of data from the buffers based on a command from a host 100, and a reproduction voice data output processing part 50 which is adapted so that a plurality of voice data can be simultaneously received, and outputs reproduction voice data based on the simultaneously input voice data. The buffer control part 30 performs switching between a first operation mode for operating the buffers 20 as one double buffer and a second operation mode for operating the buffers 20 as a plurality of double buffers based on the command from the host. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an integrated circuit device (audio reproduction IC) for reproducing audio.

There is known an audio reproduction IC that receives audio data and performs a process for reproducing audio. Further, a technique for reproducing a sound in which a plurality of sounds are superimposed based on sound data indicating two or more kinds of sounds is known.
JP 2000-308015 A

  In order to reproduce natural sound with the sound reproduction IC, it is important to control the timing of processing the sound data. Further, if a plurality of audio data can be controlled at a desired timing by the audio reproduction IC, natural audio can be reproduced by being superimposed. Further, if the mode for reproducing a plurality of sounds in a superimposed manner and the normal sound reproduction mode can be easily switched, the convenience of the sound reproduction IC can be improved.

  An object of the present invention is to easily control the timing of processing audio data, and to easily switch between a mode in which a plurality of sounds are superimposed and reproduced and a normal reproduction mode. An object of the present invention is to provide an integrated circuit device for sound reproduction.

(1) An integrated circuit device according to the present invention includes:
An integrated circuit device that performs audio reproduction processing based on commands and audio data input from a host,
L buffers (L is an integer of 4 or more);
Based on the command, a buffer control unit that controls data write processing to the buffer and data read processing from the buffer;
Reproduction audio data output processing that is configured to receive n (n is an integer of 2 or more) audio data at the same time and outputs audio data for reproduction based on the n audio data input simultaneously. And
Including
The buffer control unit
When the command input from the host is a first operation mode designation command that designates the operation mode of the buffer control unit as the first operation mode,
Classifying the L buffers into N (N is an integer of 2 or more) areas including M (M is an integer);
Controls the write process and the read process so that data is read from the buffer belonging to another area when data is written to the buffer belonging to any area. And
When the command input from the host is a second operation mode designation command that designates the operation mode of the buffer control unit as a second operation mode,
Classifying the L buffers into n areas including m (m is an integer of 2 or more) the buffers;
The writing process and the reading so that data is read from other buffers belonging to the same area when data is written to any of the buffers belonging to one area. Control processing.

  In the present invention, when the command input from the host is the first operation mode designation command, the process of reading data from any of the other buffers is performed in parallel with the process of writing data to any of the buffers. Done. That is, the buffer 20 operates as one double buffer (or multi-buffer). Therefore, one stream data can be processed at a desired timing.

  Further, in the present invention, when the command input from the host is the second operation mode designation command, the other is performed in parallel with the process of writing data to any buffer in each of the n classified areas. A process of reading data from any of the buffers is performed. That is, the buffer 20 operates as n double buffers (multi-buffers). Therefore, each of n pieces of stream data (a plurality of audio data) can be processed at a desired timing.

  In addition, according to the present invention, it is possible to provide a highly convenient integrated circuit device in which the operation mode of the buffer control unit can be easily changed by a command from the host.

(2) In this integrated circuit device,
When the command input from the host is the second operation mode designation command,
The buffer control unit
The read processing may be controlled so that data is read from each read target buffer in different n areas in parallel.

(3) In this integrated circuit device,
The reproduction audio data output processing unit
The audio data for reproduction may be output based on n audio data read in parallel from the respective read target buffers in the n different areas.

(4) In this integrated circuit device,
The buffer control unit
When the command input from the host is the first operation mode designation command,
In one area, data writing to the buffers belonging to different areas is not performed in parallel, and data reading from the buffers belonging to the different areas is not performed in parallel. The writing process and the reading process may be controlled so that data writing to the buffer to which the buffer belongs and data reading from the buffer belonging to the one area are not performed in parallel.

(5) In this integrated circuit device,
The buffer control unit
When the command input from the host is the second operation mode designation command,
Data writing to the plurality of buffers belonging to one area is not performed in parallel, and data reading from the plurality of buffers belonging to the one area is not performed in parallel. The writing process and the reading process may be controlled.

(6) In this integrated circuit device,
The buffer control unit
The writing process and the reading process may be controlled so that writing and reading of data to the respective buffers are not performed in parallel.

  For example, in the present invention, a single port memory may be applied as the buffer.

(7) In this integrated circuit device,
A serial controller for performing serial communication with the host by handshaking;
The serial controller may detect that data can be written to any of the buffers and transmit a signal requesting new audio data to the host.

  As a result, it is possible to efficiently write data to the buffer and read data from the buffer at a desired timing.

(8) In this integrated circuit device,
The reproduction audio data output processing unit
The n pieces of audio data input simultaneously may be superimposed and output.

(9) In this integrated circuit device,
A detection processing unit for detecting whether each of the n pieces of audio data simultaneously input to the reproduced audio data output processing unit is voiced voice data indicating sound or silent voice data indicating silence; ,
The reproduction audio data output processing unit
When the n pieces of voice data input at the same time include only one voiced voice data, the voiced voice data may be output as the voice data for reproduction.

(10) In this integrated circuit device,
A detection processing unit for detecting whether each of the n pieces of audio data input simultaneously to the reproduced audio data output processing unit is voiced voice data indicating voice or silent voice data indicating silence;
Operation mode of the reproduction audio data output processing unit when it is detected that the n audio data input simultaneously includes k audio data (k is an integer not less than 2 and not more than n) , The k voiced voice data is superimposed and output, the k voiced voice data selection output mode is selected and output, and the reproduced voice is silent. A silent output mode for outputting audio data, an operation mode setting processing unit for setting to one of the following,
Further including
The reproduction audio data output processing unit
When the operation mode is set to the mixing mode, the k voiced voice data input simultaneously are superimposed and output,
When the operation mode is set to the selective output mode, select and output one of the k voiced voice data input simultaneously,
When the operation mode is set to the silent output mode, audio data in which the reproduced voice is silent may be output.

(11) In this integrated circuit device,
L = M × N = m × n may be sufficient.

(12) In this integrated circuit device,
M = N = m = n = 2 may be sufficient.

  Embodiments to which the present invention is applied will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments. The present invention includes any combination of the following embodiments and modifications.

  The integrated circuit device 1 according to the present embodiment is an integrated circuit device that outputs audio data for reproducing audio based on a command and audio data input from the host 100.

  The host 100 may be an electronic device that performs overall control of the operation of a given electronic device. The host 100 includes a CPU 110 and a memory 120. The CPU 110 uses the memory 120 as a work area and performs various processes for controlling the operation of the electronic device. The host 100 also includes a serial controller 130. Serial communication between the host 100 and the integrated circuit device 1 is realized by the serial controller 130. However, in the present invention, the communication method between the host 100 and the integrated circuit device 1 is not limited to serial communication. The communication method between the host 100 and the integrated circuit device 1 may be, for example, parallel communication (parallel connection method). Alternatively, communication between the host 100 and the integrated circuit device 1 may be realized via a bus.

  The electronic device that is controlled by the host 100 (the electronic device in which the host 100 is mounted) is not particularly limited. The electronic device may be, for example, a domestic electric appliance such as a rice cooker, a lighting fixture, a washing machine, an electric kettle, a water heater, or an air conditioner. Alternatively, the electronic device may be a device that displays an image such as a television or a projector, a device that records and reproduces an image such as a DVD, a device that records and reproduces audio such as audio, or a car navigation system. .

  In the present embodiment, the integrated circuit device 1 and the host 100 may be collectively referred to as an audio reproduction system.

1. Configuration of Integrated Circuit Device 1 Hereinafter, the configuration of the integrated circuit device 1 according to the present embodiment will be described. 1 to 5 are diagrams for explaining the integrated circuit device 1.

  The integrated circuit device 1 according to the present embodiment includes a buffer device 10. The buffer device 10 includes a buffer 20 that temporarily stores data, and a buffer control unit 30 that controls writing of data into the buffer 20 and reading of data from the buffer 20. Hereinafter, the buffer device 10 will be described.

  The buffer device 10 includes L (L is an integer of 4 or more) buffers 20. In the present embodiment, as shown in FIGS. 1 to 3, the buffer device 10 includes four buffers 20 (first buffer 21, second buffer 22, third buffer 23, and fourth buffer 24. )including. However, the present invention is not limited to this, and the buffer device 10 may include four or more buffers 20.

  The buffer device 10 includes a buffer control unit 30. The buffer control unit 30 controls data write processing to the buffer 20 and data read processing from the buffer 20. Specifically, the buffer control unit 30 selects any one of the four buffers 20 (the first to fourth buffers 21, 22, 23, and 24) (the write target buffer), and stores the data in the selected buffer. Execute the write process. Further, the buffer control unit 30 selects a buffer (read target buffer) for reading data from the four buffers 20 and executes a process of reading data from the selected buffer. The buffer control unit 30 controls data write processing to the buffer 20 and data read processing from the buffer 20 based on commands from the host 100. The buffer control unit 30 may control the writing process and the reading process so that writing of data to one buffer 20 and reading of data are not performed in parallel.

  In the present embodiment, the buffer control unit 30 operates in a plurality of operation modes including the first and second operation modes. The buffer control unit 30 sets an operation mode based on a command input from the host 100. Specifically, when the command input from the host 100 is a first operation mode designation command that designates the operation mode of the buffer control unit 30 as the first operation mode, the buffer control unit 30 performs the first operation. Operate in mode. Conversely, when the command input from the host 100 is a second operation mode designation command that designates the operation mode of the buffer control unit 30 as the second operation mode, the buffer control unit 30 performs the second operation. Operate in mode.

  Hereinafter, specific operations of the buffer control unit 30 (data writing processing to the buffer 20 and data reading processing from the buffer 20) will be described.

(1) When the command from the host 100 is the first operation mode designation command The buffer control unit 30 determines that the L buffers when the command input from the host 100 is the first operation mode designation command. 20 is classified into N (N is an integer of 2 or more) areas including M (M is an integer) buffers 20. In the present embodiment, the four buffers 20 are classified into two areas including two buffers. Specifically, in the present embodiment, as shown in FIG. 2, the buffer 20 includes the first region 25 including the first and second buffers 21 and 22, and the third and fourth buffers 23 and 24. It classify | categorizes into the 2nd area | region 26 containing.

  Then, the buffer control unit 30 writes data so that data is read from the buffer 20 belonging to one other area when data is written to the buffer 20 belonging to any one area. Control processing and read processing. In other words, the buffer control unit 30 writes (reads) data to the first buffer 21 or the second buffer 22, and reads (writes) data from the third buffer 23 or the fourth buffer 24. The data writing process and the data reading process may be performed so that the processes are performed at the same time (simultaneously).

  That is, when the command input from the host 100 is the first operation mode designation command, the buffer control unit 30 selects the buffer 20 belonging to the first area 25 and the buffer 20 belonging to the second area 26. Operate as a double buffer. Thereby, the process which writes data in the buffer 20 and the process which reads data from the buffer 20 can be performed at the timing which overlaps in time. Therefore, the timing for processing the audio data can be easily controlled.

  In the present embodiment, the buffer control unit 30 may control the data writing process to the buffer 20 so that the data writing to the buffer 20 belonging to different areas is not simultaneously performed. That is, the buffer controller 30 writes data to the third and fourth buffers 23 and 24 when data is written to at least one of the first and second buffers 21 and 22. In order to prevent this, the data writing process to the buffer 20 may be controlled. The buffer control unit 30 writes data to the first and second buffers 21 and 22 when data is written to at least one of the third and fourth buffers 23 and 24. In order to prevent this, the data writing process to the buffer 20 may be controlled.

  Further, the buffer control unit 30 may control the writing process from the buffer 20 so that the data reading from the buffers 20 belonging to different areas is not simultaneously performed. That is, the buffer control unit 30 reads data from the third and fourth buffers 23 and 24 when data is read from at least one of the first and second buffers 21 and 22. In order to prevent this, the process of reading data from the buffer 20 may be controlled. The buffer control unit 30 reads data from the first and second buffers 21 and 22 when data is read from at least one of the third and fourth buffers 23 and 24. In order to prevent this, the process of reading data from the buffer 20 may be controlled.

  Further, the buffer control unit 30 may control the writing process and the reading process so that data writing and reading to the buffer 20 belonging to one area are not performed simultaneously. In other words, the buffer control unit 30 performs a write process so that data reading (writing) from the second buffer 22 is not performed when data writing (reading) to the first buffer 21 is performed. In addition, the reading process may be controlled. Further, the buffer control unit 30 performs a writing process so that data reading (writing) from the fourth buffer 24 is not performed when data writing (reading) to the third buffer 23 is performed. In addition, the reading process may be controlled.

(2) When the command from the host 100 is the second operation mode designation command The buffer control unit 30 determines that the L buffers when the command input from the host 100 is the second operation mode designation command. 20 is classified into n (n is an integer of 2 or more) areas including m (m is an integer of 2 or more) buffers 20. In the present embodiment, the four buffers 20 are classified into two areas including two buffers. Specifically, in the present embodiment, as shown in FIG. 3, the buffer 20 includes the first region 27 including the first and second buffers 21 and 22, and the third and fourth buffers 23 and 24. It classify | categorizes into the 2nd area | region 28 containing.

  Then, the buffer control unit 30 reads data from one other buffer 20 belonging to the same area when data is written to any one of the buffers 20 belonging to the one area. In addition, the writing process and the reading process are controlled. That is, the buffer control unit 30 writes and reads data so that data writing (reading) to the first buffer 21 and data reading (writing) from the second buffer 22 are performed simultaneously. Processing may be controlled. In addition, the buffer control unit 30 performs data writing processing and reading so that data writing (reading) to the third buffer 23 and data reading (writing) from the fourth buffer 24 are performed simultaneously. Processing may be controlled.

  That is, when the command input from the host 100 is the second operation mode designation command, the buffer control unit 30 buffers the buffers 20 (first and second buffers 21 and 22) belonging to the first area 27. Is operated as a double buffer, and the buffer 20 (third and fourth buffers 23 and 24) belonging to the second area 28 is operated as a double buffer. In other words, when the command input from the host 100 is the second operation mode designation command, the buffer control unit 30 operates the buffer 20 as n (two) double buffers. Therefore, it is possible to easily control the timing for processing a plurality of audio data.

  In the present embodiment, the buffer control unit 30 may control the reading process so that data is read from the read target buffers 20 in different n areas in parallel. Specifically, the buffer control unit 30 performs reading of data from the first buffer 21 or the second buffer 22 and reading of data from the third buffer 23 or the fourth buffer 24 in parallel. As described above, the reading process may be controlled. This makes it possible to read out audio data to be mixed in parallel.

  In the present embodiment, the buffer control unit 30 may control the data writing process to the buffer 20 so that the data writing to the buffer 20 belonging to one area is not simultaneously performed. That is, the buffer control unit 30 does not write data to the first and second buffers 21 and 22 at the same time, and writes data to the third and fourth buffers 23 and 24 at the same time. The writing process may be controlled so that there is no such problem.

  Further, the buffer control unit 30 may control the data reading process from the buffer 20 so that the data reading from the buffer 20 belonging to one area is not simultaneously performed. That is, the buffer control unit 30 does not read data from the first and second buffers 21 and 22 at the same time, and reads data from the third and fourth buffers 23 and 34 at the same time. The reading process may be controlled so that there is no such problem.

  The integrated circuit device 1 according to the present embodiment includes a decoder 40. The decoder 40 decodes the data read from the buffer 20. The function of the decoder 40 may be realized by a dedicated control circuit, or may be realized by executing a predetermined program by a processor such as a CPU.

  In the present embodiment, the decoder 40 includes first and second decoders 42 and 44. The first decoder 42 is a decoder that decodes data read from the first region 25 or the first region 27 (the first buffer 21 or the second buffer 22). The second decoder 44 is a decoder that decodes data read from the second area 26 or the first area 27 (the third buffer 23 or the fourth buffer 24).

  However, as a modification, the decoder 40 may be configured not to include two decoders (first and second decoders 42 and 44). The integrated circuit device of the present invention may include a decoder configured to decode data input from the host 100 and write the decoded data to the buffer device 10. In other words, the decoder 40 may be arranged on the upstream side (serial controller 60 side) of the buffer device 10.

  The integrated circuit device 1 according to the present embodiment includes a reproduction audio data output processing unit 50. The reproduced audio data output processing unit 50 is configured to be able to accept n pieces of audio data at the same time. The reproduction audio data output processing unit 50 is configured to output audio data for reproduction based on n pieces of audio data input simultaneously.

  In the present embodiment, the reproduction audio data output processing unit 50 may be configured to superimpose and output a plurality of audio data input simultaneously. At this time, the reproduction audio data output processing unit 50 may include a circuit (mixing circuit) that superimposes (adds) a plurality of audio data input simultaneously.

  Note that the playback audio data output processing unit 50 receives only one audio data (when the operation mode of the buffer control unit 30 is designated as the first operation mode), the one audio data May be output as audio data for reproduction.

  The function of the reproduced audio data output processing unit 50 may be realized by a dedicated control circuit, or may be realized by executing a predetermined program by a processor such as a CPU.

  The integrated circuit device 1 according to the present embodiment may include a post-decoding data storage buffer 55. The decoded data storage buffer 55 is a storage unit that temporarily stores the data decoded by the decoder 40 and outputs the data to the reproduced audio data output processing unit 50. The post-decoding data storage buffer 55 may be configured to manage data input / output in a first-in first-out manner.

  The decoded data storage buffer 55 may include first and second decoded data storage buffers 52 and 54. Here, the first decoded data storage buffer 52 is a buffer corresponding to the first decoder 42, and the second decoded data storage buffer 54 is a buffer corresponding to the second decoder 44. May be. The first and second post-decoding data storage buffers 52 and 54 are configured to simultaneously input the data received from the first and second decoders 42 and 44 to the reproduction audio data output processing unit 50, respectively. May be. By using the post-decoding data storage buffer 55, desired audio data can be superimposed and output. The first and second decoded data storage buffers 52 and 54 include the buffer 20 (the first buffer 21 or the second buffer 22) classified into the first area 27, and the second area 28. The two audio data read simultaneously from the buffer 20 (the third buffer 23 or the fourth buffer 24) classified into the following may be input to the reproduction audio data output processing unit 50 at the same time: .

  The integrated circuit device 1 according to the present embodiment includes a serial controller 60. The serial controller 60 performs serial communication with the host 100 by handshaking. That is, the serial controller 60 receives commands and data (audio data) input from the host 100 and inputs them to the buffer device 10. Further, the serial controller 60 detects that data can be written to any of the buffers 20 (any one of the first to fourth buffers 21, 22, 23, and 24), and notifies the host 100. A signal requesting new data (voice data) is transmitted. The serial controller 60 may generate a command for requesting new data and send it to the host 100. The serial controller 60 communicates the integrated circuit device 1 and the host 100 by handshaking, thereby efficiently writing data to the buffer 20 (buffer device 10) and reading data from the buffer 20. it can.

  However, as a modification, the integrated circuit device may include a data transfer control device other than the serial controller. The integrated circuit device may be configured to accept data in a parallel connection method. Alternatively, the integrated circuit device may be configured to receive data through a bus connection.

  In the present embodiment, the integrated circuit device 1 in which M = N = m = n = 2 has been described. However, the present invention is not limited to this. In particular, M ≠ m or N ≠ n. Further, each of M, N, m, and n may be any value of 3 or more.

  Next, a hardware configuration for realizing the integrated circuit device 1 will be described.

  As shown in FIG. 4, the integrated circuit device 1 may include a control unit 72. The control unit 72 may be hardware that performs various controls for realizing the operation of the integrated circuit device 1. The control unit 72 may realize each function of the buffer control unit 30. In addition, the control unit 72 may control the operations of the decoder 40, the post-decoding data storage buffer 55, and the serial controller 60.

  Alternatively, the integrated circuit device 1 may include a CPU 74 and a memory 76 as shown in FIG. The CPU 74 uses the memory 76 as a work area, and performs various processes for realizing the operation of the integrated circuit device 1. The CPU 74 may realize each function of the buffer control unit 30. The memory 76 may implement the buffer 20 and the decoded data storage buffer 55.

  The integrated circuit device 1 according to the present embodiment may be configured as described above. Hereinafter, the operation of the integrated circuit device 1 will be described.

2. Operation of Integrated Circuit Device 1 Next, the operation of the integrated circuit device 1 according to the present embodiment will be described with reference to FIG. FIG. 6 is a diagram showing, in time series, how data is written to the buffer 20 and data is read from the buffer 20. In each buffer 20 in FIG. 6, an area represented by shading indicates a state where data is stored. In the example shown in FIG. 6, the area where the data acquired when the command from the host 100 is the first operation mode designation command is indicated by thin shading, and the command from the host 100 is the second. The area in which the acquired data is stored in the case of the operation mode designation command is shown by dark shading.

  First, in step S1, a command (CmdFillBufferA) and data are input from the host 100, and data is written in the first area 25 (first and second buffers 21 and 22). Here, the command (CmdFillBufferA) is a command that designates the operation mode of the buffer control unit 30 as the first operation mode.

  In step S2, a command (CmdFillBufferB) and data are input from the host 100, and the data is written in the second area 26 (third and fourth buffers 23 and 24).

  In step S3, a command (DecodeStart) is input from the host 100, and reading of data written in the buffer 20 starts.

  Data in the first area 25 (first and second buffers 21 and 22) is read out, and the first and second buffers 21 and 22 are emptied to the first and second buffers 21 and 22. When the data can be written, a command (ReqFillBufferA) for requesting data is issued and transmitted to the host 100 (step S4).

  In a fifth step, a command (CmdFillBufferA) and data are input from the host 100, and data is written in the first area 25 (first and second buffers 21, 22). In the present embodiment, a process of reading data written in the second area 26 is performed in parallel with the process of writing data in the first area 25. Therefore, in step S5, all the data written in the third buffer 23 is read out.

  The data in the second area 26 (the third and fourth buffers 23 and 24) is read, and the third and fourth buffers 23 and 24 are emptied to the third and fourth buffers 23 and 24. When the data can be written, a command (ReqFillBufferB) requesting data is issued and transmitted to the host 100 (step S6).

  In step S7, a command (CmdFillBufferB) and data are input from the host 100, and the data is written in the second area 26 (third and fourth buffers 23 and 24). In the present embodiment, a process for reading data written in the first area 25 is performed in parallel with the process for writing data in the second area 26. Therefore, in step S7, all the data written in the first buffer 21 is read out.

  When data can be written to the first and second buffers 21 and 22, a command (ReqFillBufferA) for requesting data is issued and transmitted to the host 100 (step S8).

  In step S 9, a command (CmdFillBufferMA 1) and data are input from the host 100 and written to the first buffer 21. Here, the command (CmdFillBufferMA1) is a command that designates the operation mode of the buffer control unit 30 as the second operation mode (mixing mode). After step S9, the buffer control unit 30 operates in the second operation mode.

  Then, a command for requesting data (ReqFillBufferMB1) is transmitted in step S10, and the data is written in the third buffer 23 in step S11.

  Then, a command (ReqFillBufferMA2) for requesting data is transmitted in step S12, and the data is written in the second buffer 22 in step S13.

  Then, a command (ReqFillBufferMB2) for requesting data is transmitted in step S14, and data is written in the fourth buffer 24 in step S15.

  In step S16, a command (DecodeStart) is input, and reading of data written in the buffer 20 is started. In step S16 and step S17, the data from the first buffer 21 and the third buffer 23 are read simultaneously.

  When the data reading from the first buffer 21 and the third buffer 23 is completed and the data can be written to the first buffer 21 and the third buffer 23, a command (ReqFillBuffer ) Is issued and transmitted to the host 100 (step S17). In step S17 and subsequent steps, a command for requesting data from the host 100 is omitted for simplicity.

  In step S18, a command (CmdFillBufferMA1) is input, and data is written to the first buffer 21. At the same time, data is read from the second buffer 22 and the fourth buffer 24.

  In step S19, a command (CmdFillBufferMB1) is input, and data is written to the third buffer 23. At the same time, data is read from the second buffer 22 and the fourth buffer 24.

  In step S 20, a command (CmdFillBufferMA 2) is input and data is written to the second buffer 22. At the same time, data is read from the first buffer 21 and the third buffer 23.

  In step S21, a command (CmdFillBufferMB2) is input, and data is written to the fourth buffer 24. At the same time, data is read from the second buffer 22 and the fourth buffer 24.

  Thereafter, steps S18 to S21 are repeated (see steps S22 to S25).

3. Operational effects produced by the integrated circuit device 1 Hereinafter, operational effects produced by the integrated circuit device 1 will be described.

  As described above, in the integrated circuit device 1, the buffer control unit 30 operates in the first and second operation modes.

  When the buffer control unit 30 operates in the first operation mode, the buffer control unit 30 includes the buffers belonging to the first area 25 (first and second buffers 21 and 22) and the buffers belonging to the second area 26. (The third and fourth buffers 23 and 24) are operated as a double buffer. According to this, since the data read after that can be stored in the buffer 20 while the process of reading the data from the buffer 20 is performed, the voice data input from the host 100 can be output at a desired pace. The voice can be played as if it were spoken at a natural pace.

  When the buffer control unit 30 operates in the second operation mode, the buffer 30 operates the buffers 20 (first and second buffers 21 and 22) belonging to the first area 27 as double buffers, The buffer 20 (third and fourth buffers 23 and 24) belonging to the second area 28 is operated as a double buffer. That is, the buffer 20 is operated as two (n) double buffers. Therefore, it is possible to output two types (n types) of sounds at a desired pace. Then, by superimposing the two types (n types) of sounds by the reproduction audio data output processing unit 50, it is possible to reproduce the sound on which the sound uttered at a natural pace is superimposed.

  In the integrated circuit device 1, the operation mode of the buffer control unit 30 is specified by a command. Therefore, the operation mode of the buffer control unit 30 can be easily switched, and a highly convenient integrated circuit device can be provided.

  In the integrated circuit device 1, the buffer 20 is used regardless of whether the operation mode of the buffer control unit 30 is set to the first or second operation mode. In other words, even when the buffer control unit 30 operates in different operation modes, the buffer 20 can be shared. Therefore, it is not necessary to prepare a buffer for each operation mode, so that the device configuration can be simplified and the utilization efficiency of the device configuration (buffer) can be increased.

4). Modifications The present invention is not limited to the above-described embodiment, and various modifications can be made. The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

  Hereinafter, modifications of the embodiment to which the present invention is applied will be described.

(1) First Modification FIG. 7 is a diagram for explaining an integrated circuit device 2 according to a first modification.

  The integrated circuit device 2 detects whether each of the n pieces of sound data simultaneously input to the reproduction sound data output processing unit 50 is sound sound data indicating sound or sound data indicating silence. The detection processing unit 80 is included.

  The reproduction audio data output processing unit 50 outputs the audio data as audio data for reproduction when the n audio data input at the same time includes only one audio data. It may be configured as follows. At this time, the reproduction audio data output processing unit 50 may output the audio data without passing through the mixing circuit for superimposing the audio data.

  According to this, it is possible to reduce the possibility that noise is included in the voiced voice data, and it is possible to utter a voice with less noise.

(2) Second Modification FIG. 8 is a diagram for explaining an integrated circuit device 3 according to a second modification.

  The integrated circuit device 3 includes an operation mode setting processing unit 90 that sets an operation mode of the reproduction audio data output processing unit 50. The operation mode setting processing unit 90 includes k pieces of voiced sound data (k is an integer of 2 or more and n or less) in the n pieces of sound data input simultaneously to the reproduction sound data output processing unit 50. The operation mode of the reproduction audio data output processing unit 50 is detected. That is, the operation mode setting processing unit 90 sets the operation mode of the reproduction audio data output processing unit 50 when a plurality of voiced audio data is simultaneously input to the reproduction audio data output processing unit 50.

  The operation mode setting processing unit 90 selects one of the operation mode of the reproduction audio data output processing unit 50 as a mixing mode for superimposing and outputting k sound data and k sound data. You may set to either the selection output mode which selects and outputs, and the silence output mode which outputs the silence audio | voice data from which a reproduction | regeneration audio | voice becomes silence.

  When the operation mode setting processing unit 90 is set to the mixing mode, the reproduction audio data output processing unit 50 receives k sound data simultaneously from the reproduction audio data output processing unit 50. The k voiced audio data is superimposed and output. In addition, when the operation mode setting processing unit 90 is set to the selection output mode, the reproduction audio data output processing unit 50 has k voiced audio data input to the reproduction audio data output processing unit 50 at the same time. In some cases, a process of selecting and outputting any of the k voiced voice data is performed. In addition, when the operation mode setting processing unit 90 is set to the silent output mode, the reproduced audio data output processing unit 50 receives k voiced audio data simultaneously input to the reproduced audio data output processing unit 50. Sometimes, a process of outputting silent voice data is performed.

  The operation mode setting processing unit 90 may set the operation mode of the reproduction audio data output processing unit 50 based on a command from the host 100. Alternatively, the operation mode setting processing unit 90 may set the operation mode of the reproduction audio data output processing unit 50 based on a setting signal from the outside (user).

  According to the integrated circuit device 3, it is possible to change the operation of the reproduced audio data output processing unit 50 according to the nature of the input audio data and the application of the integrated circuit device 3.

4A and 4B illustrate an integrated circuit device according to this embodiment. 4A and 4B illustrate an integrated circuit device according to this embodiment. 4A and 4B illustrate an integrated circuit device according to this embodiment. 4A and 4B illustrate an integrated circuit device according to this embodiment. 4A and 4B illustrate an integrated circuit device according to this embodiment. 4A and 4B illustrate an integrated circuit device according to this embodiment. The figure for demonstrating the integrated circuit device which concerns on a modification. The figure for demonstrating the integrated circuit device which concerns on a modification.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Integrated circuit device, 2 ... Integrated circuit device, 3 ... Integrated circuit device, 10 ... Buffer device, 20 ... Buffer, 21 ... First buffer, 22 ... Second buffer, 23 ... Third buffer, 24 ... 4th buffer, 25 ... 1st area | region, 26 ... 2nd area | region, 27 ... 1st area | region, 28 ... 2nd area | region, 30 ... Buffer control part, 40 ... Decoder, 42 ... 1st decoder, 44 ... second decoder, 50 ... reproduced audio data output processing unit, 52 ... first decoded data storage buffer, 54 ... second decoded data storage buffer, 55 ... decoded data storage buffer, 60 ... serial controller 72 ... Control unit 74 ... CPU 76 ... Memory 80 ... Detection processing unit 90 ... Operation mode setting processing unit 100 ... Host 110 ... CP , 120 ... memory, 130 ... serial controller

Claims (12)

An integrated circuit device that performs audio reproduction processing based on commands and audio data input from a host,
L buffers (L is an integer of 4 or more);
Based on the command, a buffer control unit that controls data write processing to the buffer and data read processing from the buffer;
Reproduction audio data output processing that is configured to receive n (n is an integer of 2 or more) audio data at the same time and outputs audio data for reproduction based on the n audio data input simultaneously. And
Including
The buffer control unit
When the command input from the host is a first operation mode designation command that designates the operation mode of the buffer control unit as the first operation mode,
Classifying the L buffers into N (N is an integer of 2 or more) areas including M (M is an integer);
Controls the write process and the read process so that data is read from the buffer belonging to another area when data is written to the buffer belonging to any area. And
When the command input from the host is a second operation mode designation command that designates the operation mode of the buffer control unit as a second operation mode,
Classifying the L buffers into n areas including m (m is an integer of 2 or more) the buffers;
The writing process and the reading so that data is read from other buffers belonging to the same area when data is written to any of the buffers belonging to one area. An integrated circuit device that controls processing. The integrated circuit device according to claim 1,
When the command input from the host is the second operation mode designation command,
The buffer control unit
An integrated circuit device that controls the read processing so that data is read from each read target buffer in different n areas in parallel. The integrated circuit device according to claim 2, wherein
The reproduction audio data output processing unit
An integrated circuit device that outputs audio data for reproduction based on n audio data read in parallel from the respective read target buffers in the different n areas. The integrated circuit device according to claim 1,
The buffer control unit
When the command input from the host is the first operation mode designation command,
In one area, data writing to the buffers belonging to different areas is not performed in parallel, and data reading from the buffers belonging to the different areas is not performed in parallel. An integrated circuit device that controls the writing process and the reading process so that writing of data to the buffer to which the buffer belongs and reading of data from the buffer belonging to the one area are not performed in parallel. The integrated circuit device according to any one of claims 1 to 4,
The buffer control unit
When the command input from the host is the second operation mode designation command,
Data writing to the plurality of buffers belonging to one area is not performed in parallel, and data reading from the plurality of buffers belonging to the one area is not performed in parallel. An integrated circuit device for controlling the writing process and the reading process. The integrated circuit device according to any one of claims 1 to 5,
The buffer control unit
An integrated circuit device that controls the writing process and the reading process so that writing and reading of data to and from each of the buffers are not performed in parallel. The integrated circuit device according to claim 1,
A serial controller for performing serial communication with the host by handshaking;
The integrated circuit device, wherein the serial controller detects that data can be written to any of the buffers, and transmits a signal requesting new audio data to the host. The integrated circuit device according to any one of claims 1 to 7,
The reproduction audio data output processing unit
An integrated circuit device that superimposes and outputs the n pieces of audio data input simultaneously. The integrated circuit device according to any one of claims 1 to 7,
A detection processing unit for detecting whether each of the n pieces of audio data simultaneously input to the reproduced audio data output processing unit is voiced voice data indicating sound or silent voice data indicating silence; ,
The reproduction audio data output processing unit
An integrated circuit device for outputting the sounded sound data as the sound data for reproduction when only one sounded sound data is included in the n sound data input simultaneously. The integrated circuit device according to any one of claims 1 to 7,
A detection processing unit for detecting whether each of the n pieces of audio data input simultaneously to the reproduced audio data output processing unit is voiced voice data indicating voice or silent voice data indicating silence;
Operation mode of the reproduction audio data output processing unit when it is detected that the n audio data input simultaneously includes k audio data (k is an integer not less than 2 and not more than n) , The k voiced voice data is superimposed and output, the k voiced voice data selection output mode is selected and output, and the reproduced voice is silent. A silent output mode for outputting audio data, an operation mode setting processing unit for setting to one of the following,
Further including
The reproduction audio data output processing unit
When the operation mode is set to the mixing mode, the k voiced voice data input simultaneously are superimposed and output,
When the operation mode is set to the selective output mode, select and output one of the k voiced voice data input simultaneously,
An integrated circuit device for outputting sound data in which the reproduced sound is silenced when the operation mode is set to the silence output mode. The integrated circuit device according to claim 1,
An integrated circuit device in which L = M × N = m × n. The integrated circuit device according to any one of claims 1 to 11,
An integrated circuit device in which M = N = m = n = 2.