JP2008267841A - Semiconductor tester - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor tester for shortening the time required for calibration. <P>SOLUTION: In the semiconductor tester, correction data in a calibration operation storage means 1 are added to level data output from a level data output means 40, level voltages VH and VL corresponding to data obtained by the addition are applied to a DUT via a driver 5, the voltages are measured by a voltage measuring means 30, and the correction data are operated based on the measured voltages and the level data. The semiconductor tester includes a comparator 8 for comparing the voltages output from the driver 5 with reference values H-LIM and L-LIM, and a determination circuit 50 for determining the propriety of calibration execution based on a signal output from the comparator 8. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to level calibration in pin electronics of a semiconductor test apparatus such as an IC tester.

  In general, a semiconductor test apparatus gives a test signal to an IC, LSI or the like to be tested (DUT), measures the output of the DUT, and determines whether the DUT is good or bad. The semiconductor test apparatus has a pin electronics substrate formed of a combination of a driver circuit and a comparator circuit in a test head, and outputs a test signal and evaluates a DUT. In this case, in order to maintain the voltage level accuracy of the driver, it is necessary to calibrate the voltage level applied to the DUT.

  FIG. 3 is a block diagram showing the configuration of a conventional semiconductor test apparatus. Since the n pin electronics 301, 302,... 30n have the same configuration, the pin electronics 301 will be described below as an example. The level data output means 40 outputs level data (data set) corresponding to the voltage level to the pin electronics 301. The calibration calculation storage means 1 has a memory for storing initial correction data and difference correction data as correction data for calibration, and an addition / subtraction function for performing correction / calibration calculations between correction data, level data, and measurement voltage data. Corresponding to the level data sent from the level data output means 40, the corrected correction level data is output to the digital signal bus 2. The DA converters 3 and 4 convert the high level and low level correction level data sent via the digital signal bus 2 into the high level voltage VH and the low level voltage VL, respectively. The driver 5 outputs the drive voltage set by the voltages VH and VL output from the DA converters 3 and 4 as the output voltage Vout corresponding to the pattern data Din. The output relay 6 is connected between the driver 5 and the DUT and is opened and closed by a control signal. The DC relay 7 is connected between the output relay 6 and the voltage measurement unit 30 and is opened and closed by a control signal. A tester controller (hereinafter referred to as TSC) 60 issues a command to the level data output means 40, the calibration calculation storage means 1 and the voltage control unit 30 to control the calibration process.

The operation of the apparatus of FIG. 3 will be described below.
In the test mode, calibrated correction level data output from the calibration calculation storage means 1 is converted into level voltages by the DA converters 3 and 4 via the digital signal bus 2, and VH and VL are output, respectively. The The level voltages VH and VL are the H side and L side drive voltage setting inputs of the driver 5, respectively. As shown in the time chart of FIG. 4, when the input pattern data Din is “H”, VH is output as the output voltage Vout. When the input pattern data Din is “L”, VL is output. The output relay 6 is closed by the control signal from the TSC 60, and the output voltage Vout is applied to the DUT via the output relay 6.

In the calibration mode, the DC relay 7 is closed by a control signal from the TSC 60, and the output voltage Vout is measured by the voltage control unit 30 via the DC relay 7. The data corresponding to the measured voltage is sent to the calibration calculation storage means 1 via the TSC 60, and the initial correction data stored in the memory in the calibration calculation storage means 1 and the level data sent from the level data output means 40. The difference is taken (Equation (1)) and stored in the memory in the calibration calculation storage means 1 as difference correction data.
Level data-(initial correction data + measured voltage data) = difference correction data (1)

In the test mode described above, a value obtained by adding the initial correction data and the difference correction data to the level data is output from the calibration calculation storage means 1 as calibrated correction level data. At this time, since the path error due to the DA converters 3 and 4, the driver 5, the output relay 6, the DC relay 7, etc. in the pin electronics 301 is canceled by the initial correction data and the difference correction data, it is observed by the voltage control unit 30. The level voltage to be applied is equal to the level data (formula (2)).
Measurement voltage = level data + (initial correction data + difference correction data) −path error = level data (2)

The stored content of the difference correction data is rewritten every time the calibration mode is used.

  Prior art documents related to level calibration of semiconductor test equipment include the following.

JP-A-7-280885

  In the conventional apparatus, since all the pin electronics are measured by the switching of the relay and the voltage measuring unit, a great amount of time is spent for calibration.

  An object of the present invention is to provide a semiconductor test apparatus that can shorten the time required for calibration.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
A semiconductor test apparatus having a plurality of pin electronics in which a level voltage corresponding to level data is applied to a DUT via a driver, and the level voltage is calibrated based on the level voltage measured by voltage measuring means and the level data In
A comparator for comparing the level voltage with a reference value;
A semiconductor test apparatus comprising: a discriminating unit that discriminates pin electronics for performing the calibration based on a signal output from the comparator.

The invention according to claim 2
The semiconductor test apparatus according to claim 1,
Calibration calculation storage means for calculating correction data from the difference between the level voltage measured by the voltage measuring means and the level data, and adding the correction data to the level data;
And a DA converter that converts the correction level data output from the calibration calculation storage means into a level voltage of the driver.

The invention described in claim 3
The semiconductor test apparatus according to claim 1,
A comparator for pass / fail judgment of the pin electronics is used as the comparator.

The invention according to claim 4
The semiconductor test apparatus according to claim 1,
A DC voltage / current source of the pin electronics is used as the voltage measuring means.

The invention according to claim 5
The semiconductor test apparatus according to claim 1,
A first relay connected between the driver and the DUT;
A second relay connected between the first relay and the voltage measuring means; and performing the calibration by closing the first and second relays of the pin electronics determined by the determination circuit. Features.

  As is apparent from the above description, according to the present invention, the level voltage corresponding to the level data is applied to the DUT via the driver, and based on the level voltage and the level data measured by the voltage measuring means. In a semiconductor test apparatus having a plurality of pin electronics in which the level voltage is calibrated, a comparator for comparing the level voltage with a reference value, and a discrimination for determining the pin electronics to be calibrated based on a signal output from the comparator Since the calibration is performed only for the pin whose voltage level accuracy is poor, the time required for calibration can be shortened.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing the configuration of an example of a semiconductor test apparatus according to an embodiment of the present invention. The same parts as those in FIG. Since the n pin electronics 101, 102,... 10n have the same configuration, the pin electronics 101 will be described below as an example. In the pin electronics 101, the comparator 8 compares the output voltage Vout of the driver 5 with the upper limit H-LIM and the lower limit L-LIM. The detection circuit 9 detects good / bad voltage level accuracy based on the comparison result of the comparator 8. Based on the detection signal output from the detection circuit 9, the calibration necessity determination circuit 50 determines whether or not the pin electronics (101) needs to be calibrated. The TSC 160 starts a calibration process similar to the case of the apparatus of FIG. 3 based on the calibration necessary signal output from the calibration necessity determination circuit 50. Here, the calibration necessity determination circuit 50 constitutes a determination circuit that determines whether or not calibration can be performed based on a signal output from the comparator 8.

  The operation of the apparatus of FIG. 1 will be described below. The output voltage Vout output from the driver 5 is compared with the upper limit H-LIM and the lower limit L-LIM by the comparator 8, and the detection circuit 9 detects good / bad voltage level accuracy based on the comparison result. Here, the upper limit H-LIM and the lower limit L-LIM are given corresponding to “H” and “L” of the input pattern data Din, respectively, and the level voltage VH is greater than the upper limit H-LIM or the level voltage VL is the lower limit. If it is smaller than L-LIM, it is considered good, and otherwise it is considered bad. Based on the detection signal output from the detection circuit 9, the calibration necessity determination circuit 50 determines whether or not the pin electronics (101) needs to be calibrated. To TSC160. Based on the signal requiring calibration, the TSC 160 transmits control commands to the level data output circuit 40, the calibration calculation storage means 1, the voltage measurement unit 30, and the like to the pin electronics (101). The same calibration process as in the case of the apparatus 3 is started.

  According to the semiconductor test apparatus configured as described above, the relays 6 and 7 are opened / closed only for pin electronics with poor voltage level accuracy, and the level voltage is calibrated by measuring with the voltage measurement unit 30. Time can be shortened.

  In the above embodiment, the reference value of the comparator 8 is the upper limit H-LIM and the lower limit L-LIM, but is not limited thereto. For example, the H-side and L-side reference values may be used as window type reference values, and the window width may be set as a “good” range, and the others may be set as “bad” ranges.

  When the initial correction data can be set to 0, the initial correction data area may be omitted from the correction data area for calibration in the memory of the calibration calculation storage means 1.

  FIG. 2 is a block diagram showing an application example of the semiconductor test apparatus shown in FIG. 1, which is configured using an existing circuit of pin electronics. The same parts as those in FIG. The n pin electronics 201, 202,... 20n have a configuration of a normal pin electronics card. Hereinafter, the pin electronics 201 will be described as an example. The comparator 81 is a comparator constituting a driver / comparator for performing pass / fail (hereinafter referred to as P / F) determination for the DUT in a normal pin electronics card. The DA converters 10 and 11 are respectively connected to the comparator 81 on the H side. The reference voltage VOH and the L-side reference voltage VOL are supplied. The active load 12 has a function of drawing current into the DUT according to the magnitude of the DUT output voltage with respect to the reference voltage VREF, and discharging it from the source. The DA converter 13 applies a reference voltage VREF to the active load 12. Here, the input data of the DA converters 10, 11, and 13 are sent from the calibration calculation storage means 1 via the digital signal bus. A DC voltage / current source (Parametric Measurement Unit: hereinafter referred to as PMU) 130 applies and measures voltage and current to the DUT. The TSC 260 controls each level data and calibration data.

  The operation of the apparatus of FIG. 2 will be described below. The comparator 81 performs the same operation as the comparator 8 of FIG. 1 by selecting the reference voltages VOH and VOL equal to the upper limit H-LIM and the lower limit L-LIM of the comparator 8 of FIG. The PMU unit 130 performs the same operation as the voltage measurement unit 30 of FIG. 1 using its voltage measurement function. The comparison output of the comparator 81 is sent to the TSC 260 (not shown) as a good / failed judgment result after being judged as good / bad by the P / F judging means (not shown) as in the detection circuit 9 of FIG. . When the TSC 260 determines whether or not the pin electronics (201) needs to be calibrated, as in the case of the calibration necessity determination circuit 50 of FIG. The control data is transmitted to and received from the level data output circuit 40, the calibration calculation storage means 1, the PMU 130, etc., and the calibration process is started. Here, the TSC 260 constitutes a determination circuit that determines whether or not calibration can be performed based on a signal output from the comparator 81.

  According to the apparatus configured as described above, not only the same effect as in the apparatus of FIG. 1 is produced, but also the hardware of the existing pin electronics card is utilized, so it is necessary to newly add hardware. It can be realized at a lower cost.

In the application example described above, whether the reference voltage VREF of the active load 12 is good or bad may be determined using the comparator 81 in the same manner as the voltages VH and VL.

1 is a configuration block diagram showing an example of a semiconductor test apparatus according to an embodiment of the present invention. FIG. 2 is a configuration block diagram showing an application example of the semiconductor test apparatus of FIG. 1. It is a block diagram which shows the structure of the conventional semiconductor test apparatus. It is a time chart for demonstrating operation | movement of the apparatus of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Calibration calculation memory | storage means 5 Driver 8 Comparator 30 Voltage measurement means 40 Level data output means 50 Discrimination circuit H-LIM, L-LIM Reference value VH, VL Level voltage

Claims (5)

A semiconductor test apparatus having a plurality of pin electronics in which a level voltage corresponding to level data is applied to a DUT via a driver, and the level voltage is calibrated based on the level voltage measured by voltage measuring means and the level data In
A comparator for comparing the level voltage with a reference value;
A semiconductor test apparatus comprising: a discriminating unit that discriminates pin electronics for performing the calibration based on a signal output from the comparator. Calibration calculation storage means for calculating correction data from the difference between the level voltage measured by the voltage measuring means and the level data, and adding the correction data to the level data;
2. The semiconductor test apparatus according to claim 1, further comprising: a DA converter that converts correction level data output from the calibration calculation storage means into a level voltage of the driver.   2. The semiconductor test apparatus according to claim 1, wherein a comparator for pass / fail judgment of the pin electronics is used as the comparator. 2. The semiconductor test apparatus according to claim 1, wherein a DC voltage / current source of the pin electronics is used as the voltage measuring means. A first relay connected between the driver and the DUT;
A second relay connected between the first relay and the voltage measuring means; and performing the calibration by closing the first and second relays of the pin electronics determined by the determination circuit. The semiconductor test apparatus according to claim 1, wherein:

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