JP2008259891A - Ultrasonic diagnostic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide ultrasonic diagnostic apparatus which forms two or more receiving beams in a wave front synchronous sampling phasing method. <P>SOLUTION: This ultrasonic diagnostic apparatus 1 provides a probe 10 which arranges two or more oscillators which send and receive an ultrasonic wave each between the oscillator and a subject, an AD conversion section 32a which synchronizes a received signal received by each oscillator with a sampling clock and converts it into a digital signal, a clock generation section 38 which is synchronized with a receiving wave front and generates the sampling clock, a phasing addition section which phases and adds the digital signal converted by the AD conversion section, and an image composition section which makes up an ultrasonic image from an added received signal. The phasing addition section performs phasing treatment on the digital signal of AD conversion in parallel based on preset two or more receiving beams. The digital signal on two or more receiving beams, where the phasing treatment is performed basis, is added. Two or more receiving beams are formed. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to an ultrasonic diagnostic apparatus, and more particularly to a technique for digitally phasing an ultrasonic reception signal in synchronization with a reception wavefront.

  The ultrasonic diagnostic apparatus has a probe in which a plurality of transducers that transmit and receive ultrasonic waves to and from a subject are arranged, and receives reflected echo signals generated from the subject through the probe. The received signal is sampled and AD-converted as a digital signal, and the converted signal is phased and added to obtain an ultrasonic image.

  As a sampling method of such an ultrasonic diagnostic apparatus, a wavefront synchronous sampling phasing method is known. In the wavefront synchronization sampling phasing method, a plurality of sampling clocks are generated based on the transmission frequency of ultrasonic waves, and a multi-phase sampling clock is generated by applying a small delay equal to or less than the sampling period to the generated sampling clock. A sampling clock synchronized with the reception wavefront is selected from the multiphase sampling clock, and the reception signal is converted into a digital signal.

  In this wavefront synchronization sampling phasing method, a sampling clock having a frequency corresponding to 4n times (n is a natural number) the ultrasonic transmission frequency is used so that complex signals can be easily formed. For example, a sampling clock having a frequency 4n times the center frequency of the transmission signal is generated, and the reception frequency is sampled by the sampling clock. Then, by delaying the data output by sampling by n clocks, a complex signal, that is, a signal composed of a real component and an imaginary component is easily obtained to construct an ultrasonic image (see, for example, Patent Document 1).

JP-A-9-224937

  However, as in Patent Document 1, when the received signal is sampled with the sampling clock generated based on the center frequency of the ultrasonic transmission signal, the phase difference between the sampling data is shifted from a predetermined value. Sometimes. For example, the ultrasonic signal is attenuated when propagating through the subject, and its frequency changes. At this time, if the received signal is sampled with a sampling clock having a frequency four times the transmission frequency even though the frequency has changed, the output data has a desired phase difference, that is, a 90 ° phase difference. Deviation occurs. When a complex signal is extracted by delaying the sampling data by one clock, the extracted complex signal includes an error due to a phase difference shift. As a result, the spatial resolution and sensitivity of the ultrasonic diagnostic apparatus may be reduced.

  An object of the present invention is to improve the spatial resolution and sensitivity by improving the phasing accuracy of an ultrasonic reception signal in the wavefront synchronous sampling phasing method.

  In order to achieve the above object, an ultrasonic apparatus of the present invention includes a probe formed by arranging a plurality of transducers that transmit and receive ultrasonic waves to and from a subject, and a reception signal received by each transducer. An AD converter that converts the signal into a digital signal in synchronization with the sampling clock, a clock generator that generates a sampling clock that is synchronized with the received wavefront, and a phasing of the digital signal converted by the AD converter A phase addition unit and an image configuration unit that configures an ultrasonic image from the added reception signal are included, and the clock generation unit includes a unit that generates a sampling clock based on the frequency of the reception signal.

  According to this, when the ultrasonic wave propagates through the medium in the subject and the frequency band changes, the sampling clock can be generated by the clock generation unit following the frequency change. Therefore, even if the frequency of the ultrasonic wave changes in the medium, the received signal can be sampled at a desired sampling frequency by the AD converter. Therefore, the phase difference between the data having a complex relationship in the sampling data can be accurately adjusted to a predetermined value, for example, 90 °, so that a complex signal with little error can be obtained. As a result, the phase accuracy for phasing the reception frequency can be improved and the spatial resolution and sensitivity in the ultrasonic diagnostic apparatus can be improved compared to when the sampling clock is generated based on the transmission frequency. .

  For example, a sampling clock is generated so as to have a frequency corresponding to four times the frequency of the received signal, and the received signal is sampled by the generated sampling clock. As a result, a predetermined phase difference, that is, a 90 ° phase difference (1/4 wavelength phase difference) is accurately guaranteed between adjacent data among data to be output, that is, data having a complex relationship. Therefore, if a set of two data having a complex relationship is extracted and converted into a complex signal, a complex signal with few errors can be obtained.

  Further, instead of a sampling clock having a frequency corresponding to four times the frequency of the received signal, a sampling clock having a frequency corresponding to 4n times (n: natural number) may be generated. At this time, the two data having a complex relationship are shifted by n clocks, and a 90 ° phase difference is accurately guaranteed between the data. Therefore, a complex signal with few errors can be obtained by delaying data having the phase difference by n clocks.

  In this case, the configuration of the clock generation unit that generates a sampling clock having a frequency corresponding to four times the frequency of the reception signal includes means for generating a sampling clock according to the reception frequency, and samples the sampling clock of the generated frequency. A means for generating a plurality of sampling clocks delayed by a minute time equal to or less than a period, and a sampling clock synchronized with the reception wavefront from the plurality of delayed sampling clocks are selected and given to an AD converter corresponding to the received signal Means. Furthermore, it is preferable to provide means for detecting the frequency of the received signal in order to generate a sampling clock according to the received frequency. In this way, the clock generation unit can generate the sampling clock following the frequency of the received signal. Therefore, by sampling the generated sampling clock in synchronization with the reception wavefront, the reception signal can be sampled at a desired sampling frequency even if the frequency band of the transmission signal changes in the medium. As a result, a complex signal with few errors can be obtained by delaying the sampling data to convert it into a complex signal.

Further, it is preferable to cause the phase correction unit to correct the phase of the digital signal converted by the AD conversion unit based on a set phase correction coefficient. Thereby, the phasing addition part can adjust a phase finer than the period of the frequency of a sampling clock, before adding a digital signal. Therefore, it is possible to further improve the phase accuracy for phasing, extract a complex signal without error, and further improve the spatial resolution and sensitivity of the ultrasonic diagnostic apparatus.
For example, the phase φ (t) that is finer than the time interval Δt obtained by dividing the period of the frequency four times the ultrasonic reception frequency by k is adjusted. As a result, the phase accuracy for phasing the ultrasonic reception signal is improved, and the spatial resolution and sensitivity of the ultrasonic device are further improved.

  The phase correction unit includes a delay unit that delays a received signal by 90 ° phase difference, that is, a ¼ wavelength phase difference, a phase correction coefficient generation unit that generates phase correction data, and data and a phase correction coefficient from the delay unit. It is preferable to provide a complex multiplication unit that performs complex multiplication on data from the generation unit. Further, a delay unit that delays to a phase difference, that is, a quarter wavelength phase difference, a LookUpTable (LUT) that includes a memory such as SRAM, and a LUT address control unit such as a counter may be included.

  By the way, as the ultrasound imaging method, there are known a biological non-linear imaging method and a contrast harmonic imaging method that form an image based on a reception frequency of a harmonic. For example, the biological nonlinear imaging method is to image a reflected signal having a transmission frequency, that is, a harmonic frequency such as twice or three times the fundamental frequency, as ultrasonic waves propagate through a nonlinear medium such as a living body. . In contrast, the harmonic imaging method is a method of injecting bubbles of about several tens of μm or oily microbubbles into blood vessels and generating harmonic emission frequencies such as twice or three times the incident frequency emitted by the microbubbles. A reflected signal is received, and a good blood flow image is obtained from the reflected signal.

  As described above, there is a case where it is desired to simultaneously extract a plurality of bands of harmonic components derived from a living body or a contrast medium and form an image. In this case, it is preferable to provide a phasing addition unit that phasing multiple frequency bands at the same time. Furthermore, it is preferable that the phasing addition unit is provided with a phase correction unit corresponding to the number of frequencies extracted from the harmonic component and a band filter for removing unnecessary frequency bands from the signal of the phase correction unit.

  For example, the received signal is received by the vibrator, the received signal is digitized by the AD conversion unit, the digital signal is delayed by the delay unit, and the delayed signal is obtained from a plurality of phase correction units, that is, harmonic components. Preferably, the phase correction unit corresponding to the number of frequencies to be extracted is phase-corrected for each high-frequency component, and the phase-corrected signal is filtered by the bandpass filter.

  Thereby, a plurality of frequency bands can be simultaneously processed and imaged for each high frequency component. For example, when extracting the second harmonic component and the third harmonic component from the harmonic and imaging them simultaneously, a part of the plurality of phase correction units is allocated for the second harmonic, and other phase correction units are Assign for the third harmonic. Thus, if each phase correction unit is controlled and filtered, each harmonic wave front of the received signal can be phased simultaneously and accurately, so that the second harmonic component and the third order processed simultaneously. It is possible to further improve the spatial resolution and sensitivity of the harmonic component image.

  According to the present invention, in the wavefront synchronous sampling phasing method, it is possible to improve the phasing accuracy of the ultrasonic reception signal and improve the spatial resolution and sensitivity.

  An embodiment of an ultrasonic diagnostic apparatus to which the present invention is applied will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration example of an ultrasonic diagnostic apparatus to which the present invention is applied. FIG. 2 shows a configuration example of the phasing addition unit, and FIG. 3 shows a configuration example of the sampling clock generation unit. FIG. 4 shows a configuration example of the delay control unit.

  As shown in FIG. 1, the ultrasonic diagnostic apparatus 1 includes a probe 10 in which a plurality of transducers that transmit and receive ultrasonic waves to and from a subject are arranged, and an ultrasonic wave for the probe 10. A transmission unit 12 that generates a transmission signal for transmitting the signal and a reception unit 14 that receives and amplifies a reflected echo signal generated from the subject are provided. In addition, a phasing addition unit 16 that phasing and adding the signal amplified by the reception unit 14 to the ultrasonic wave front, and extracting information such as ultrasonic intensity and ultrasonic frequency from the phased and added reception signal And a signal processing unit 18 for performing the processing. And the image processing part 20 which comprises an ultrasonic image from the information extracted by the signal processing part 18 and the display part 22 which displays the comprised image are provided. Moreover, the control part 24 which controls each structure part is provided.

  As shown in FIG. 2, the probe 10 includes a plurality of transducers 26a to 26m that transmit and receive ultrasonic waves, a plurality of variable gain amplifiers (VGA) 28a to 28m respectively corresponding to the transducers 26a to 26m, and a variable gain. A plurality of band control filters (AAF) 30a to 30m corresponding to each of the amplifiers 28a to 28m are configured. Here, the transducers 26a to 26m constitute an ultrasonic receiving aperture and receive an ultrasonic signal. Further, for example, the variable gain amplifier 28a is for correcting the signal attenuation during propagation through the medium with respect to the reception signal received by the transducer 26a. For example, the band control filter 30a limits the pass band of the signal that has been attenuation-corrected by the variable gain amplifier 28a to suppress aliasing in the frequency space.

  The phasing addition unit 16 includes a plurality of AD conversion units (ADC) 32a to 32m corresponding to the variable gain amplifiers 30a to 30m, a plurality of delay units 34a to 34m respectively corresponding to the ADCs 32a to 32m, and a delay unit. Phase correction units 36a to 36m respectively corresponding to 34a to 34m, a clock generation unit 38 for generating a sampling clock clock to be applied to each of the ADCs 32a to 32m, a delay control unit 40 for controlling the delay units 34a to 34m, and a phase The phase correction control unit 42 that controls the correction units 36a to 36m and the addition unit 44 that adds the reception signals output from the phase correction units 36a to 36m are configured. Here, for example, the ADC 32a samples the analog signal output from the band control filter 30a with the sampling clock from the clock generation unit 38 and converts it into a digital signal. In addition, for example, the delay unit 34a delays the received signal from the ADC 32a by an integral multiple of the sampling clock period based on a command from the delay control unit 40. Further, for example, the phase correction unit 36a finely adjusts the phase of the ultrasonic reception signal from the delay unit 34 based on the phase correction data from the phase correction control unit 42 to make the wave front of the reception signal in-phase. is there.

The clock generator 38 is synchronized with the wavefront of the received signal received by the probe 10 and has a frequency (hereinafter, 4nf ₀ ) 4n times (n: natural number) with respect to the center frequency (f ₀ ) of the received signal. .) Is generated and given to the AD converter 32a, for example. The delay control unit 40 outputs a control signal to, for example, the delay unit 34a according to the reception timing of the ultrasonic signals of the transducers 26a to 26m. The phase correction control unit 42 outputs phase correction data based on desired phase accuracy to, for example, the phase correction unit 36a.

  The operation of the ultrasonic diagnostic apparatus configured as described above will be described. In the ultrasonic diagnostic apparatus 1, an ultrasonic wave is transmitted to the subject via the probe 10, a reflected echo signal generated from the subject is received by the receiving unit 14, and the received reception signal is the phasing addition unit 16. Is subjected to phasing and addition, and an ultrasonic image is constructed by the image construction unit 20 from the phased and added received signals, and the constructed image is displayed on the display unit 22.

Here, the clock generation unit 38 will be described in detail with reference to FIG. The clock generation unit 38 generates a sampling clock having a frequency 4n times the frequency of the ultrasonic reception signal, a 4nf ₀ generation unit 46, and a phase delay unit 48 that delays the sampling clock from the 4nf ₀ generation unit 46. A clock selection unit 50 that selects a sampling clock from the phase delay unit 48 and applies the sampling clock to the ADCs 32a to 32m, a 4nf ₀ generation unit 46, a phase delay unit 48, and a control unit 52 that controls the clock selection unit 50. It is configured.

Here, the 4nf ₀ generator 46 includes an oscillator 54 formed of a crystal oscillator, a frequency divider 56 formed of a register, a DLL, and the like, counters 58a to 58i driven by outputs from the frequency divider 56, and a frequency divider And a clock selector 60 driven by the output from 56.

  The phase delay unit 48 instructs the control unit 52 to select one delay line, for example 62a, from the pulse delay lines 62a to 62j having k taps that are delayed by a minute time Δt that is equal to or less than the sampling period, and the delay lines 62a to 62j. The delay line selector 64 is selected according to The clock selection unit 50 includes clock selectors 66a to 66m that output the clock delayed by the phase delay unit 48 to a predetermined ADC based on a command from the control unit 52.

The control unit 52 writes an address determination unit 68 connected to the bus, an address counter 70, an address selector 74 that outputs a predetermined address according to a signal from the address determination unit 68 or the address counter 70, and a request from the bus A data buffer 72 that controls whether the data flows or not, and a storage element such as SRAM or DRAM, and a delay of the clock selector 60 and the phase delay unit 64 of the 4nf ₀ generation unit 46 Data holding units 76a to 76m that hold data for controlling the line selector 64 and the clock selectors 66a to 66m of the clock selection unit 50 are configured.

The operation of the clock generation unit 48 configured as described above will be described. First, an operation for generating a 4nf ₀ clock will be described. In the 4nf ₀ generator 46, the oscillator 54 generates a master clock (mclk). The generated master clock is frequency-divided into a frequency-divided clock (sclk) by the frequency divider 56. The frequency-divided clock is input to the counters 58a to 58i and the clock selector 60 as a drive clock. Each counter is counted by the counters 58a to 58i to which the drive clock is input, and a plurality of i 4nf _0s having different frequencies are generated. Here, the frequency can be arbitrarily generated by adjusting the degree of frequency division and the number of counters. Then, one 4nf ₀ is selected from the plurality of 4nf _0s generated by the counters 58a to 58i by the clock selector 60 in accordance with the frequency shift that occurs when the ultrasonic wave propagates through the medium. That is, the frequency of the ultrasonic reception signal is detected, and the sampling clock closest to the sampling clock having a frequency 4n times the detected reception frequency is selected from the generated i 4nf _0s . By such a procedure, 4nf ₀ clock is generated.

Next, the operation of the phase correction unit 48 will be described. As for the 4nf ₀ clock selected by the clock selector 60, for example, a plurality of 4nf ₀ clocks having different phases are generated by a pulse delay line 62a at a minute time Δt ₁ interval equal to or less than the sampling period. In this case, the delay line selector 64 selects the pulse delay line 62a from the pulse delay lines 62a to 62j so as to have a minute time Δt that is equal to or less than the sampling period of the frequency at which the ultrasonic wave has propagated through the medium and changed. Yes. According to such a procedure, a 4nf ₀ clock having a plurality of k phases delayed by a pulse delay line having a desired Δt is obtained.

The operation of the clock selector 50 will be described. A plurality of k phases of the different 4nF ₀ clock following the short time Δt interval sampling cycle obtained by the delay line selector 64, and most synchronized 4nF ₀ clock to the wavefront of the received signal received by the transducer 26a~26m Is selected by the clock selector 66a, for example. Then, the selected 4nf ₀ clock is applied to the ADC 32a, for example.

The control unit 52 will be described. The address determination unit 68 determines whether the address is a predetermined address for storing control data. If the address is a predetermined address, the control data is output to the data holding unit 76a via the address selector 74, for example. The data buffer 72 determines whether the request from the bus is a write or a read, and controls the data flow direction. The address counter 70 changes the count value with 4nf ₀ clock at the timing when the ultrasonic wave propagates through the medium, thereby generating the read address of the data holding unit 76a. Then, the address selector 74 selects the addresses from the address counter 70 and the address determination unit 68 according to the determination, for example, as the address of the data holding unit 76a.

That is, in the control unit 52, the control data is written at a predetermined address by the address determination unit 68 using BUS. Then, the count value of the address counter 70 is changed at 4nf ₀ clock at the timing at which the ultrasonic wave propagates through the medium, and a read address is generated from the count value. Based on the generated address, control data is read from the data holding units 76a to 76m via the address selector 74. The read control data controls the clock selector 60, the delay line selector 64, and the clock selectors 66a to 66m. In addition, although the control part 52 using the data holding parts 76a-76m which consist of volatile memory elements was demonstrated, it replaces with this and may use the data holding part which consists of non-volatile ROM for a control part.

  As described above, when the ultrasonic wave propagates through the medium in the subject and the frequency thereof changes, the clock generation unit 38 can generate the sampling clock following the frequency change. At this time, the generated sampling clock has a frequency 4n times the ultrasonic reception frequency and is accurately synchronized with the wavefront of the reception signal. Therefore, even if the frequency of the ultrasonic wave changes in the medium, the received signal can be accurately sampled at a desired sampling frequency, for example, by the ADC 32a. Therefore, the phase difference between the output data can be accurately adjusted to a predetermined value, for example, 90 ° phase difference, and if the data is subjected to delay processing for the set clock, a complex signal with less error can be obtained. . As a result, the phase accuracy for phasing the received signal compared to the case where a sampling clock is generated based on the transmission frequency for a signal or nonlinear signal whose frequency caused by attenuation caused by propagation of ultrasonic waves through the medium And the spatial resolution and sensitivity of the ultrasonic diagnostic apparatus can be improved.

  Here, the delay units 34 a to 34 m and the delay control unit 40 in the phasing addition unit 16 will be described with reference to FIG. 4. Each of the delay units 34a to 34m is composed of a storage element such as SRAM or DRAM. The delay control unit 40 includes an address determination unit 78 connected to the bus, an address counter 82, an address selector 80 that outputs a predetermined address according to a signal from the address determination unit 78 or the address counter 82, and a request from the bus. It includes a data buffer 81 that determines whether data is written or read and controls the direction of data flow, and a delay data memory 83 that holds delay data based on the address from the address selector 80. Further, the write permission unit 84 that changes the address value of the write address generation units 88 a to 88 m based on the delay data of the delay data memory 83, and the read address generation units 90 a to 90 m based on the delay data of the delay data memory 83. And a read permission unit 86 for changing the address value. Here, the delay data memory 83 is composed of a memory such as an SRAM or a DRAM, and the write permission unit 84 and the read permission unit 86 are composed of a logic gate, an LUT, or the like. The write address generators 88a to 88m are composed of a counter or the like.

  First, similarly to the control unit 52 of the clock generation unit 38 shown in FIG. 3, the delay control unit 40 uses the address determination unit 78, the address counter 82, the data buffer 81, and the address selector 80 to specify a predetermined address via Bus. Sometimes delay data is written into the delay data memory 83. Then, the delay data memory 83 is read with the address counter value at the timing when the ultrasonic wave propagates through the medium. In the read delay data, the address values of the write address generation units 88a to 88m and the read address generation units 90a to 90m are changed according to the states of the write permission unit 84 and the read permission unit 86. Further, the write permission unit 84 and the read permission unit 86 output permission signals WENA and RENA and clocks WCLK and RCLK to the delay unit 34a, for example, according to the respective states.

  In addition, although the delay control part 40 shown by FIG. 4 was demonstrated, it is not restricted to this. For example, FIG. 5 shows another configuration example of the delay control unit. As shown in FIG. 5, when each of the delay units 34a to 34m includes a shift register 92 to which the reception signals from the ADCs 32a to 32m are input and a selector 93 to which the signal from the shift register 92 is input, delay control is performed. The unit 41 does not use the write permission unit 84, the read permission unit 86, the write address generation units 88a to 88m, and the read address generation units 90a to 90m illustrated in FIG. An address selector 80, a data buffer 81, an address counter 82, and a delay data memory 83 composed of a memory such as SRAM or DRAM are included.

According to the delay units 34a to 34m and the delay control unit 40, the frequency is 4n times the frequency of the ultrasonic reception signal, and the frequency is 4nf ₀ clocks synchronized with the wavefront of the ultrasonic reception signal. Coarse delay processing can be performed on the sound wave reception signal, and in-phase of the ultrasonic wave reception signal can be achieved.

  Next, the phase correction units 36a to 36m and the phase correction control unit 42 will be described with reference to FIGS. FIG. 6 shows a configuration example of the phase correction unit 36a, and FIG. 7 shows a configuration example of the phase correction control unit. As shown in FIG. 6, the phase correction unit 36 a includes a delay unit 94 including a shift register and a complex multiplication unit 95 that multiplies the complex signal from the delay unit 94 and the phase correction data. At this time, the complex multiplication unit 95 multiplies the real number component of the ultrasonic reception signal x (t) by the real number component of the correction data, the real number component of the ultrasonic reception signal x (t), and the imaginary number of the correction data. A multiplication unit 96b that multiplies the components, a multiplication unit 96c that multiplies the imaginary number component of the ultrasonic reception signal x (t) and the real number component of the correction data, an imaginary number component of the ultrasonic reception signal x (t) and the imaginary number of the correction data A multiplication unit 96d that multiplies the components; an addition unit 100a that adds a result obtained by inverting the multiplication result of the multiplication unit 96b by the sign inversion unit 98 and a multiplication result of the multiplication unit 96c; and a multiplication result of the multiplication unit 96a and a multiplication unit 96d. And an addition unit 100b for adding the multiplication results of the above.

  Further, as shown in FIG. 7, the phase correction control unit 42 outputs an address determination unit 102 connected to the bus, an address counter 104, and a predetermined address by a signal from the address determination unit 102 or the address counter 104. A selector 108, a data buffer 106 that determines whether the request from the bus is a write or a read and controls the direction of data flow, and a phase correction memory 110 that holds phase data based on the address from the address selector 108 It is comprised including. A shift register 112 and latch registers 113a to 113m are provided following the phase correction memory 110. Here, the phase correction memory 110 includes a storage element such as SRAM or DRAM.

  Thus, the phase correction data is output to the phase correction unit 36a by the phase correction control unit 42. That is, the phase correction control unit 42, as with the control unit 52 of the clock generation unit 38 shown in FIG. Phase correction data is written into the phase correction memory 110 at the time of addressing. Then, the phase correction data stored in the phase correction memory 110 is read as an address counter value at the timing when the ultrasonic wave propagates through the medium. The read phase correction data is shifted by the shift register 112 to hold the data in the latch registers 113a to 113m corresponding to the transducers 26a to 26m, respectively. The shifted phase correction data is held at the latch timing by the latch registers 113a to 113m and output to the phase correction unit 36a.

On the other hand, in the phase correction unit 36a, the ultrasonic reception signal is delayed by n clocks by the delay unit 94 operating at 4nf ₀ clock, and a complex signal is extracted. The extracted complex signal and the phase correction data from the phase correction control unit 42 are complex multiplied by the complex multiplication unit 95. Thereby, since the phase of the ultrasonic reception signal is corrected based on the phase correction data, the phasing accuracy can be improved.

Such complex multiplication processing will be described using mathematical expressions. When the ultrasonic reception signal x (t) is expressed as shown in Equation 1, since the reception signal x (t) is delayed by n clocks by the delay unit 94, the delayed reception signal x (t−n) is expressed by Equation 2. It is expressed as an expression. Here, since the sampling frequency is 4 nf ₀ clock, the relationship of Formula 3 is established. Further, when the amplitude A (t) is approximated to A (t−n), x (t−n) is expressed by the following equation (4). Therefore, since Formula 1 and Formula 4 have a complex relationship, they are expressed as Formula 5. That is, as shown in Equation 5, the ultrasonic reception signal x (t) is delayed by n clocks by the delay unit 94 and becomes complex data. Further, when the phase correction data output from, for example, the latch register 113a of the phase correction control unit 42 is expressed as Equation 6, the output Y (t) of the complex multiplier 95 that multiplies Equation 6 and Equation 5 is , As shown in Equation 7. That is, as shown in Equation 7, the output Y (t) from the complex multiplier 95 becomes a value corrected by phase rotation by the phase φ (t).

このように位相補正部３６ａ〜３６ｍは、Δｔ間隔より微少な位相φ（ｔ）に基づいて位相を調整することができるので、超音波受信信号の整相精度をより一層向上させることができる。ここで、Δｔとは、クロック生成部３８により超音波受信周波数の４ｎ倍の周波数の周期がｋ分割された時間間隔をいう。したがって、例えば、所望の位相精度が波長λ／１２８である場合、ｎ＝４、ｋ＝４、φ（ｔ）分割数＝２とすることによりその位相精度を得ることができる。また、超音波受信信号の高調波撮像において高周波数帯域を画像化するとき、ｎを大きく取れずに超音波受信信号の整相精度が低下する場合がある。例えば、ＡＤＣ３２ａの最大サンプリング周波数が６０Ｍｈｚで、超音波受信周波数が１５Ｍｈｚの場合、ｎ＝１となるので整相精度が低下する。この場合、φ（ｔ）分割数＝８とすることにより、λ／１２８の位相精度を実現することができる。このように、位相補正部３６ａによれば、高周波数帯域を画像化する場合、位相精度を改善することができる。

As described above, the phase correction units 36a to 36m can adjust the phase based on the phase φ (t) that is finer than the Δt interval, so that the phasing accuracy of the ultrasonic reception signal can be further improved. Here, Δt means a time interval obtained by dividing the period of the frequency 4n times the ultrasonic reception frequency into k by the clock generation unit 38. Therefore, for example, when the desired phase accuracy is the wavelength λ / 128, the phase accuracy can be obtained by setting n = 4, k = 4, and φ (t) division number = 2. Further, when imaging a high frequency band in harmonic imaging of an ultrasonic reception signal, there may be a case where n is not large and the phasing accuracy of the ultrasonic reception signal is lowered. For example, when the maximum sampling frequency of the ADC 32a is 60 Mhz and the ultrasonic reception frequency is 15 Mhz, since n = 1, the phasing accuracy decreases. In this case, the phase accuracy of λ / 128 can be realized by setting the φ (t) division number = 8. Thus, according to the phase correction unit 36a, the phase accuracy can be improved when imaging a high frequency band.

  As described above, according to the present embodiment, when the ultrasonic wave propagates through the medium in the subject and the frequency changes, the sampling clock can be generated by the clock generation unit 38 following the frequency change. Therefore, even if the frequency of the ultrasonic wave changes in the medium, the reception signal can be sampled by the ADCs 32a to 32m with a sampling clock having a frequency 4n times the reception frequency. Therefore, the phase difference between data having a complex relationship in the output data can be 90 °. If the data is delayed by n clocks by the delay units 34a to 34m, a complex signal with few errors can be obtained. As a result, the spatial resolution and sensitivity of the ultrasonic diagnostic apparatus can be improved.

  Further, since the phase adjusting and adding unit 16 finely adjusts the phase by the phase correcting units 36a to 36m before adding the digital signals, the phase adjusting accuracy can be improved. The sound wave reception signal can be further in phase. For example, when making an ultrasonic reception signal in-phase, not only phasing by a time interval Δt obtained by dividing a period of four times the ultrasonic reception frequency by k, but also adjusting a phase φ (t) slightly smaller than Δt By doing so, phasing can be performed. As a result, since the phasing accuracy is improved, the spatial resolution and sensitivity of the ultrasonic apparatus can be further improved.

  Furthermore, conventionally, when imaging a high frequency band in harmonic imaging of an ultrasonic reception signal, the value of n may not be large and the phasing accuracy may be reduced. However, if the number of phase divisions is adjusted by the phase correction units 36a to 36m, desired phase accuracy can be obtained. That is, since the phase correction accuracy of the phasing addition unit 16 can be improved by the phase correction units 36a to 36m, spatial resolution and sensitivity can be improved also in harmonic imaging.

Although the present embodiment has been described above, the present invention is not limited to this. For example, FIG. 8 shows another embodiment of the phase correction unit and the phase correction control unit. As shown in FIG. 8, the phase correction unit 120 includes a delay unit 122 that applies a 90 ° phase delay to the ultrasonic reception signal X (t) and an LUT 124 that performs complex multiplication processing. The phase correction control unit 114 includes a counter 116 that counts in synchronization with 4nf ₀ clocks during the ultrasonic reception period to generate the address of the LUT 124, and a delay unit 118 that delays the 4nf ₀ clocks by p clocks. Has been. Here, the delay unit 122 is configured by a shift register or the like, and the LUT 124 is configured by a storage element such as SRAM or DRAM.

In the phase correction control unit 114 and the phase correction unit 120 as described above, the counter 116 generates an address of the LUT 124 by counting in synchronization with 4nf ₀ clock during the ultrasonic wave reception period. Further, the delay unit 118 delays the p clock so that the phase is delayed by 90 ° from the signal of the counter 116. Thereby, desired complex phase correction data can be generated.

  Then, the phase of the ultrasonic reception signal is corrected based on the generated correction data. For example, the ultrasonic reception signal X (t) is delayed by n clocks by the delay unit 122 and becomes a complex signal. The complex signal from the delay unit 122 is complex-multiplied by the phase correction data from the phase correction control unit 144 and the LUT 124. Therefore, the output from the LUT 124 is an ultrasonic reception signal Y (t) whose phase is corrected.

  Further, another embodiment of the phase correction unit and the phase correction control unit will be described with reference to FIGS. 9 and 10. FIG. 9 shows a configuration example of the phase correction unit, and FIG. 10 shows a configuration example of the phase correction control unit. As shown in FIG. 9, the phase correction unit 126 has a configuration similar to the phase correction unit 36a shown in FIG. That is, the phase correction unit 126 includes a delay unit 94 including a shift register and the complex multiplication unit 95. The complex multiplication unit 95 includes multiplication units 96a to 96d, a sign inversion unit 98, and addition units 100a and 100b.

  Further, as shown in FIG. 10, the phase correction control unit 128 has a configuration similar to the phase correction control unit 42 shown in FIG. That is, the phase correction control unit 42 includes an address determination unit 102, an address counter 104, a data buffer 106, an address selector 108, and a phase correction memory 110 made of a storage element such as SRAM or DRAM. .

In the phase correction control unit 36a in FIG. 6, the output data from the delay unit 34 is corrected using the phase correction data e ^{jφ (t)} as the correction data. However, in the phase correction unit 126 in FIG. Instead, the output data from the delay unit 34 is corrected using the frequency correction data e ^{−j (2πfs (t) t)} from the phase correction control unit 128. That is, the ultrasonic reception signal X (t) is subjected to n clock delay processing by the delay unit 34 to become a complex signal. By multiplying the complex signal from the delay unit 34 and the frequency correction data from the phase correction control unit 128 by the complex multiplication unit 95, an output Y (t) whose frequency is corrected can be obtained. At this time, the output Y (t) is expressed as shown in Equation 8. Therefore, since the frequency band of the ultrasonic reception signal can be moved based on the predetermined frequency correction data, the phase for phasing can be achieved even when the ultrasonic signal is attenuated in the medium and the frequency band is shifted. Accuracy can be improved. As a result, the spatial resolution and sensitivity of the ultrasonic device can be improved. Here, if f _s = f ₀ , the ultrasonic reception frequency band is shifted to the baseband. Further, in the case of n = 2, it can be realized by repeating the eight values shown in Equation 9.

  Another embodiment of the phase correction unit and the phase correction control unit will be described with reference to FIGS. FIG. 11 shows a configuration example of the phase correction unit, and FIG. 12 shows a configuration example of the phase correction control unit. The phase correction unit 130 shown in FIG. 11 is configured similar to the phase correction unit 36a shown in FIGS. That is, the phase correction unit 130 includes a delay unit 94 including a shift register and the complex multiplication unit 95. The complex multiplication unit 95 includes multiplication units 96a to 96d, a sign inversion unit 98, and addition units 100a and 100b. The phase correction control unit 132 illustrated in FIG. 12 is configured similarly to the phase correction control unit 42 illustrated in FIGS. 7 and 10. That is, the phase correction control unit 132, the phase correction control unit 42, the address determination unit 102, the address counter 104, the data buffer 106, the address selector 108, and the phase correction memory 110 including storage elements such as SRAM and DRAM, It is comprised including.

The phase correction unit 36a in FIG. 6 performs correction using the phase correction data e ^{jφ (t)} as the correction data, and the phase correction control unit 128 in FIG. 10 performs frequency correction data e ^{−j (2πfs (t) t).} It is decided to perform correction using. Instead, the phase correction unit 130 shown in FIG. 11 performs correction using a value e ^{−j (2πfs (t) + φ (t))} obtained by multiplying the phase correction data and the frequency correction data. . At this time, the output Y (t) of the complex multiplication unit 95 is expressed as in Expression 11. That is, since the ultrasonic reception signal is corrected by the frequency correction data simultaneously with the phase correction data, the phase accuracy for phasing can be further improved. As a result, the spatial resolution and sensitivity of the ultrasonic apparatus can be further improved.

また、図１３を用いて位相補正制御部の他の実施例を説明する。図１３は、超音波受信信号の位相と周波数を補正する補正制御部１３３の構成例を示している。補正制御部１３３は、位相補正データを出力する位相補正制御部１３４と、周波数補正データを出力する周波数補正制御部１３６と、位相補正データと周波数補正データを複素乗算する乗算部１３８とを含んで構成されている。

Another embodiment of the phase correction control unit will be described with reference to FIG. FIG. 13 shows a configuration example of the correction control unit 133 that corrects the phase and frequency of the ultrasonic reception signal. The correction control unit 133 includes a phase correction control unit 134 that outputs phase correction data, a frequency correction control unit 136 that outputs frequency correction data, and a multiplication unit 138 that multiplies the phase correction data and the frequency correction data. It is configured.

  Similarly to the phase correction control unit 42 shown in FIG. 7, the phase correction control unit 134 includes a phase determination unit 102, an address counter 104, a data buffer 106, an address selector 108, and a phase composed of storage elements such as SRAM and DRAM. The correction memory 110, the shift register 112, and latch registers 113a to 113m are included. The frequency correction control unit 136 includes an address determination unit 102, an address counter 104, a data buffer 106, an address selector 108, and a frequency memory 140 made up of storage elements such as SRAM and DRAM. The multiplier 138 includes a complex multiplier 138a that multiplies the real component of the complex signal and a complex multiplier 138b that multiplies the imaginary component of the complex signal.

  In the correction control unit 133 configured as described above, the multiplication unit 138 multiplies the phase correction data from the phase correction memory 110 and the frequency correction data from the frequency memory 140. The multiplied correction data is output to, for example, the phase correction unit 36a. Therefore, the phasing accuracy of the ultrasonic reception signal can be improved based on the correction data from the correction control unit 133. Thus, in the correction control unit 133, the phase correction memory 110 and the frequency memory 140 can be provided separately.

  Further, another embodiment of the phasing adder will be described with reference to FIG. In the phasing addition unit 16 of FIG. 2, phase correction units 36 a to 36 m are provided corresponding to the number of transducers 26 a to 26 m. Instead, the phasing addition unit 142 of FIG. The number of phase correction units 146a to 146m and 147a to 147m is provided by multiplying the number of frequency bands to be used by the number of transducers 26a to 26m. That is, in the phasing adder 16 of FIG. 2, the number of installed transducers 26a to 26m is equal to the number of installed phase correcting units 36a to 36m, whereas in the phasing adder 142 of FIG. 14, the transducers 26a to 26m. The number of phase correction units 144a to 144m and 145a to 145m corresponding to twice the number of installed is provided.

  As shown in FIG. 14, the phasing addition unit 142 includes AD conversion units 32a to 32m corresponding to the number of transducers 26a to 26m, and delay units 34a to 34m corresponding to the number of AD conversion units 32a to 32m. It has been. Then, two phase correction units are provided in the subsequent stage of each of the delay units 34a to 34m. For example, a phase correction unit 144a and a phase correction unit 145a are provided after the delay unit 34a, and a phase correction unit 144m and a phase correction unit 145m are provided after the delay unit 34m. Further, filters 146a to 146m and 147a to 147m are provided corresponding to the number of phase correction units 144a to 144m and 145a to 145m. For example, a filter 146a is attached to the phase correction unit 144a, and a filter 147a is attached to the phase correction unit 145a. Further, the number of rate conversion units 148a to 148m equal to the number of AD conversion units 32a to 32m are provided in the subsequent stage of the filters 146a to 146m and 147a to 147m. For example, the outputs of the filters 146a and 147a are input to the rate conversion unit 148a, and the outputs of the filters 146m and 147m are input to the rate conversion unit 148m. An adder 44 that adds the outputs from the rate converters 148a to 148b is provided. Note that the filters 146a to 146m are configured by band-pass filters such as FIR filters and IIR filters. The rate conversion units 148a to 148m are configured by a decimator, a selector, and the like.

The phasing addition unit 142 configured in this way can image two types of frequency bands. For example, a reflected signal having a harmonic frequency that is twice or three times the transmission frequency (fundamental frequency f ₀ ) as a result of ultrasonic waves propagating through a non-linear medium such as a living body may be imaged as in the case of non-linear biological imaging. . At this time, if a common multiple of 4nf ₀ of each harmonic frequency, for example, 24f ₀ is set, the sampling clock can be set with n = 3 for the second harmonic and n = 4 for the third harmonic. The ultrasonic reception signals are sampled by the ADCs 32a to 32m by the set sampling clock. At this time, the phase correction units 144a to 144m are assigned and controlled for the second harmonic, and the phase correction units 145a to 145m are assigned and controlled for the third harmonic. As a result, phasing can be performed on each harmonic wave front of the ultrasonic reception signal, and two types of frequency bands can be simultaneously imaged.

  That is, according to the phasing addition unit 142 of the present embodiment, it is possible to have a sufficient sampling frequency with respect to the reception frequency desired for the imaging method using harmonics, and to receive each of the transducers 26a to 26m. The phase accuracy for phasing the signal can be improved. Furthermore, a plurality of high frequency components can be imaged by simultaneously extracting a plurality of bands of harmonic components derived from a living body or a contrast medium.

  Further, since the filtered signal is decimated by, for example, the rate by ½ by the rate conversion units 148a to 148m and converted into one signal and two time series signals, the circuit scale of the signal processing unit 18 installed in the subsequent stage is reduced. Can be reduced.

  Further, another embodiment of the phase correction unit will be described with reference to FIG. FIG. 15 shows a configuration example of the phase correction unit 143 that simultaneously processes two types of frequency bands. In the phase correction unit 142 of FIG. 14, each component is provided in the order of, for example, the phase correction unit 144a, the filter 146a, the rate conversion unit 148a, and the addition unit 44, whereas in the phase correction unit 143 of FIG. Each component is provided in the order of a phase correction unit 144a, an addition unit 150a, a filter 152a, and a rate conversion unit 154.

  That is, as illustrated in FIG. 15, the phase correction unit 143 is provided with ADCs 32 a to 32 m that sample ultrasonic reception signals and delay units 34 a to 34 m corresponding to the number of ADCs 32 a to 32 m. Also, one phase correction unit 144a to 144m assigned to the second harmonic and one phase correction unit 145a to 145m assigned to the third harmonic are provided for each of the delay units 34a to 34m. For example, the delay unit 34a includes a phase correction unit 144a and a phase correction unit 145a, and the delay unit 34m includes a phase correction unit 144m and a phase correction unit 145m. An adder 150a that adds the outputs from the phase correctors 144a to 144m and an adder 150b that adds the outputs from the phase correctors 145a to 145m are provided. Further, a filter 152a is provided at the subsequent stage of the adder 150a, and a filter 152b is provided at the subsequent stage of the adder 152b. A rate conversion unit 154 that performs rate conversion between the output from the filter 152a and the output from the filter 152b is provided. With this configuration, the number of filters and rate conversion units can be reduced as compared with the case of the phase correction unit 142 shown in FIG.

  14 and 15, the phase correction unit 142 and the phase correction unit 143 in the case of imaging two types of frequency bands have been described. However, the present invention is not limited to this. For example, when imaging three or more types of frequency bands, the number of phase correction units, addition units, filters, and the like may be increased as necessary.

  Another embodiment of the phase correction unit will be described with reference to FIG. FIG. 16 shows a configuration example of the phase correction unit 143 when two reception beams are formed. The phase correction unit 156 is provided with ADCs 32a to 32m corresponding to the number of transducers, and each ADC is provided with one delay unit 158a to 158m and one delay unit 160a to 160m. For example, the ADC 32a is provided with a delay unit 158a and a delay unit 160a, and the ADC 32m is provided with a delay unit 158m and a delay unit 160m. Phase correction units 144a to 144m are provided corresponding to the number of delay units 158a to 158m, and phase correction units 145a to 145m are provided corresponding to the number of delay units 160a to 160m. An adder 150a that adds outputs from the phase correctors 144a to 144m and an adder 150b that adds outputs from the phase correctors 145a to 145m are provided. A filter 152a is provided following the adder 150a, and a filter 152b is provided following the adder 150b. A rate converter 154 that converts the output of the filter 152a and the filter 152b is provided. Note that the filters 152a to 152b are configured by band-pass filters such as FIR filters and IIR filters. The rate conversion unit 154 includes a decimator and a selector.

First, the sampling clocks of the ADCs 32a to 32m that sample the ultrasonic reception signals, that is, 4nf ₀ clocks, are adjusted between the wavefronts of the ultrasonic reception signals related to the first beam and the second beam. Digital signals sampled by the sampling clock are output from the ADCs 32a to 32m, respectively. For example, the signal related to the first beam among the signals output from the ADC 32a is delayed by the delay unit 158a, while the signal related to the second beam among the signals output from the ADC 32a is delayed by the delay unit 160a. It is processed. The reception signals delayed by the delay units 158a to 158m are phase-corrected by the phase correction units 144a to 144m, respectively, and the phase-corrected signals are added by the addition unit 150a. In addition, the received signals delayed by the delay units 160a to 160m are phase-corrected by the phase correction units 145a to 145m, respectively, and the phase-corrected signals are added by the addition unit 150b. An unnecessary frequency band is removed by the filter 152a from the signal related to the first beam added by the adder 150a, and the rate of the filtered signal is converted by the rate converter 154. Further, the signal related to the second beam added by the adder 150b is subjected to filter processing by the filter 152b, and the rate-converted signal is rate-converted by the rate converter 154.

  According to such a phase correction unit 156, it is possible to form the first beam by correcting the phase by the filter 152a and at the same time form the second beam by correcting the phase by the filter 152b. That is, in the wavefront synchronous sampling phasing method, the phase accuracy for phasing the received signal can be improved and a plurality of beams can be formed simultaneously. As a result, the frame rate and spatial resolution of the image can be improved. When three or more beams are formed, the number of delay units, phase correction units, addition units, and filter units may be increased as necessary.

It is a block diagram which shows the structural example of the ultrasonic diagnosing device to which this invention is applied. The structural example of the phasing addition part is shown. 2 shows a configuration example of a sampling clock generation unit. The structural example of the delay control part is shown. The other structural example of the delay control part is shown. The structural example of the phase correction part is shown. The structural example of the phase correction control part is shown. The other example of a structure of the phase correction part and the phase correction control part is shown. The structural example of the phase correction | amendment part which correct | amends the frequency band of a received signal is shown. The other structural example of the phase correction control part which correct | amends the frequency band of a received signal is shown. 2 shows a configuration example of a phase correction unit that corrects the phase and frequency band of a received signal. The other example of a structure of the phase correction control part which correct | amends the phase and frequency band of a received signal is shown. The other example of a structure of the phase correction control part which correct | amends the phase and frequency band of a received signal is shown. The other example of a structure of the phasing addition part is shown. The other example of a structure of the phasing addition part is shown. The other example of a structure of the phasing addition part is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Ultrasonic diagnostic apparatus 10 Probe 16 Phase adjustment addition part 18 Signal processing part 20 Image structure part 22 Display part 24 Control part 26a Vibrator 32a ADC
34a delay unit 36a phase correction unit 38 clock generation unit 40 delay control unit 42 phase correction control unit 46 4nf ₀ generation unit 48 phase delay unit 50 clock selection unit 52 control unit

Claims (4)

A probe formed by arranging a plurality of transducers that transmit and receive ultrasonic waves to and from the subject, and an AD conversion unit that converts received signals received by the transducers into digital signals in synchronization with a sampling clock A clock generation unit that generates the sampling clock in synchronization with the reception wavefront, a phasing addition unit that phasing and adding the digital signals converted by the AD conversion unit, and a superposition from the added reception signal An image composing unit that constitutes a sound wave image,
The phasing addition unit performs phasing processing on the AD-converted digital signal in parallel based on a plurality of preset reception beams, and adds the digital signals for the plurality of reception beams subjected to the phasing processing. Then, an ultrasonic diagnostic apparatus characterized by forming a plurality of reception beams.   A plurality of the phasing and adding units are provided in parallel for each of the plurality of reception beams with respect to each of the AD-converted digital signals, and a delay unit that delays the digital signals, and a delay unit And a phase correcting unit provided for the phase correction of the delayed digital signal and an adding unit for adding the phase-corrected digital signals for each of the plurality of received beams. Ultrasonic diagnostic equipment.   The ultrasonic diagnostic apparatus according to claim 1, wherein the clock generation unit includes means for generating the sampling clock based on a frequency of the reception signal. The ultrasonic diagnostic apparatus according to claim 3, wherein the clock generation unit generates a sampling clock having a frequency corresponding to a natural number multiple of 4 of the frequency of the reception signal.

Images