JP2008258521A - Multi-chip lamination substrate, multi-chip lamination mounting structure using the same, and application of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-chip lamination substrate, a multi-chip lamination mounting structure using the same, and an application of the same in which each chip group can independently operate. <P>SOLUTION: A multi-chip lamination substrate 200 at least has a first wire bonding finger 211, a second wire bonding finger 212, a trace, and a loop wiring. The first wire bonding finger 211 and the second wire bonding finger 212 are adjacent to a die attaching area. The loop wiring is connected in series to the first wire bonding finger 211 and the second wire bonding finger 212, and also connected to the trace. A multi-chip lamination mounting structure includes the substrate 200, a first chip 50 provided in the die attaching area, and a second chip 60 laminated on the first chip 50. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multi-chip stacking technique, and more particularly to a multi-chip stacked substrate, a multi-chip stacked mounting structure using the same, and its application.

  In recent years, with the advancement of electronic technology, more and more electronic devices suitable for human beings have been commercialized for higher performance. In terms of appearance, products are designed according to the trend of weight reduction, thinning, miniaturization, etc., and in response to the demands for miniaturization and high speed, multiple chips are used to achieve several times more capacity or more functions. Are stacked vertically on a substrate and sealed with a sealing body, which is referred to as a multichip stacked mounting structure. However, if the product is electrically inspected after the sealing operation in the manufacturing process of the conventional multi-chip stacked mounting structure and only one chip does not work well in the product, the entire product must be discarded as a defective product. The repair after the sealing operation becomes impossible.

  As shown in FIG. 1, the multichip stacked mounting structure includes at least a substrate 100, a first chip 10, a second chip 20, a plurality of bonding wires 31, bonding wires 32, and a sealing body 40. The substrate 100 includes a plurality of wire bonding fingers 110 and a plurality of traces 120, which are formed on the inner surface 101 of the substrate 100. The wire bonding fingers 110 are adjacent to the die attach area 103 of the substrate 100, the first chip 10 is stuck on the die attach area 103, and the second chip 20 is stacked above the first chip 10. . Further, referring to FIG. 1, these wire bonding fingers 110 are formed on the inner surface 101 and exposed on the insulating layer 130 of the substrate 100 for wire bonding. A plurality of outer connection pads 140 are formed on the outer surface 102 of the substrate 100. The first chip 10 has a plurality of first bonding pads 11 and electrically connects the first bonding pads 11 and the corresponding wire bonding fingers 110 via first bonding wires 31. An inclusion 12 is installed between the first chip 10 and the second chip 20. The second chip 20 has a plurality of second bonding pads 21 and electrically connects the second bonding pads 21 and the corresponding wire bonding fingers 110 via the second bonding wires 32. Therefore, the wire bonding fingers 110 using the same signal, common power supply, or ground can be simultaneously connected to the first bonding wire 31 and the second bonding pad 21 (shown in FIG. 2).

  A known multi-chip stacked mounting structure includes, for example, a memory card and a sealing body 40, and the first chip 10 and the second chip 20 are sealed by the sealing body 40. During the sealing process, if the chip or bonding wire connected to the chip becomes defective, know that one or some of the chips will not move normally after the mounting and inspection operations, and the defective chip or bonding wire Is sealed in a sealing body and electrically connected to the substrate, so that other good chips cannot be moved normally, and the entire semiconductor product is discarded along with the defective chips. The rate will rise.

  At present, there are several solutions to the above problem, and one can perform a complete electrical test on all chips in the wafer level class to check which chips operate normally. However, the cost of such measurements is quite high and is not suitable for low-cost mass production. Another method is that repair is performed during the mounting process, and referring to the multichip module mounting structure that can be repaired in Patent Document 1, the lower layer is electrically connected during the die attach and electrical connection work and before the sealing work. When inspection is performed and a lower layer chip that is not normal is found, the bonding wire connected to the lower layer chip is removed, and one substitute chip is attached in a stacked manner. Such a method requires electrical inspection and removal of bonding wires of defective chips before the sealing operation, so the quality after the sealing operation is not yet finalized, and there are additional restrictions on the manufacturing process. come. Moreover, such a stacking method is not a dedicated method for a multichip stacked mounting structure in which normal chips are stacked on a defective chip.

Taiwan Patent Publication No. 409,330 public information

A main object of the present invention is to provide a multichip laminated substrate, a multichip laminated mounting structure using the same, and its application. A plurality of chips are stacked in a mounting structure and designed using a loop wiring having a fuse so that the chip groups can perform independent work without interfering with each other after electrical inspection.
Another object of the present invention is to provide a multi-chip laminated substrate, a multi-chip laminated mounting structure using the same, and its application, so that the fuse can be burned out even after the sealing operation, and the bonding wire Even if you don't remove it, you will be able to repair it.

  In order to achieve the above object, the following technique is proposed in the present invention. According to the present invention, the multichip laminated substrate includes at least a first wire bonding finger, a second wire bonding finger, a trace, and a loop wiring. The first wire bonding finger is adjacent to the die attach area, and the second wire bonding finger is also adjacent to the die attach area. Traces are used for electrical transfer. The loop wiring is connected in series to the first wire bonding finger and the second wire bonding finger, and is connected to the trace.

  In the above board, the first fuse, the second fuse, and the third fuse are installed in the loop wiring, the first fuse is connected in series between the first wire bonding finger and the trace, and the second fuse is connected to the first wire bonding. A series connection is made between the finger and the second wire bonding finger, and a third fuse is connected in series between the second wire bonding finger and the trace.

In the substrate, the line widths of the first fuse, the second fuse, and the third fuse are smaller than the line width of the loop wiring.
The substrate further includes an insulating layer, the insulating layer having a plurality of openings, the openings aiming at the first fuse, the second fuse, and the third fuse, the first fuse, the second fuse, and the third fuse. Expose the fuse.
In the above substrate, the insulating layer may be a core substrate, exposing the first fuse, the second fuse, and the third fuse on the outer surface of the substrate.

In the substrate, the insulating layer may be a solder mask layer, and the first fuse, the second fuse, and the third fuse are exposed on the inner surface of the substrate.
In the substrate, the first wire bonding finger, the second wire bonding finger, the trace and the loop wiring may be disposed on the inner surface of the substrate, and further include an external connection pad, and the external connection pad is formed on the outer surface of the substrate. is set up.
In the substrate described above, the appearance of the loop wiring is a polygonal, circular, and arc-shaped periphery.
The substrate further includes a third wire bonding finger, and the third wire bonding finger is connected in series with the loop wiring.

A multichip laminated substrate according to a first embodiment of the present invention is disclosed. 3 is a cross-sectional view in which the substrate is applied to a multichip stacked mounting structure, FIG. 4 is a perspective view showing a portion of the substrate after wire bonding connection work, and FIG. 5 shows various electrical inspection results. FIG. 6 is a cross-sectional view showing a portion of a substrate. FIG.
As shown in FIGS. 3 and 4, the substrate 200 includes at least a plurality of finger sets, and each finger set includes a first wire bonding finger 211, a second wire bonding finger 212, a trace 220, and a loop wiring 230. The substrate 200 has an inner surface 201 and an outer surface 202. A die attach area 203 is defined on the inner surface 201, and a plurality of laminated chips 50, laminated chips 60 or more are installed in the die attach area 203. ing. The first wire bonding finger 211 and the second wire bonding finger 212 are disposed on the inner surface 201 of the substrate 200 adjacent to the die attach area 203 close to each other. As shown in FIG. 4, the trace 220 is placed on the inner surface 201 of the substrate 200 for electrical transmission. In this embodiment, the substrate 200 further includes an external connection pad 250 disposed on the outer surface 202 of the substrate 200. The external connection pad 250 may be an elongated gold finger. Applied to the card.

  As shown in FIG. 4, the loop wiring 230 is connected in series with the first wire bonding finger 211 and the second wire bonding finger 212 and is also connected to the trace 220, so that the first wire bonding finger 211 and the second wire bonding finger are connected. Each finger 212 is electrically connected to a trace 220. In this embodiment, the loop wiring 230 can be installed on the inner surface 201 of the substrate 200 and has an outer shape of a substantially polygonal, circular or arcuate periphery. Referring again to FIG. 4, the first fuse F <b> 1, the second fuse F <b> 2, and the third fuse F <b> 3 can be installed in the loop wiring 230 in order to provide a selectable fuse blow. The first fuse F1 is connected in series between the first wire bonding finger 211 and the trace 220, and the second fuse F2 is connected in series between the first wire bonding finger 211 and the second wire bonding finger 212. The third fuse F3 is connected in series between the second wire bonding finger 212 and the trace 220. It is considered ideal that the distance between the first wire bonding finger 211 and the second wire bonding finger 212 can be arranged with only a single second fuse F2. Therefore, the first wire bonding finger 211 and the second wire bonding finger 212 are considered. And can be closely arranged. In general, since the line width of each of the first fuse F1, the second fuse F2, and the third fuse F3 is smaller than the line width of the loop wiring 230, the line is cut by selectively burning the fuse with the laser beam 90. Is possible. In the present embodiment, the first fuse F1, the second fuse F2, and the third fuse F3 may be made of the same manufacturing material as the loop wiring 230, for example, generally using Cu (copper) or the like, or a tungsten filament. (Tungsten filament) or other metal that can be burned out.

  According to the first embodiment of the present invention, the substrate 200 can be further applied to a multi-chip stacked mounting structure, in particular, a micro SD card. As shown in FIG. 3, the multichip stacked mounting structure includes at least a substrate 200, a first chip 50, and a second chip 60. The first chip 50 is installed in the die attach area 203 of the substrate 200, includes a plurality of first bonding pads 51, and the first bonding wires 71 are associated with the first bonding wires 71 using a traditional wire bonding connection technique. The bonding pad 51 and the first wire bonding finger 211 are electrically connected. The second chip 60 is stacked above the first chip 50, includes a plurality of second bonding pads 61, and using traditional wire bonding connection techniques, the second bonding wires 72 are associated with the corresponding second bonding pads. The pad 61 and the second wire bonding finger 212 are electrically connected. Specifically, the multi-chip stacked mounting structure further includes an inclusion 52, which is disposed between the first chip 50 and the second chip 60, so that the back surface of the second chip 60 is The first chip 50 and the first bonding wire 71 are not in direct contact.

Referring again to FIG. 3, the sealing body 80 is formed on the inner surface 201 of the substrate 200 to seal the first chip 50, the second chip 60, the first bonding wire 71 and the second bonding wire 72. .
Specifically, the substrate 200 further includes a solder mask layer 260, which is formed on the inner surface 201 of the substrate 200 to partially cover the wiring layer of the substrate 200 and cover the traces 220, The first wire bonding finger 211 and the second wire bonding finger 212 are exposed for wire bonding connection.

In this embodiment, the multi-chip stacked mounting structure further includes a control chip, and the control chip is electrically connected to the trace 220. As an application, both the first chip 50 and the second chip 60 are used as memory chips. For example, a memory card (not shown) can be assembled.
The quality and status of each chip used are different, and if the chip determined to be defective based on the inspection result is subjected to the correspondence adjustment as shown in FIG. 5, the first fuse F1, the second fuse F2, and the third fuse F3 are used. By burning out, other good chips can move normally. Electrical inspection and repair work can be performed even after the sealing work is completed.

  4 and 5, if the first chip 50 and the second chip 60 are satisfactory in the inspection result, it is necessary to cut the first fuse F1, the second fuse F2, and the third fuse F3. There is no. Next, when only the first chip 50 fails, the first fuse F1 and the second fuse F2 are disconnected, so that the first wire bonding finger 211 and the trace 220 are electrically disconnected. The lower first chip 50 is completely electrically insulated from the internal wiring of the substrate 200. Therefore, the second chip 60 can perform normal calculation without interference by the first chip 50. In addition, it is not necessary to remove or cut the second bonding wire 72 connected to the second chip 60.

  Referring to FIGS. 4 and 5 again, when only the second chip 60 fails, the second fuse F2 and the third fuse F3 are disconnected, and the second bonding wire 72 and the trace 220 are not separated. As a result, the upper second chip 60 is completely electrically disconnected from the internal wiring of the substrate 200. Therefore, the first chip 50 can operate normally without interference by the second chip 60. In addition, it is not necessary to remove or cut the first bonding wire 71 connected to the first chip 50.

  Therefore, the first fuse 50, the second fuse F2, and the third fuse F3 are used to make a disconnection that can be selected, and the first chip 50 and the second chip 60 do not interfere with each other, and each performs an independent operation. . In other words, if one or a part of a chip breaks down in a multi-chip stacked mounting structure, only the wire bonding finger fuse connected to the defective chip is burned out, and the wire bonding finger is disconnected. Good chip groups can work normally and provide a reduction in manufacturing costs. In addition, the fuse cutting operation that allows such selection is preferably performed after the die attach operation and the sealing operation in the manufacturing process.

  As shown in FIG. 6, the substrate 200 further includes an insulating layer 240 having a plurality of openings 241. The openings 241 are aimed at the first fuse F1, the second fuse F2, and the third fuse F3. The first fuse F1, the second fuse F2, and the third fuse F3 are exposed so that the second fuse F2 and the third fuse F3 can be arbitrarily cut by the laser beam 90. The insulating layer 240 is preferably a core substrate, whereby the first fuse F1, the second fuse F2, and the third fuse F3 are exposed to the outer surface 202 of the substrate 200, and after the wire bonding connection operation and the sealing operation. Also, the first fuse F1, the second fuse F2, and the third fuse F3 are burned and disconnected using the laser beam 90. In this embodiment, dielectric openings 270 are used to fill the openings 241.

  7A to 7D show a method of forming a break on the substrate 200 after wire bonding connection work and sealing work. First, as shown in FIG. 7A, the multi-chip stacked mounting structure subjected to wire bonding connection, sealing, and inspection work is left on a flat table so that the outer surface 202 of the substrate 200 faces the laser beam emitting device. Next, as shown in FIG. 7B, the fuse F1, the fuse F2, and the fuse F3 connected to the defective chip are searched. Further, as shown in FIG. 7C, the opening 241 group of the insulating layer 240 exposes the second fuse F2, and the laser beam 90 is used to cut the second fuse F2 to be in a disconnected state. Finally, as shown in FIG. 7D, applying a PCB via-filling technique, these openings 241, i.e., openings that have not been exposed to the laser beam, are filled with dielectric material. 270 is inserted, thus avoiding exposure of those fuses F1, F2 and F3.

  In the second embodiment, another type of multi-chip stacked mounting structure is disclosed. As shown in FIG. 8, the substrate 300 includes a plurality of electrical mechanisms, and each electrical mechanism includes at least a first wire bonding finger 311, a second wire bonding finger 312, a trace 320, and a loop wiring 330. In this embodiment, the first wire bonding finger 311, the second wire bonding finger 312, the trace 320 and the loop wiring 330 can be disposed on the inner surface 301 of the substrate 300. The substrate 300 further includes an external connection pad 350, which is disposed on the outer surface 302 of the substrate 300. The first wire bonding finger 311 and the second wire bonding finger 312 are adjacent to a die attach area where a plurality of chips 50 'and chips 60' are stacked. The trace 320 is used for electrical transfer. The loop wiring 330 is connected in series to the first wire bonding finger 311 and the second wire bonding finger 312, and is connected to the trace 320. Referring again to FIG. 8, at least a fuse 360 is installed in the loop wiring 330, and this fuse 360 is connected in series between the first wire bonding finger 311, the second wire bonding finger 312, and the trace 320, and can be selected. Is provided.

  Specifically, the substrate 300 further includes an insulating layer 340 having a plurality of openings 341, and these openings 341 easily cut the fuse 360 with the laser beam 90, so that the fuse 360 is exposed by aiming at the fuse 360. . In the present embodiment, the insulating layer 340 may be a solder mask layer, which is applied to expose the fuse 360 on the inner surface 301 of the substrate 300 and perform a selectable disconnection before the sealing operation.

  9A to 9C show a method for burning out the fuse of the substrate 300 after the wire bonding connection work and before the sealing work. First, as shown in FIG. 9A, the first chip 50 ′ is installed on the inner surface 301 of the substrate 300, and at least the second chip 60 ′ is stacked above the first chip 50 ′. The first bonding pads 51 ′ of the first chip 50 ′ are electrically connected to the first wire bonding fingers 311 using the wires 71 ′, and the second chips 60 ′ are used using the plurality of second bonding wires 72 ′. The second bonding pads 61 ′ and the second wire bonding fingers 312 are electrically connected. Next, after the electrical inspection and before performing the sealing operation, the inner surface 301 of the substrate 300 faces the laser beam emitting device while the semi-finished product of the multichip stacked mounting structure is left on a flat table, so that the fuse 360 is exposed. Then, as shown in FIG. 9B, the fuse 360 connected to the wire bonding finger of the detected defective chip is cut using a laser beam 90. Finally, as shown in FIG. 9C, the fuse 360 is disconnected, so that the detected defective chip is electrically disconnected from the internal wiring of the substrate 300. Therefore, it is possible to form a selectable disconnection using the fuse 360, and the plurality of laminated chips do not interfere with each other, and perform independent operations.

  In the third embodiment, yet another type of multi-chip stacked mounting structure is disclosed. As shown in FIG. 10, the substrate 400 includes at least a first wire bonding finger 411, a second wire bonding finger 412, a trace 420, and a loop wiring 430. The first wire bonding finger 411 and the second wire bonding finger 412 are adjacent to the die attach area 403, and the trace 420 is used for electrical transfer. The loop wiring 430 is connected in series with the first wire bonding finger 411 and the second wire bonding finger 412, and is connected to the trace 420. In the present embodiment, depending on the number of laminated chips, the substrate 400 further includes a third wire bonding finger 413 for wire bonding connection with the third chip, and the third wire bonding finger 413 is adjacent to the die attach area 403. The loop wiring 430 is connected in series. The first wire bonding finger 411, the second wire bonding finger 412, the third wire bonding finger 413, the trace 420 and the loop wiring 430 are installed on the inner surface 401 of the substrate 400.

As shown in FIG. 10, a first fuse F1, a second fuse F2, a third fuse F3, a fourth fuse F4, and a fifth fuse F5 can be installed in the loop wiring 430. The first fuse F1 is connected in series between the first wire bonding finger 411 and the trace 420, and the second fuse F2 is connected in series between the first wire bonding finger 411 and the second wire bonding finger 412. The fuse F3 is connected in series between the second wire bonding finger 412 and the trace 420, the fourth fuse F4 is connected in series between the second wire bonding finger 412 and the third wire bonding finger 413, and the fifth fuse F5. Are connected in series between the third wire bonding finger 413 and the trace 420. This provides selectable breaks and has the advantage that multiple stacked chips (three or more) on a substrate can be repaired without removing the bonding wires, as well as during the semiconductor mounting process and after product completion The ability to perform the repair operation can further improve flexibility and convenience for the entire manufacturing process.
Although the present invention has been described based on the preferred embodiments thereof, the scope of protection of the present invention is limited by the scope of patent application that is attached later, and touches the spirit and scope of the present invention based on this scope of protection. Any changes or modifications belong to the protection scope of the present invention.

It is sectional drawing of a known multichip laminated substrate. It is a perspective view of the known board | substrate after being wire-bonded-connected. It is sectional drawing which shows the multichip lamination | stacking mounting structure by 1st Example of this invention. 1 is a perspective view showing a substrate after wire bonding connection of a multichip stacked mounting structure according to a first embodiment of the present invention. FIG. It is a figure which shows the comparison table of the several fuse open / close state according to the board | substrate of the multichip laminated mounting structure by 1st Example of this invention, and various test results. It is sectional drawing which shows the board | substrate of the multichip lamination | stacking mounting structure by 1st Example of this invention. It is sectional drawing which shows the disconnection formation method of the bottom face of the board | substrate of the multichip lamination | stacking mounting structure by 1st Example of this invention. It is a perspective view which shows the disconnection formation method of the bottom face of the board | substrate of the multichip lamination | stacking mounting structure by 1st Example of this invention. It is sectional drawing which shows the disconnection formation method of the bottom face of the board | substrate of the multichip lamination | stacking mounting structure by 1st Example of this invention. It is sectional drawing which shows the disconnection formation method of the bottom face of the board | substrate of the multichip lamination | stacking mounting structure by 1st Example of this invention. It is sectional drawing which shows the board | substrate of the multichip lamination | stacking mounting structure by the 2nd Example of this invention. It is a schematic diagram which shows the disconnection formation method on the board | substrate of the multichip lamination | stacking mounting structure by the 2nd Example of this invention. It is a perspective view which shows the disconnection formation method on the board | substrate of the multichip lamination | stacking mounting structure by 2nd Example of this invention. It is a perspective view which shows the disconnection formation method on the board | substrate of the multichip lamination | stacking mounting structure by 2nd Example of this invention. It is a schematic diagram which shows the inner surface of the board | substrate of the multichip lamination | stacking mounting structure by the 3rd Example of this invention.

Explanation of symbols

  10: first chip, 11: first bonding pad, 12: inclusion, 20: second chip, 21: second bonding pad, 31: first bonding wire, 32: second bonding wire, 40: sealing body 50: first chip, 50 ′: first chip, 51: first bonding pad, 51 ′: first bonding pad, 52: inclusion, 60: second chip, 60 ′: second chip, 61: first chip Two bonding pads, 61 ′: second bonding pad, 71: first bonding wire, 71 ′: first bonding wire, 72: second bonding wire, 72 ′: second bonding wire, 80: sealing body, 90: Laser beam, 90 ': Laser beam, 100: Substrate, 101: Inner surface, 102: Outer surface, 103: Die attach area, 110: Wire bond 120: Trace, 130: Insulating layer, 140: Outer connection pad, 200: Substrate, 201: Inner surface, 202: Outer surface, 203: Die attach area, 211: First wire bonding finger, 212: Second Wire bonding finger, 220: Trace, 230: Loop wiring, 240: Insulating layer, 241: Opening, 250: External connection pad, 260: Solder mask layer, 270: Dielectric filling, 300: Substrate, 301: Inner surface, 302: outer surface, 311: first wire bonding finger, 312: second wire bonding finger, 320: trace, 330: loop wiring, 340: insulating layer, 341: opening, 350: external connection pad, 360: fuse, 401 : Inner surface, 403: die attach area, 411: first Wire bonding finger, 412: Second wire bonding finger, 413: Third wire bonding finger, 420: Trace, 430: Loop wiring, F1: First fuse, F2: Second fuse, F3: Third fuse, F4: First Fourth fuse, F5: Fifth fuse

Claims (8)

(A) the first wire bonding finger is provided adjacent to the die attach area;
(B) the second wire bonding finger is provided adjacent to the die attach area and the first wire bonding finger;
(C) The trace is used for electrical transfer,
(D) The multi-layer laminated substrate in which the loop wiring is connected in series with the first wire bonding finger and the second wire bonding finger and connected to the trace. The first fuse, the second fuse and the third fuse are installed in the loop wiring,
The first fuse is connected in series between the first wire bonding finger and the trace,
The second fuse is connected in series between the first wire bonding finger and the second wire bonding finger,
The multichip laminated substrate according to claim 1, wherein the third fuse is connected in series between the second wire bonding finger and the trace.   The first wire bonding finger, the second wire bonding finger, the trace and the loop wiring are installed on the inner surface of the substrate, further include an outer connection pad, and the outer connection pad is installed on the outer surface of the substrate. The multichip laminated substrate according to claim 1. Including a third wire bonding finger,
The multi-chip laminated substrate according to claim 1, wherein the third wire bonding fingers are connected in series to the loop wiring. (A) The substrate is
(1) a first wire bonding finger adjacent to the die attach area;
(2) a second wire bonding finger adjacent to the die attach area and the first wire bonding finger;
(3) a trace used for electrical transfer;
(4) A first wire bonding finger and a second wire bonding finger are connected in series, and connected to the trace, and a loop wiring is provided.
(B) a first chip installed in the die attach area of the substrate and electrically connected to the first wire bonding fingers;
(C) a second chip stacked above the first chip and electrically connected to the second wire bonding finger;
A multi-chip stacked mounting structure comprising: The first fuse, the second fuse and the third fuse are installed in the loop wiring,
The first fuse is connected in series between the first wire bonding finger and the trace,
The second fuse is connected in series between the first wire bonding finger and the second wire bonding finger,
6. The multichip stacked mounting structure according to claim 5, wherein the third fuse is connected in series between the second wire bonding finger and the trace. The substrate further includes an insulating layer having a plurality of openings,
7. The multichip stacked mounting structure according to claim 6, wherein the opening is aimed at the first fuse, the second fuse, and the third fuse to expose the first fuse, the second fuse, and the third fuse.   8. The multi-chip stacked mounting structure according to claim 7, further comprising a dielectric filler to be put in the opening.

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