JP2008258494A - Ic chip - Google Patents

Ic chip Download PDF

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Publication number
JP2008258494A
JP2008258494A JP2007100686A JP2007100686A JP2008258494A JP 2008258494 A JP2008258494 A JP 2008258494A JP 2007100686 A JP2007100686 A JP 2007100686A JP 2007100686 A JP2007100686 A JP 2007100686A JP 2008258494 A JP2008258494 A JP 2008258494A
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Prior art keywords
bumps
chip
row
gap
acf
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JP2007100686A
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Japanese (ja)
Inventor
Tatsuya Hasegawa
達也 長谷川
Takeshi Kamoto
剛 嘉本
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Japan Display Central Inc
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Toshiba Matsushita Display Technology Co Ltd
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Priority to JP2007100686A priority Critical patent/JP2008258494A/en
Publication of JP2008258494A publication Critical patent/JP2008258494A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an IC chip capable of raising an insulation performance between bumps, when the IC chip is fixed by an ACF. <P>SOLUTION: In bumps 14 which are arranged at a bottom face of an IC chip 12 in a stagger shape, there is provided a gap A between a bump 14 of a primary sequence and a bump 14 of a secondary sequence, and this gap A is set larger than twice the diameter of a conductive particle 20 contained in an ACF 18. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、液晶表示装置等に取り付けられるICチップに関するものである。   The present invention relates to an IC chip attached to a liquid crystal display device or the like.

液晶表示装置の液晶パネルの表面には、ソースドライバーやゲートドライバーの機能を果たすICチップが取り付けられている。この接続方法は、液晶パネルを構成するガラス基板上に千鳥状に端子が配置され、ICチップの底面にも千鳥状にバンプが配置され、バンプと端子を異方性導電膜(以下、ACFという)によって物理的、かつ、電気的に接続している(例えば、特許文献1参照)。
特開平8−293529号公報
An IC chip that functions as a source driver or a gate driver is attached to the surface of the liquid crystal panel of the liquid crystal display device. In this connection method, terminals are arranged in a zigzag pattern on a glass substrate constituting the liquid crystal panel, bumps are arranged in a zigzag pattern on the bottom surface of the IC chip, and the bump and the terminal are referred to as an anisotropic conductive film (hereinafter referred to as ACF). ) Are physically and electrically connected (see, for example, Patent Document 1).
JP-A-8-293529

図6はICチップ100のICチップ本体104の底面を拡大した図面であり、バンプ102が千鳥状に配列されている。   FIG. 6 is an enlarged view of the bottom surface of the IC chip body 104 of the IC chip 100, and the bumps 102 are arranged in a staggered pattern.

このような従来のICチップ100において、各バンプ102の間にACFの導電性粒子が存在して絶縁性が低くなるという問題点があった。   In such a conventional IC chip 100, there is a problem in that the conductive properties of ACF exist between the bumps 102, resulting in low insulation.

そこで、本発明は上記問題点に鑑み、ICチップをACFによって固定した場合に、バンプ間の絶縁性を高めることができるICチップを提供する。   Accordingly, in view of the above problems, the present invention provides an IC chip that can enhance the insulation between bumps when the IC chip is fixed by ACF.

本発明は、ICチップ本体の底面に複数のバンプが形成されたICチップであって、異方性導電膜によって前記バンプのそれぞれが端子に接続されるICチップおいて、
前記複数のバンプが横方向に一直線状に配列され、縦方向に少なくとも2列配列され、かつ、第1の列において隣接する前記バンプの間に第2の列の前記バンプが配置された千鳥状配置であり、前記第1の列のバンプと前記第2の列のバンプの間に間隙が形成され、前記間隙が前記異方性導電膜に含まれる導電性粒子の直径の2倍以上である、ICチップである。
The present invention is an IC chip in which a plurality of bumps are formed on the bottom surface of the IC chip body, and each of the bumps is connected to a terminal by an anisotropic conductive film.
The plurality of bumps are arranged in a straight line in the horizontal direction, arranged in at least two rows in the vertical direction, and the bumps in the second row are arranged between the adjacent bumps in the first row. A gap is formed between the bumps in the first row and the bumps in the second row, and the gap is at least twice the diameter of the conductive particles contained in the anisotropic conductive film. IC chip.

本発明によれば、ACFによって固定しても、ICチップのバンプ間の絶縁性を高めることができる。   According to the present invention, the insulation between the bumps of the IC chip can be improved even if the ACF is used.

本発明の一実施形態のICチップ10について図1〜図5に基づいて説明する。   An IC chip 10 according to an embodiment of the present invention will be described with reference to FIGS.

(1)ICチップ10の構成
本実施形態のICチップ10は、液晶パネルに取り付けられるドライバーICであって、図1に示すように図1及び図2に示すように、ICチップ本体12は直方体状であって、その底面に複数のバンプ14が設けられている。即ち、ICチップ本体12の底面において、一方の側辺に沿って千鳥状のバンプ14a、bが配列され、他方の側辺に沿って1列にバンプ14cが配置されている。この千鳥状に配置されたバンプ14については後から詳しく説明する。
(1) Configuration of IC Chip 10 The IC chip 10 of the present embodiment is a driver IC attached to a liquid crystal panel. As shown in FIG. 1 and FIG. A plurality of bumps 14 are provided on the bottom surface. That is, on the bottom surface of the IC chip body 12, staggered bumps 14a and 14b are arranged along one side, and the bumps 14c are arranged in a row along the other side. The bumps 14 arranged in a staggered manner will be described in detail later.

液晶パネルのガラス基板22上にも、このICチップ10のバンプ14の配置に対応するように端子16が設けられている。例えば、前記した千鳥状のバンプ14a、bに対応して、図2に示すように千鳥状に端子16が配置されている。   Terminals 16 are also provided on the glass substrate 22 of the liquid crystal panel so as to correspond to the arrangement of the bumps 14 of the IC chip 10. For example, corresponding to the staggered bumps 14a and 14b, terminals 16 are arranged in a staggered manner as shown in FIG.

(2)バンプ14の配置
次に、千鳥状に配置されたバンプ14a、b、cについて詳しく説明する。
(2) Arrangement of Bumps 14 Next, the bumps 14a, 14b, 14c arranged in a staggered manner will be described in detail.

これらバンプ14a、bは、横方向に沿って1列に配置され、縦方向に2列配置されている。そして、第1列において隣接するバンプ14a,14aの間に第2列のバンプ14bが配置されている。さらに、第1列のバンプ14aと第2列のバンプ14bとの間には間隙Aが設けられている。この間隙Aとしては、後から説明するようにACF18に含まれる導電性粒子20の直径の2倍に設定されている。   The bumps 14a and 14b are arranged in one row along the horizontal direction and arranged in two rows in the vertical direction. A second row of bumps 14b is arranged between adjacent bumps 14a and 14a in the first row. Further, a gap A is provided between the first row of bumps 14a and the second row of bumps 14b. The gap A is set to be twice the diameter of the conductive particles 20 included in the ACF 18 as will be described later.

ICチップ10のバンプ14a、b、cと、端子16とはACF18によって固定される。   The bumps 14a, b, c of the IC chip 10 and the terminal 16 are fixed by the ACF 18.

(3)間隙Aを設けた理由
上記のように第1列のバンプ14aと第2列のバンプ14bとの間隙Aを導電性粒子20の直径の2倍にした理由について説明する。
(3) Reason for Providing Gaps A The reason why the gap A between the first row of bumps 14a and the second row of bumps 14b is twice the diameter of the conductive particles 20 will be described.

背景技術で説明したように、千鳥状に配置されたバンプ102においては、各バンプ102,102間の絶縁性が低くなるという問題点があった。この理由について色々な実験を重ねた結果、第1列のバンプ102と第2列のバンプ102の間隙が0か若しくは小さいと、導電性粒子20の移動量が少なくバンプ102,102間を絶縁し難いことが判明した。   As described in the background art, the bumps 102 arranged in a staggered manner have a problem that the insulation between the bumps 102 and 102 is lowered. As a result of various experiments for this reason, when the gap between the bumps 102 in the first row and the bumps 102 in the second row is 0 or small, the amount of movement of the conductive particles 20 is small and the bumps 102 and 102 are insulated. It turned out to be difficult.

その状態について図4に基づいて説明する。   The state will be described with reference to FIG.

図4(a)はACF18によってICチップ10,100を仮付け状態した底面図であり、(b)は本実施形態のICチップ10を本圧着した状態の底面図であり、(c)は従来のICチップ100を本圧着した状態の底面図である。   4A is a bottom view in which the IC chips 10 and 100 are temporarily attached by the ACF 18, FIG. 4B is a bottom view in a state in which the IC chip 10 of the present embodiment is finally press-bonded, and FIG. It is a bottom view in the state where this IC chip 100 was finally press-fitted.

この図が示すように仮付け状態において導電性粒子20が存在し、本圧着をすると、従来のICチップ100では、導電性粒子20の移動量が少なく、バンプ102間を電気的に接続する状態が起こる。一方、本実施形態のICチップ10であると、間隙Aが存在するため、導電性粒子20の移動量が大きく、バンプ14a、bの間を導通させたりすることがない。   As shown in this figure, the conductive particles 20 are present in the temporarily attached state, and when the main pressure bonding is performed, the conventional IC chip 100 has a small amount of movement of the conductive particles 20 and the state in which the bumps 102 are electrically connected. Happens. On the other hand, in the IC chip 10 of this embodiment, since the gap A exists, the amount of movement of the conductive particles 20 is large, and the bumps 14a and 14b are not electrically connected.

図5が、間隙Aを横軸に、縦軸に導電性粒子20の移動量を表したものであり、Aが0〜2μmの間は従来のICチップ100を示し、6μm以上が本実施形態のICチップ10を示している。尚、導電性粒子の直径は3μmとする。   FIG. 5 shows the movement amount of the conductive particles 20 with the gap A on the horizontal axis and the vertical axis with the conventional IC chip 100 when A is 0 to 2 μm, and this embodiment is 6 μm or more. The IC chip 10 is shown. The diameter of the conductive particles is 3 μm.

このグラフが示すように、4μm以上間隙Aが存在すると導電性粒子の移動量が80μm近くになり、絶縁性を確保することができる。そのため、絶縁性の安全を見て導電性粒子20の直径の2倍(6μm)以上、バンプ14の間を離すと、移動量が確実に大きくなり、その絶縁性を確保することができる。   As shown in this graph, when the gap A is 4 μm or more, the amount of movement of the conductive particles is close to 80 μm, and insulation can be ensured. For this reason, when the distance between the bumps 14 is increased by twice (6 μm) or more of the diameter of the conductive particles 20 in view of the safety of insulation, the amount of movement is surely increased, and the insulation can be ensured.

以上のように本実施形態のICチップ10であると、ACF18によってICチップ10を端子16に固定した場合でも、各バンプ14の間の絶縁性を確実に確保することができる。   As described above, in the case of the IC chip 10 according to the present embodiment, even when the IC chip 10 is fixed to the terminal 16 by the ACF 18, the insulation between the bumps 14 can be reliably ensured.

(a)はICチップの底面図であり、(b)はその一部拡大図である。(A) is a bottom view of the IC chip, and (b) is a partially enlarged view thereof. 端子の拡大平面図である。It is an enlarged plan view of a terminal. ICチップを端子に取り付けようとする状態の縦断面図である。It is a longitudinal cross-sectional view of the state which tries to attach an IC chip to a terminal. 本実施形態と従来のICチップを仮付け状態から本圧着した状態を示す説明図である。It is explanatory drawing which shows the state which carried out this pressure bonding of this embodiment and the conventional IC chip from the temporary attachment state. 導電性粒子の移動量と間隙Aとの関係を示したグラフである。5 is a graph showing the relationship between the amount of movement of conductive particles and the gap A. 従来のICチップの底面図である。It is a bottom view of the conventional IC chip.

符号の説明Explanation of symbols

10 ICチップ
12 ICチップ本体
14 バンプ
16 端子
18 ACF
20 導電性粒子
10 IC chip 12 IC chip body 14 Bump 16 Terminal 18 ACF
20 Conductive particles

Claims (2)

ICチップ本体の底面に複数のバンプが形成されたICチップであって、異方性導電膜によって前記バンプのそれぞれが端子に接続されるICチップおいて、
前記複数のバンプが横方向に一直線状に配列され、縦方向に少なくとも2列配列され、かつ、第1の列において隣接する前記バンプの間に第2の列の前記バンプが配置された千鳥状配置であり、
前記第1の列のバンプと前記第2の列のバンプの間に間隙が形成され、
前記間隙が前記異方性導電膜に含まれる導電性粒子の直径の2倍以上である、
ICチップ。
In an IC chip in which a plurality of bumps are formed on the bottom surface of the IC chip body, and each of the bumps is connected to a terminal by an anisotropic conductive film,
The plurality of bumps are arranged in a straight line in the horizontal direction, arranged in at least two rows in the vertical direction, and the bumps in the second row are arranged between the adjacent bumps in the first row. Arrangement,
A gap is formed between the first row of bumps and the second row of bumps;
The gap is at least twice the diameter of the conductive particles contained in the anisotropic conductive film;
IC chip.
前記間隙が6μm以上である、
請求項1記載のICチップ。
The gap is 6 μm or more,
The IC chip according to claim 1.
JP2007100686A 2007-04-06 2007-04-06 Ic chip Pending JP2008258494A (en)

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Application Number Priority Date Filing Date Title
JP2007100686A JP2008258494A (en) 2007-04-06 2007-04-06 Ic chip

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Application Number Priority Date Filing Date Title
JP2007100686A JP2008258494A (en) 2007-04-06 2007-04-06 Ic chip

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012015544A (en) * 2011-09-14 2012-01-19 Sony Chemical & Information Device Corp Method of manufacturing connecting structure, and connecting structure and connecting method
CN104516134A (en) * 2013-10-08 2015-04-15 株式会社日本显示器 Display device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012015544A (en) * 2011-09-14 2012-01-19 Sony Chemical & Information Device Corp Method of manufacturing connecting structure, and connecting structure and connecting method
CN104516134A (en) * 2013-10-08 2015-04-15 株式会社日本显示器 Display device
CN104516134B (en) * 2013-10-08 2017-09-29 株式会社日本显示器 Display device

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