JP2008257789A - Cross-point rram memory array having reduced bit line crosstalk - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce leak current in a cross-point RRAM memory cell. <P>SOLUTION: A cross-point RRAM memory array includes a word line array having an array of parallel word lines and a bit line array having an array of parallel bit lines perpendicular to the word lines, wherein a cross-point is formed between the word lines and the bit lines. A memory resistor is provided between the word lines and the bit lines at each cross-point. A high-open-circuit-voltage gain bit line sensing differential amplifier circuit provided at each bit line, includes a feedback resistor and a high-open-circuit-voltage gain amplifier, arranged in parallel, wherein a resistance of the feedback resistors is greater than a resistance of any of the memory resistors programmed at a low resistance state. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a cross-point type RRAM three-dimensional memory array with very little leakage current, and more specifically to a cross-point type RRAM three-dimensional memory array having a high gain bit line detection amplifier on each bit line.

  RRAM (Resistance Random Access Memory) is capable of switching resistance at a very low voltage, and is used as a nonvolatile memory resistor in a large-scale memory array. However, a single RRAM memory cell is not suitable for use in a cross-point memory array.

  US Pat. No. 6,753,561 (Rinerson et al., “Crosspoint Memory Array with Multiple Thin Films”, granted Jun. 22, 2004) discloses a plurality of substantially parallel conductive arrays. A memory array is described that includes a first group of lines, a second group of conductive array lines that are substantially parallel, and a plurality of memory plugs. The second group of substantially parallel conductive array lines is disposed substantially orthogonal to the first group of substantially parallel conductive array lines, and the plurality of memory plugs are: The first group of substantially parallel conductive array lines and the second group of substantially parallel conductive array lines are disposed at the intersection of the first group of substantially parallel conductive array lines. Each memory plug includes a metal / insulator / metal (MIM) device comprising a multilayer film including a thin film layer of a memory element and at least one thin film constituting a non-ohmic element. As a method of solving the above problem, Rinerson et al. Proposes to insert a current limiter into each memory resistor. However, adding a current limiter complicates the manufacturing process and increases circuit reliability.

FIG. 1 shows an equivalent circuit of a conventional cross-point type memory array. In FIG. 1, the entire circuit is indicated by an arrow 10, and a memory array having bit lines B ₁ , B ₂ , B ₃ , and B ₄ and a crosstalk path are shown. When the voltage VR is applied to the word line, for example, writing is performed by the resistor R ₃₄ on the bit line B ₄ , but crosstalk occurs between B ₄ and the adjacent bit line. When crosstalk occurs, distortion occurs in the memory signal output, so that crosstalk on the bit line is a very serious problem.

  S. T.A. Hsu et al. K. In Li, Sharp US Laboratory's internal document “Ultra High Density Crosspoint Resistive Memory Array with MSM / PCMO Memory Cells” (submitted on May 5, 2005) was inserted into each memory cell. A metal / semiconductor / metal (MSM) current limiter is disclosed, the MSM described in that document is a bidirectional Schottky diode and can handle larger currents than the MIM diode by Rinerson et al.

US Pat. No. 6,753,561

  An object of the present invention is to provide a circuit technique for minimizing leakage current in a cross-point RRAM three-dimensional memory array.

  Another object of the present invention is to provide a cross-point RRAM three-dimensional memory array having a high gain bit line detection amplifier for each bit line.

  A cross-point type RRAM memory array according to the present invention includes a word line array formed by arranging a plurality of word lines substantially in parallel and a plurality of bit lines substantially orthogonal to the word lines. A bit line array arranged in parallel is provided, and a cross point is formed between the word line and the bit line. A memory resistor is provided between the word line and the bit line at each cross point. The high gain bit line detection amplifier circuit on each bit line has a feedback resistor and a high gain differential amplifier arranged in parallel, and the resistance value of the feedback resistor is the value of any memory resistor written in the low resistance state. It is larger than the resistance value and smaller than the resistance value of any memory resistor written in the high resistance state.

  The gist and purpose of the present invention provide as soon as possible an understanding of the features of the present invention. In addition, a full understanding of the present invention can be obtained by reference to the drawings detailed below and the best mode for carrying out the invention.

  The first object of the three-dimensional cross-point type RRAM memory array according to the present invention is to eliminate crosstalk between bit lines. In the RRAM memory array according to the present invention, a high open circuit voltage gain amplifier is used as a bit line detection differential amplifier. Since the input voltage of the high gain amplifier is equal to 0, the crosstalk between the bit lines is minimized. The open circuit gain of the amplifier must be higher than 100. Further, the bit line detection amplifier circuit includes a feedback resistor having a resistance value larger than the resistance value of the memory resistor in the low resistance state.

FIG. 2 shows an equivalent circuit of two adjacent bit lines. An arrow 20 indicates the entire circuit. This circuit includes an amplifier with an open circuit voltage gain A, memory resistors R _M1 and R _M2 , and a feedback resistor R _F. Here, R corresponds to all unselected memory resistors connected to an arbitrary bit line, V is a selected word line voltage, V ₀₁ and V ₀₂ are output voltages of amplifiers on the bit line 1 and the bit line 2, respectively. Represents. I ₁ is a current that flows from the selected word line to the bit line 1 via the memory resistor R _M1 , I ₂ is a current that flows from the selected word line to the bit line 2 via the memory resistor R _M2 , and I ₃ is crosstalk It represents the leakage current that causes The above relationship is expressed by the following equations 1 to 5.

  The following Equation 6 and Equation 7 are derived from Equation 1 to Equation 5.

From the equations 6 and 7, the relationship between the output voltages V ₀₁ and V ₀₂ is defined as the following equation 8.

3 and FIG. 4 respectively, in the case of R _M2 = 5R _M1 = 5 kΩ and R _M2 = 10R _M1 = 10 kΩ, the open circuit voltage gain A is a parameter, and the resistance value of the non-selected memory resistor is the smallest As a function of the number of leak paths in the case. Resistance of the feedback resistor _{R F} is a 2 k.OMEGA. From these results, it can be seen that when the open circuit voltage gain A is greater than 500, the output voltage ratio V ₀₁ / V ₀₂ is about 2.8 and 4, respectively, if the number of leak resistance paths is a minimum of 100. . When the open circuit voltage gain A is 1000, the output voltage ratio V ₀₁ / V ₀₂ is about 3.5 and 5.4, respectively. This clearly shows that the output voltage ratio increases with the open circuit voltage gain of the sense amplifier and the high resistance to low resistance ratio of the memory resistor. By appropriately designing the sense amplifier, a large-scale cross-point RRAM array can be manufactured without providing a current limiter.

  Since the voltage on the bit line is substantially equal to the ground potential, the memory array indicated by the arrow 30 in FIG. 5 is read in units of words. The memory array 30 includes a plurality of word lines and bit lines arranged substantially in parallel, and the bit lines are substantially orthogonal to the word lines. Cross points are formed at the intersections of the word lines and the bit lines, and memory resistors are arranged at the respective cross points of the memory array 30. During the read operation, it is desirable that the unselected word line is biased to the ground potential.

As shown in FIG. 6, the memory array 30 can also be read in bit units. In FIG. 6, T ₂ and T ₄ are short-circuit transistors, and T ₁ and T ₃ are pass transistors. When any word line and bit line is selected, the selected word line is biased to voltage V by turning on T ₁ and T ₃ and turning off T ₂ and T ₄ and the output of the selected bit line is detected Connected to an amplifier. For unselected word lines and unselected bit lines, all the unselected word lines and unselected bit lines are short-circuited to the ground potential by turning off T ₁ and T ₃ and turning on T ₂ and T _4. Is done.

  The circuit capable of removing the crosstalk between bit lines in the cross point RRAM memory array has been described above. The present invention can be appropriately changed within the technical scope of the present invention shown in the claims.

Equivalent circuit diagram of a conventional crosspoint memory array with a crosstalk path in the bit line Equivalent circuit diagram of two adjacent bit lines with bit line sense amplifier It shows the output voltage ratio between 1kΩ resistor R _M1 and 5kΩ resistor R _M2 a cross-point RRAM low-resistance memory cell and a high-resistance memory cell according to the present invention comprising It shows the output voltage ratio between 1kΩ resistor R _M1 and 10kΩ resistor R _M2 a cross-point RRAM low-resistance memory cell and a high-resistance memory cell according to the present invention comprising The figure which shows the memory array based on this invention when reading by a word unit The figure which shows the principal part of the memory array based on this invention in the case of reading by a bit unit

Explanation of symbols

10: Conventional cross-point type memory array 20: Equivalent circuit of two adjacent bit lines 30: Cross-point type memory array according to the present invention

Claims (5)

A word line array formed by arranging a plurality of word lines in parallel and a bit line array formed by arranging a plurality of bit lines orthogonal to the plurality of word lines in parallel;
A cross point is formed between the word line and the bit line,
A memory resistor positioned between the word line and the bit line at each cross point;
A cross-point type RRAM memory array comprising a bit line detection differential amplifier circuit having a high open circuit voltage gain on each bit line.   2. The RRAM memory array according to claim 1, wherein said high open circuit voltage gain bit line detection differential amplifier circuit comprises a feedback resistor and a high open circuit voltage gain bit line detection differential amplifier arranged in parallel. .   3. The RRAM memory array according to claim 2, wherein a resistance value of the feedback resistor is larger than a resistance value of any of the memory resistors written in a low resistance state.   4. The RRAM memory array according to claim 2, wherein a resistance value of the feedback resistor is smaller than a resistance value of any of the memory resistors written in a high resistance state.   5. The RRAM memory array according to claim 2, wherein an open circuit voltage gain of the high-disclosure voltage gain bit line detection differential amplifier is greater than 100. 6.

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