JP2008257779A - Memory macro cell and semiconductor device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a memory macro cell capable of sharing a redundancy I/O area by a plurality of memory macro cells and to obtain a semiconductor device using the same. <P>SOLUTION: The memory macro cell and the semiconductor device using the same have: a selector 15a, of which the first shift input pin SI0 is connected to a first input, the DI0 is connected to a second input, the output is connected to In0, and the first or second input is selected by an SC; a selector 16a, of which the Out0 is connected to a first input, the Out1 is connected to a second input, the output is connected to DO0, and the first or second input is selected by the SC; and a selector 16h, of which the shift output pin SO0 connected to the Out0 and the Out7 are connected to the first input, a second shift input pin S17 is connected to a second input, the output is connected to DO7, and the first or second input is selected by the SC. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory macro cell employing a shift redundancy system and a semiconductor device using the memory macro cell.

  In general, a memory group that is mounted on a SoC (System On Chip) product such as a large-scale integrated circuit (LSI), particularly a semiconductor device that has a large number of small-scale memory groups, and does not have a redundancy function. There are many. For this reason, conventionally, if there is a defect at one location in one chip, it is discarded as a defective product. However, with the recent increase in functionality and diversification of chips, the number of small-scale memory groups mounted on one chip has increased, and the total memory capacity of the chip has also increased. In particular, in a SoC product in which several hundred levels of memory groups are scattered on one chip, a technique for efficiently mounting a redundancy function (for example, see “Patent Document 1”) is very important.

However, in the conventional semiconductor device, there is a problem that if the redundancy function is provided for each small-scale memory scattered in the chip, the chip area increases and the cost increases. On the other hand, along with miniaturization, there is a problem that dust such as small conductivity in the manufacturing process, which has not been a problem until now, causes the memory group to be defective, resulting in a decrease in yield and consequently an increase in cost. It was. In addition, products that require high-speed operation or the like with high functionality have a problem that the process steps become complicated and the memory group is defective.
JP 2003-157692 A

  The present invention provides a memory macrocell in which a redundancy I / O region can be shared by a plurality of memory macrocells, and a semiconductor device using the memory macrocell.

  According to a first aspect of the present invention, there is provided a memory macrocell having an N-bit (N is an integer of 2 or more) data input pin and an N-bit data output pin, and replacing a defective I / O by a shift redundancy method. A memory cell array having an N-bit I / O input and an N-bit I / O output corresponding to the I / O input, and the address information of the defective I / O, and based on the address information Control means for generating an N-bit control signal for replacing the defective I / O, and shifting data from the data input pin based on the control signal and supplying it to the I / O input of the memory cell array And an output shift means for shifting data from the I / O output of the memory cell array based on the control signal and supplying the data to the data output pin And a first shift input pin is connected to a first input, a first data input pin of the N bit data input pins is connected to a second input, and an output is the N bit I / The first input shift means is connected to the first I / O input of the O inputs, and the first or second input is selected by the first control signal of the N-bit control signals. And a first I / O output of the N-bit I / O outputs is connected to a first input, and a second I / O output of the N-bit I / O outputs is a second I / O output. And the output is connected to a first data output pin among the N-bit data output pins, and the first or second input is selected by the first control signal. Second selection means as shift means and connected to the first I / O output And the (n−1) th data input pin (n is an integer, 2 ≦ n ≦ (N−1)) among the N-bit data input pins is connected to the first input. , The nth data input pin of the N-bit data input pins is connected to a second input, the output is connected to the nth I / O input of the N-bit I / O inputs, and the N (2n-1) selection means as the input shift means for selecting the first or the second input by the nth control signal among the bit control signals, and the N-bit I / O output N-th I / O output is connected to the first input, (n + 1) -th I / O output among the N-bit I / O outputs is connected to the second input, and the output is the N-th output. The nth data output pin is connected to the nth data output pin of the bit data output pin, and is controlled by the nth control signal. The (2n) selection means as the output shift means for selecting the first or the second input, and the (N-1) th data input pin among the N-bit data input pins is the first one. The Nth data input pin of the N-bit data input pins is connected to the second input, and the output is the Nth I / O input of the N-bit I / O inputs. And (2N-1) th selection means as the input shift means for selecting the first or second input by an Nth control signal among the N-bit control signals, and the N Of the bit I / O outputs, the Nth I / O output is connected to the first input, the second shift input pin is connected to the second input, and the output is the N-bit data output pin. Connected to the Nth data output pin, and according to the Nth control signal. Thus, there is provided a memory macrocell having (2N) selection means as the output shift means for selecting the first or second input.

  According to the second aspect of the present invention, the memory macrocell includes an M-bit (M is an integer of 2 or more) data input pin and an M-bit data output pin, and replaces a defective I / O by a shift redundancy method. A memory cell array having an (M + 1) -bit I / O input and an (M + 1) -bit I / O output corresponding to the I / O input, and address information of the defective I / O. A control means for generating a control signal of (M + 1) bits for replacing the defective I / O based on the address information, and shifting data from the data input pin based on the control signal, Input shift means for supplying to the I / O input of the cell array, and shifting the data from the I / O output of the memory cell array based on the control signal, An output shift means for supplying to the output pin, a first shift input pin is connected to the first input, and a first data input pin of the M-bit data input pins is connected to the second input for output. Is connected to a first I / O input of the (M + 1) -bit I / O inputs, and the first or second input is controlled by a first control signal of the (M + 1) -bit control signals. The first selection means as the input shift means to be selected, and the first I / O output of the (M + 1) -bit I / O output is connected to the first input, and the (M + 1) -bit I / O output A second I / O output of the I / O outputs is connected to a second input, an output is connected to a first data output pin of the M-bit data output pins, and the first control signal The output from which the first or second input is selected; Second selection means as shift means and (m−1) th data input pin (m is an integer, 2 ≦ m ≦ M) among the M-bit data input pins are connected to the first input. The m-th data input pin among the M-bit data input pins is connected to the second input, and the output is connected to the m-th I / O input among the (M + 1) -bit I / O inputs. , (2m−1) th selection means as the input shift means for selecting the first or second input by the mth control signal among the (M + 1) -bit control signals, and the (M + 1) ) The mth I / O output of the bit I / O outputs is connected to the first input, and the (m + 1) th I / O output of the (M + 1) bit I / O outputs is the second. An m-th data output pin of the M-bit data output pins. And (2m) selection means as the output shift means for selecting the first or second input by the mth control signal, and Mth of the M-bit data input pins. The data input pin is connected to the first input, the fixed potential is connected to the second input, and the output is connected to the (M + 1) th I / O input of the (M + 1) -bit I / O inputs. And (2M + 1) selection means as the input shift means for selecting the first or second input by the (M + 1) th control signal among the (M + 1) -bit control signals. A memory macrocell is provided.

  Furthermore, according to a third aspect of the present invention, there is provided a semiconductor device using the first memory macrocell described in the first aspect and the second memory macrocell described in the second aspect. The Nth data input pin of the first memory macrocell is connected to the first shift input pin of the second memory macrocell, and the second shift input pin of the first memory macrocell is connected to the second shift input pin. A shift output pin of the memory macro cell is connected to the semiconductor device.

  According to the present invention, since the redundancy I / O region can be shared by a plurality of memory macrocells, it is possible to improve the yield while suppressing an increase in the chip area of the semiconductor device.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first memory macrocell according to an embodiment of the present invention. Here, the part mainly related to the shift redundancy system is shown.
The first memory macrocell according to the embodiment of the present invention is called an 8-bit I / O input (hereinafter referred to as “In0 to In7”) and an 8-bit I / O output (hereinafter referred to as “Out0 to Out7”). ), An input shift circuit 12 and an output shift circuit 13 for replacing a defective I / O of the C / A 11 by a shift redundancy method, an input shift circuit 12 and an output of the memory cell array 11 (hereinafter referred to as “C / A 11”). A control circuit 14 for generating an 8-bit shift control signal (hereinafter referred to as “SC [0: 7]”) for controlling the data shift of the shift circuit 13, an 8-bit data input pin (hereinafter referred to as “DI0 to DI7”). 8 bit data output pin (hereinafter referred to as “DO0 to DO7”), two shifts to which shift data from other memory macrocells are input. Input pin (hereinafter, referred to as "SI0 and SI7."), And shift the output pin for outputting a shift data to another memory macro cell (hereinafter, referred to as. "SO0") and a.

  The input shift circuit 12 includes eight 2-input selectors 15a to 15h (hereinafter referred to as “selectors 15a to 15h”), and the output shift circuit 13 includes eight 2-input selectors 16a to 16h (hereinafter referred to as “selector 16a”). ~ 16h ").

  SI0 is connected to the first input of the selector 15a, DI0 is connected to the second input, the first bit SC [0] of SC [0: 7] is connected to the control input of the selector 15a, The output of the selector 15a is connected to In0.

  Out0 corresponding to In0 is connected to the first input of the selector 16a, Out1 corresponding to In1 is connected to the second input, SC [0] is connected to the control input of the selector 16a, and the selector 16a Is connected to DO0 corresponding to DI0. Out0 is also connected to SO0.

  DI0 is connected to the first input of the selector 15b, DI1 is connected to the second input, the second bit SC [1] of SC [0: 7] is connected to the control input of the selector 15b, The output of the selector 15b is connected to In1.

  Out1 corresponding to In1 is connected to the first input of the selector 16b, Out2 corresponding to In2 is connected to the second input, SC [1] is connected to the control input of the selector 16b, and the selector 16b Is connected to DO1 corresponding to DI1.

  DI1 is connected to the first input of the selector 15c, DI2 is connected to the second input, the third bit SC [2] of SC [0: 7] is connected to the control input of the selector 15c, The output of the selector 15c is connected to In2.

  Out2 corresponding to In2 is connected to the first input of the selector 16c, Out3 corresponding to In3 is connected to the second input, SC [2] is connected to the control input of the selector 16c, and the selector 16c Is connected to DO2 corresponding to DI2.

  DI2 is connected to the first input of the selector 15d, DI3 is connected to the second input, the fourth bit SC [3] of SC [0: 7] is connected to the control input of the selector 15d, The output of the selector 15d is connected to In3.

  Out3 corresponding to In3 is connected to the first input of the selector 16d, Out4 corresponding to In4 is connected to the second input, SC [3] is connected to the control input of the selector 16d, and the selector 16d Is connected to DO3 corresponding to DI3.

  DI3 is connected to the first input of the selector 15e, DI4 is connected to the second input, the fifth bit SC [4] of SC [0: 7] is connected to the control input of the selector 15e, The output of the selector 15e is connected to In4.

  Out4 corresponding to In4 is connected to the first input of the selector 16e, Out5 corresponding to In5 is connected to the second input, SC [4] is connected to the control input of the selector 16e, and the selector 16e Is connected to DO4 corresponding to DI4.

  DI4 is connected to the first input of the selector 15f, DI5 is connected to the second input, the sixth bit SC [5] of SC [0: 7] is connected to the control input of the selector 15f, The output of the selector 15f is connected to In5.

  Out5 corresponding to In5 is connected to the first input of the selector 16f, Out6 corresponding to In6 is connected to the second input, SC [5] is connected to the control input of the selector 16f, and the selector 16f Is connected to DO5 corresponding to DI5.

  DI5 is connected to the first input of the selector 15g, DI6 is connected to the second input, the seventh bit SC [6] of SC [0: 7] is connected to the control input of the selector 15g, The output of the selector 15g is connected to In6.

  Out6 corresponding to In6 is connected to the first input of the selector 16g, Out7 corresponding to In7 is connected to the second input, SC [6] is connected to the control input of the selector 16g, and the selector 16g Is connected to DO6 corresponding to DI6.

  DI6 is connected to the first input of the selector 15h, DI7 is connected to the second input, the eighth bit SC [7] of SC [0: 7] is connected to the control input of the selector 15h, The output of the selector 15h is connected to In7.

  Out7 corresponding to In7 is connected to the first input of the selector 16h, SI7 is connected to the second input, SC [7] is connected to the control input of the selector 16h, and the output of the selector 16h is DI7. Is connected to DO7 corresponding to.

  The selector 15a and the selector 16a operate complementary to SC [0]. That is, when the selector 15a selects and outputs the first input based on SC [0], the selector 16a selects and outputs the second input based on SC [0]. On the other hand, when the selector 15a selects and outputs the second input based on SC [0], the selector 16a selects and outputs the first input based on SC [0]. Similarly, the selectors 15b to 15h and the selectors 16b to 16h perform complementary operations based on SC [1] to SC [7], respectively.

  The C / A 11 is composed of eight I / O areas composed of a plurality of SRAM (Static Random Access Memory) cells. Each I / O area has one I / O input and one I / O input for data input / output. It has / O output.

  That is, the first I / O area includes In0 as an I / O input and Out0 as an I / O output. Similarly, the second I / O area includes In1 and Out1, and the third I / O area includes a third I / O area. The O region includes In2 and Out2, the fourth I / O region includes In3 and Out3, the fifth I / O region includes In4 and Out4, and the sixth I / O region includes In5 and Out5. The seventh I / O region includes In6 and Out6, and the eighth I / O region includes In7 and Out7.

  In the shift redundancy system, when a defect exists in an SRAM cell belonging to a certain I / O area, the entire I / O area is replaced with another I / O area. A specific replacement method in the semiconductor device using the memory macrocell according to the embodiment of the present invention will be described later with reference to FIGS.

  The control circuit 14 includes a nonvolatile memory circuit that holds address information of a defective cell by a fuse element and a decode circuit that decodes the address information to generate SC [0: 7].

FIG. 2 is a circuit diagram showing a second memory macrocell according to an embodiment of the present invention. Here, the part mainly related to the shift redundancy system is shown.
The second memory macrocell according to the embodiment of the present invention includes a 9-bit I / O input (hereinafter referred to as “In0 to In7 and RIn”) and a 9-bit I / O output (hereinafter referred to as “Out0 to Out7 and Rout ”), an input shift circuit 22 and an output shift circuit 23 for replacing a defective I / O of C / A 21 by a shift redundancy method, input shift A control circuit 24 for generating a 9-bit shift control signal (hereinafter referred to as “SC [0: 8]”) for controlling the data shift of the circuit 22 and the output shift circuit 23, an 8-bit data input pin (hereinafter referred to as “ DI0 to DI7 ”), 8-bit data output pins (hereinafter referred to as“ DO0 to DO7 ”), shift data from other memory macrocells. Shift input pin data is inputted (hereinafter, referred to as "SI0".), And the shift output pin for outputting a shift data to another memory macro cell (hereinafter, referred to as. "SO0") and a.

  The input shift circuit 22 includes nine 2-input selectors 25a to 25j (hereinafter referred to as “selectors 25a to 25j”), and the output shift circuit 23 includes eight 2-input selectors 26a to 26h (hereinafter referred to as “selectors 26a”). ~ 26h ").

  SI0 is connected to the first input of the selector 25a, DI0 is connected to the second input, the first bit SC [0] of SC [0: 7] is connected to the control input of the selector 25a, The output of the selector 25a is connected to In0.

  Out0 corresponding to In0 is connected to the first input of the selector 26a, Out1 corresponding to In1 is connected to the second input, SC [0] is connected to the control input of the selector 26a, and the selector 26a Is connected to DO0 corresponding to DI0. Out0 is also connected to SO0.

  DI0 is connected to the first input of the selector 25b, DI1 is connected to the second input, the second bit SC [1] of SC [0: 7] is connected to the control input of the selector 25b, The output of the selector 25b is connected to In1.

  Out1 corresponding to In1 is connected to the first input of the selector 26b, Out2 corresponding to In2 is connected to the second input, SC [1] is connected to the control input of the selector 26b, and the selector 26b Is connected to DO1 corresponding to DI1.

  DI1 is connected to the first input of the selector 25c, DI2 is connected to the second input, the third bit SC [2] of SC [0: 7] is connected to the control input of the selector 25c, The output of the selector 25c is connected to In2.

  Out2 corresponding to In2 is connected to the first input of the selector 26c, Out3 corresponding to In3 is connected to the second input, SC [2] is connected to the control input of the selector 26c, and the selector 26c Is connected to DO2 corresponding to DI2.

  DI2 is connected to the first input of the selector 25d, DI3 is connected to the second input, the fourth bit SC [3] of SC [0: 7] is connected to the control input of the selector 25d, The output of the selector 25d is connected to In3.

  Out3 corresponding to In3 is connected to the first input of the selector 26d, Out4 corresponding to In4 is connected to the second input, SC [3] is connected to the control input of the selector 26d, and the selector 26d Is connected to DO3 corresponding to DI3.

  DI3 is connected to the first input of the selector 25e, DI4 is connected to the second input, the fifth bit SC [4] of SC [0: 7] is connected to the control input of the selector 25e, The output of the selector 25e is connected to In4.

  Out4 corresponding to In4 is connected to the first input of the selector 26e, Out5 corresponding to In5 is connected to the second input, SC [4] is connected to the control input of the selector 26e, and the selector 26e Is connected to DO4 corresponding to DI4.

  DI4 is connected to the first input of the selector 25f, DI5 is connected to the second input, the sixth bit SC [5] of SC [0: 7] is connected to the control input of the selector 25f, The output of the selector 25f is connected to In5.

  Out5 corresponding to In5 is connected to the first input of the selector 26f, Out6 corresponding to In6 is connected to the second input, SC [5] is connected to the control input of the selector 26f, and the selector 26f Is connected to DO5 corresponding to DI5.

  DI5 is connected to the first input of the selector 25g, DI6 is connected to the second input, the seventh bit SC [6] of SC [0: 7] is connected to the control input of the selector 25g, The output of the selector 25g is connected to In6.

  Out6 corresponding to In6 is connected to the first input of the selector 26g, Out7 corresponding to In7 is connected to the second input, SC [6] is connected to the control input of the selector 26g, and the selector 26g Is connected to DO6 corresponding to DI6.

  DI6 is connected to the first input of the selector 25h, DI7 is connected to the second input, the eighth input SC [7] of SC [0: 7] is connected to the control input of the selector 25h, The output of the selector 25h is connected to In7.

  Out7 corresponding to In7 is connected to the first input of the selector 26h, ROut corresponding to RIn is connected to the second input, SC [7] is connected to the control input of the selector 26h, and the selector 26h Is connected to DO7 corresponding to DI7.

  The first input of the selector 25j is connected to DI7, the second input is connected to the power supply VDD, which is a fixed potential, and the control input of the selector 25j is the ninth bit SC [8 of SC [0: 7]. ] And the output of the selector 25j is connected to RIn.

  The selector 25a and the selector 26a operate complementary to SC [0]. That is, when the selector 25a selects and outputs the first input based on SC [0], the selector 26a selects and outputs the second input based on SC [0]. On the other hand, when the selector 25a selects and outputs the second input based on SC [0], the selector 26a selects and outputs the first input based on SC [0]. Similarly, the selectors 25b to 25h and the selectors 26b to 26h perform complementary operations based on SC [1] to SC [7], respectively.

  The C / A 21 is composed of nine I / O areas composed of a plurality of SRAM cells, and each I / O area has one I / O input and one I / O output for data input / output. Yes.

  That is, the first I / O area includes In0 as an I / O input and Out0 as an I / O output. Similarly, the second I / O area includes In1 and Out1, and the third I / O area includes a third I / O area. The O region includes In2 and Out2, the fourth I / O region includes In3 and Out3, the fifth I / O region includes In4 and Out4, and the sixth I / O region includes In5 and Out5. The seventh I / O region includes In6 and Out6, the eighth I / O region includes In7 and Out7, and the ninth I / O region includes RIn and ROut.

  The ninth I / O area is used as a replacement I / O area (hereinafter referred to as a “redundancy I / O area”) when a defective cell exists. For convenience, “RIn” is used as an I / O input and “ROut” is used as an I / O output as a signal name, but the number and structure of SRAM cells, the circuit configuration of the cell array, etc. are different from those of other I / O regions. It is equivalent.

  In the first memory macrocell described above, the number of data input pins (DI0 to DI7), the number of data output pins (DO0 to DO7), and the number of I / O areas of C / A11 are the same. In the second memory macro cell, the number of I / O areas of C / A 21 is increased by one.

  The control circuit 24 includes a nonvolatile storage circuit that holds address information of a defective cell by a fuse element and a decoding circuit that decodes the address information to generate SC [0: 7].

  FIG. 3 is a circuit diagram showing a semiconductor device using a memory macrocell according to an embodiment of the present invention. Here, the part mainly related to the memory macrocell mounted on the semiconductor device is shown. Further, as an example, a portion related to shift redundancy in the case where an SRAM capable of 16-bit input / output by the 8-bit input / output memory macrocell shown in FIGS. 1 and 2 is shown.

  The semiconductor device using the memory macrocell according to the embodiment of the present invention includes a first memory macrocell 31 (hereinafter referred to as “MMC31”) shown in FIG. 1 and a second memory macrocell 32 ( Hereinafter, it is referred to as “MMC32”).

  The lower 8 bits Data [0: 7] of the 16-bit width data bus Data [0:15] are connected to DI0 to DI7 and DO0 to DO7 of the MMC31, and VDD is connected to SI0 of the MMC31.

  The upper 8 bits Data [8:15] of Data [0:15] are connected to DI0 to DI7 and DO0 to DO7 of MMC32, and Data [7] connected to DI7 of MMC31 is connected to SI0 of MMC32. Then, SO0 of MMC32 is connected to SI7 of MMC31.

Next, the operation of the memory macrocell having the above configuration will be described.
FIG. 4 is an image diagram showing an operation of the first memory macro cell (MMC 31) according to the embodiment of the present invention. Here, as an example, a case where a defective cell exists in the fourth I / O region (In3 / Out3) of C / A11 is shown.

  In the first memory macro cell (MMC 31) according to the embodiment of the present invention, when there is a defective cell, the input shift circuit 12 and the output shift circuit 13 cause an I / O region (hereinafter referred to as “defective”). It operates so as to connect DI0 to DI7 and DO0 to DO7 to the normal I / O area of C / A11.

  First, the control circuit 14 generates SC [0: 7] on the basis of the stored information on the defective address and outputs it to the input shift circuit 12 and the output shift circuit 13. SC [0: 7] is set so that each bit controls the selectors 15a to 15h and the selectors 16a to 16h, and each selector selects and outputs an appropriate one of the two inputs.

  That is, for example, as shown in FIG. 4, when the fourth I / O region is defective I / O, in the input shift circuit 12, DI0 is connected to In0 of C / A11 and DI1 is C / C. Connected to In1 of A11, DI2 connected to In2 of C / A11, DI3 connected to In4 of C / A11, DI4 connected to In5 of C / A11, DI5 connected to In6 of C / A11 DI6 is connected to In7 of C / A11.

  DI7 is not connected to the I / O area of C / A11, and therefore data from DI7 is not stored in C / A11. As shown in FIG. 3, since DI7 is also connected to SI0 of MMC32, the data of DI7 is stored in MMC32 in this case. The operation of the MMC 32 will be described later.

  In the output shift circuit 13, Out0 of C / A11 is connected to DO0, Out1 of C / A11 is connected to DO1, Out2 of C / A11 is connected to DO2, and Out4 of C / A11 is connected to DO3. Connected, Out5 of C / A11 is connected to DO4, Out6 of C / A11 is connected to DO5, and Out7 of C / A11 is connected to DO6.

  DO7 is connected to SI7 that receives shift data from MMC32 by selector 26h based on SC [7].

  FIG. 5 is an image diagram showing the operation of the second memory macro cell (MMC 32) according to the embodiment of the present invention. Here, as an example, a case where a defective I / O exists in C / A 11 of MMC 31 is shown.

  The second memory macro cell (MMC 32) according to the embodiment of the present invention avoids the first I / O region by the input shift circuit 22 and the output shift circuit 23 when a defective I / O exists in the MMC 31. It operates to connect DI0 to DI7 and DO0 to DO7 to the second to ninth I / O regions of C / A21.

  The first I / O area is connected to SI0 and SO0, and is used to store Data [7] that cannot be stored in the MMC 31.

  First, the control circuit 24 generates SC [0: 8] based on the stored information on the defective address and outputs it to the input shift circuit 22 and the output shift circuit 23. SC [0: 7] controls the selectors 25a to 25h and selectors 26a to 26h respectively, and SC [8] controls the selector 25j and selects the appropriate one of the two inputs in each selector. Are set to output.

  That is, for example, when the fourth I / O region of the MMC 31 is a defective I / O, SI0 is connected to In0 of C / A21 in the input shift circuit 22 as shown in FIG. Is connected to In1 of C / A21, DI1 is connected to In2 of C / A21, DI2 is connected to In3 of C / A21, DI3 is connected to In4 of C / A21, and DI4 is In5 of C / A21 DI5 is connected to In6 of C / A21, DI6 is connected to In7 of C / A21, and DI7 is connected to RIn of CA21.

  In the output shift circuit 23, Out0 of C / A21 is connected to SO0, Out1 of C / A21 is connected to DO0, Out2 of C / A21 is connected to DO1, and Out3 of C / A21 is connected to DO2. Connected, Out4 of C / A21 is connected to DO3, Out5 of C / A21 is connected to DO4, Out6 of C / A21 is connected to DO5, Out7 of C / A21 is connected to DO6, and C / A21 ROUT is connected to DO7.

  In this way, even when a defective I / O exists in the MMC 31 that does not have a redundancy I / O area, 16-bit width data can be normally stored using the redundancy I / O area of the MMC 32.

  According to the above embodiment, the redundancy I / O region can be shared by a plurality of memory macrocells, so that it is possible to improve the yield while suppressing an increase in the chip area of the semiconductor device.

  In the above embodiment, the memory macrocell has an 8-bit data input pin and a data output pin. However, the present invention is not limited to this and can be applied to any number of bits in principle. It is. Further, the number of data input / output bits may be different among a plurality of memory macrocells.

  Furthermore, in the above-described embodiment, two memory macrocells (MMC31 and MMC32) are used as an example. However, the present invention is not limited to this. For example, three MMC31 and one MMC32 are used. It can be easily expanded to a bit width.

  Furthermore, in the above-described embodiment, the case where the bit width to be stored is expanded is shown as an example. However, the present invention is not limited to this, and may be applied to, for example, memory macrocells used for different purposes. Is also possible.

  Furthermore, in the above embodiment, the memory cell array is composed of SRAM cells. However, the present invention is not limited to this, and for example, a shift redundancy system such as a DRAM (Dynamic Random Access Memory) cell can be adopted. Any memory cell array can be applied in principle.

1 is a circuit diagram showing a first memory macrocell according to an embodiment of the present invention. The circuit diagram which shows the 2nd memory macrocell concerning the Example of this invention. 1 is a circuit diagram showing a semiconductor device using a memory macrocell according to an embodiment of the present invention. The image figure which shows operation | movement of the 1st memory macrocell (MMC31) concerning the Example of this invention. The image figure which shows operation | movement of the 2nd memory macrocell (MMC32) concerning the Example of this invention.

Explanation of symbols

11, 21 Memory macrocell (C / A)
12, 22 Input shift circuit 13, 23 Output shift circuit 14, 24 Control circuit 15a-15h, 16a-16h, 25a-25j, 26a-26j Selector DI0-DI7 Data input pin DO0-DO7 Data output pin SI0, SI7 Shift input Pin SO0 Shift output pins In0 to In7, RIn I / O input Out0 to Out7, ROut I / O output

Claims (5)

A memory macrocell having an N-bit (N is an integer of 2 or more) data input pin and an N-bit data output pin, and replacing a defective I / O by a shift redundancy method,
A memory cell array having an N-bit I / O input and an N-bit I / O output corresponding to the I / O input;
Control means for holding address information of the defective I / O and generating an N-bit control signal for replacing the defective I / O based on the address information;
Input shift means for shifting data from the data input pins based on the control signal and supplying the data to the I / O inputs of the memory cell array;
Output shift means for shifting data from the I / O output of the memory cell array based on the control signal and supplying the data to the data output pin;
A first shift input pin is connected to a first input, a first data input pin of the N-bit data input pins is connected to a second input, and an output is the N-bit I / O input. The first selection means as the input shift means is connected to the first I / O input, and the first or second input is selected by the first control signal among the N-bit control signals. When,
A first I / O output of the N-bit I / O outputs is connected to a first input, and a second I / O output of the N-bit I / O outputs is connected to a second input. The output is connected to a first data output pin among the N-bit data output pins, and the first or second input is selected by the first control signal. Two selection means;
A shift output pin connected to the first I / O output;
Of the N-bit data input pins, the (n-1) th data input pin (n is an integer, 2 ≦ n ≦ (N−1)) is connected to the first input, and the N-bit data Of the input pins, the nth data input pin is connected to the second input, the output is connected to the nth I / O input of the N-bit I / O input, and the N-bit control signal (2n-1) selection means as the input shift means for selecting the first or the second input by an nth control signal;
An nth I / O output of the N-bit I / O outputs is connected to a first input, and an (n + 1) th I / O output of the N-bit I / O outputs is a second input. As the output shift means, the output is connected to the nth data output pin among the N-bit data output pins, and the first or second input is selected by the nth control signal. (2n) selection means,
Of the N bit data input pins, the (N-1) th data input pin is connected to the first input, and among the N bit data input pins, the Nth data input pin is connected to the second input. And the output is connected to the Nth I / O input of the N-bit I / O inputs, and the first or second input is selected by the Nth control signal of the N-bit control signals. (2N-1) th selection means as the input shift means,
Of the N-bit I / O outputs, an N-th I / O output is connected to a first input, a second shift input pin is connected to a second input, and an output is the N-bit data output pin. And (2N) selection means as the output shift means connected to the Nth data output pin and for selecting the first or the second input by the Nth control signal. A memory macrocell.   The second selection unit selects the second I / O output when the first selection unit selects data from the first shift input pin according to the first control signal. The memory macrocell according to claim 1, wherein the memory macrocell is output to the first data output pin.   The (2N) selection means, when the (2N-1) selection means selects data from the (N-1) th data input pin by the Nth control signal, 2. The memory macrocell according to claim 1, wherein data from the second shift input pin is selected and output to the Nth data output pin. A memory macrocell having a data input pin of M bits (M is an integer of 2 or more) and a data output pin of M bits, and replacing a defective I / O by a shift redundancy method,
A memory cell array having an (M + 1) -bit I / O input and an (M + 1) -bit I / O output corresponding to the I / O input;
Control means for holding address information of the defective I / O and generating a (M + 1) -bit control signal for replacing the defective I / O based on the address information;
Input shift means for shifting data from the data input pins based on the control signal and supplying the data to the I / O inputs of the memory cell array;
Output shift means for shifting data from the I / O output of the memory cell array based on the control signal and supplying the data to the data output pin;
A first shift input pin is connected to a first input, a first data input pin of the M-bit data input pins is connected to a second input, and an output is the (M + 1) -bit I / O. The input shift means is connected to the first I / O input of the inputs, and the first or second input is selected by the first control signal among the (M + 1) -bit control signals. 1 selection means;
The first I / O output of the (M + 1) -bit I / O output is connected to the first input, and the second I / O output of the (M + 1) -bit I / O output is the second I / O output. The output shift is connected to the first data output pin of the M-bit data output pins, and the first or second input is selected by the first control signal. Second selection means as means;
Of the M-bit data input pins, the (m−1) -th data input pin (m is an integer, 2 ≦ m ≦ M) is connected to the first input, and among the M-bit data input pins, The mth data input pin is connected to the second input, the output is connected to the mth I / O input of the (M + 1) -bit I / O input, and the (M + 1) -bit control signal (2m-1) th selection means as the input shift means for selecting the first or the second input by an mth control signal;
Of the (M + 1) -bit I / O outputs, the m-th I / O output is connected to the first input, and among the (M + 1) -bit I / O outputs, the (m + 1) -th I / O output is Connected to a second input, an output is connected to an m-th data output pin among the M-bit data output pins, and the first or the second input is selected by the m-th control signal. (2m) selection means as output shifting means;
The M-th data input pin among the M-bit data input pins is connected to the first input, the fixed potential is connected to the second input, and the output is the first of the (M + 1) -bit I / O inputs. (M + 1) I / O input, and the first or second input is selected by the (M + 1) -th control signal among the (M + 1) -bit control signals. A memory macrocell having (2M + 1) selection means. A first memory macrocell according to claim 1;
A semiconductor device using the second memory macrocell according to claim 4,
An Nth data input pin of the first memory macrocell is connected to a first shift input pin of the second memory macrocell, and the second memory is connected to a second shift input pin of the first memory macrocell. A semiconductor device, wherein a shift output pin of a macro cell is connected.

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