JP2008251729A - Manufacturing method of light-receiving element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a light-receiving element, capable of preventing a second conductivity-type impurity from diffusing on a first semiconductor layer of a light-receiving section. <P>SOLUTION: In a laminate in which a first semiconductor layer (6) made of a first conductivity-type InP and a second semiconductor layer (7) made of a second conductivity-type InP are sequentially formed on a semiconductor substrate (1), the manufacturing method of a semiconductor device (100) includes a step of forming a diffusion suppressing layer (8) containing at least any one of InGaAs and InGaAsP on at least one part of a light-receiving region (7a) of the second semiconductor layer, a step of forming an insulating layer (9) on the diffusion suppressing layer, and a step of thermally diffusing a second conductivity-type impurity into one part of the first semiconductor layer by executing thermal diffusion in an atmosphere containing the second conductivity-type impurity while using the diffusion suppressing layer and the insulating layer as thermal diffusion masks. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a light receiving element.

  In the light receiving element in which the second semiconductor layer of the second conductivity type is provided on the first semiconductor layer of the first conductivity type, the manufacturing includes the step of performing diffusion annealing of the impurity of the second conductivity type around the light receiving portion The method is known. In this diffusion annealing step, an insulating film is used as a diffusion mask so that the second conductivity type impurity is diffusion-annealed in a part of the first semiconductor layer around the light receiving portion (see, for example, Patent Document 1). ). The insulating film used in the technique of Patent Document 1 has been conventionally used as a diffusion mask, and it was thought that diffusion was sufficiently prevented.

JP 2006-339413 A

  However, the inventor has found that the impurity of the second conductivity type may be diffused into the first semiconductor layer of the first conductivity type even in the light receiving portion by the diffusion annealing in the technique of Patent Document 1. . As a result, a desired light response speed may not be obtained.

  An object of the present invention is to provide a method for manufacturing a light receiving element in which the second conductivity type impurity is prevented from diffusing into the first semiconductor layer of the light receiving unit.

  The method for manufacturing a light receiving element according to the present invention includes: a stacked body in which a first semiconductor layer made of a first conductivity type InP and a second semiconductor layer made of a second conductivity type InP are sequentially formed on a semiconductor substrate; Forming a diffusion suppressing layer including at least one of InGaAs and InGaAsP on at least a part of the light receiving region of the semiconductor layer; forming an insulating layer on the diffusion suppressing layer; and thermally diffusing the diffusion suppressing layer and the insulating layer. And a step of thermally diffusing the second conductivity type impurity in a part of the first semiconductor layer by thermally diffusing in an atmosphere containing the second conductivity type impurity as a mask. is there.

  In the method for manufacturing a light receiving element according to the present invention, the diffusion rate of the second conductivity type impurity in the diffusion suppression layer is smaller than the diffusion rate of the second conductivity type impurity in the second semiconductor layer. The diffusion of the second conductivity type impurity to the first semiconductor layer below the light receiving region is suppressed.

  A step of removing the diffusion suppressing layer on the light receiving region may be further included. Further, in the step of removing the diffusion suppression layer, the diffusion suppression layer may be etched in a substantially ring shape. Furthermore, it may further include a step of forming an electrode on the diffusion suppression layer after the step of removing the diffusion suppression layer.

  In the step of forming the diffusion suppression layer, the diffusion suppression layer may be formed over the entire light receiving region of the second semiconductor layer. In this case, the diffusion of the second conductivity type impurity to the first semiconductor layer below the light receiving portion in the annealing process is further suppressed.

  In the step of forming the diffusion suppression layer, the diffusion suppression layer may be formed wider than the light receiving region. Further, in the step of forming the diffusion suppression layer, the diffusion suppression layer may be formed wider than the insulating layer. The light receiving element may be a PIN photodiode or an avalanche photodiode. The light receiving element may have a mesa structure defined by an upper surface and a side surface. Further, the second conductivity type impurity may be Zn, Cd, or Mg.

  Another method of manufacturing a light receiving element according to the present invention is the first method in a stacked body in which a first semiconductor layer made of a first conductivity type InP and a second semiconductor layer made of a second conductivity type InP are sequentially formed on a semiconductor substrate. Forming a diffusion suppression layer having an impurity diffusion rate smaller than the impurity diffusion rate in the second semiconductor layer on at least a part of the light receiving region of the two semiconductor layers; forming an insulating layer on the diffusion suppression layer; Thermally diffusing the second conductive type impurity into a part of the first semiconductor layer by thermally diffusing in an atmosphere containing the second conductive type impurity using the diffusion layer and the insulating layer as a thermal diffusion mask; It is characterized by including. In another method for manufacturing a light receiving element according to the present invention, since the diffusion rate of the second conductivity type impurity in the diffusion suppression layer is smaller than the diffusion rate of the second conductivity type impurity in the second semiconductor layer, annealing is performed. The diffusion of the second conductivity type impurity to the first semiconductor layer below the light receiving region in the process is suppressed.

  In the step of forming the diffusion suppression layer, the diffusion suppression layer may be formed over the entire light receiving region of the second semiconductor layer. In this case, the diffusion of the second conductivity type impurity to the first semiconductor layer below the light receiving portion in the annealing process is further suppressed. The diffusion suppression layer may be a ternary semiconductor layer or a quaternary semiconductor layer. In the step of forming the diffusion suppression layer, the diffusion suppression layer may be formed wider than the light receiving region.

  According to the present invention, diffusion of impurities of the second conductivity type into the first semiconductor layer of the light receiving unit can be suppressed.

  Hereinafter, the best mode for carrying out the present invention will be described.

(First embodiment)
1 to 4 are flowcharts for explaining a method of manufacturing a light receiving element according to the first embodiment of the present invention. Hereinafter, a method for manufacturing the light receiving element will be described with reference to FIGS.

  First, as shown in FIG. 1A, on a semiconductor substrate 1 made of InP, a buffer layer 2 made of n-type InP, a light absorption layer 3 made of n-type or i-type InGaAs, and an impact relaxation made of n-type InGaAsP. The layer 4, the field dropping layer 5 made of n-type InP, the multiplication layer 6 made of n-type or i-type InP, the window layer 7 made of p-type InP, and the diffusion suppression layer 8 made of p-type InGaAs are grown in this order.

  For example, the semiconductor substrate 1 has a thickness of 350 μm, the buffer layer 2 has a thickness of 1.0 μm, the light absorption layer 3 has a thickness of 1.0 μm, and the impact relaxation layer 4 has a thickness of 0. 05 μm, the layer thickness of the electric field drop layer 5 is 0.05 μm, the layer thickness of the multiplication layer 6 is 0.05 μm, the layer thickness of the window layer 7 is 1.0 μm, and the diffusion suppression layer 8 The layer thickness is 0.3 μm.

Next, as shown in FIG. 1B, an insulating layer 9 made of an insulator such as SiO ₂ is formed on the diffusion suppression layer 8, and a substantially circular resist 10 is formed on the central portion of the insulating layer 9. Form. The layer thickness of the insulating layer 9 is, for example, about 0.6 μm. Next, as shown in FIG. 1C, the insulating layer 9 and the diffusion suppression layer 8 in the region where the resist 10 is not formed are removed by etching. For the etching of the diffusion suppressing layer 8, a solution obtained by diluting sulfuric acid and hydrogen peroxide with water can be used as an etching solution. The etching treatment may be performed so that the diffusion suppression layer 8 has a larger area than the insulating layer 9.

  Next, as shown in FIG. 2A, the stacked body shown in FIG. 1C is subjected to a heat treatment (annealing process) in an atmosphere containing the p-type impurity doped in the window layer 7. This annealing process is performed for 30 minutes in an atmosphere of a p-type impurity concentration of, for example, 500 ppm to 2000 ppm and 600 ° C. By this annealing treatment, p-type impurities are diffused from the window layer 7 to the multiplication layer 6 below the region where the diffusion suppression layer 8 is not formed. Therefore, the window layer 7 expands to the multiplication layer 6 below the region where the diffusion suppression layer 8 is not formed. Note that Zn, Cd, Mg, or the like can be used as the p-type impurity.

  Next, as shown in FIG. 2B, a resist 11 is formed on the exposed region of the window layer 7 and on the outer peripheral portion of the insulating layer 9, and regions other than the outer peripheral portion of the diffusion suppressing layer 8 and the insulating layer 9 are formed. Remove by etching. Next, as shown in FIG. 2C, the resist 11 and the insulating layer 9 are removed. Thereby, the substantially ring-shaped diffusion suppression layer 8 is exposed. The window layer 7 inside the diffusion suppression layer 8 becomes the light receiving region 7a.

Next, as shown in FIG. 3A, the insulating layer 12 made of an insulator such as SiO ₂ is formed on the diffusion suppressing layer 8 and the region excluding the outer peripheral portion of the window layer 7. Next, as shown in FIG. 3B, an ICP dry etching process is performed using the insulating layer 12 as a mask. In this case, etching is performed until the buffer layer 2 is exposed. Thereby, the mesa structure 20 including the semiconductor substrate 1, the buffer layer 2, the light absorption layer 3, the impact relaxation layer 4, the electric field drop layer 5, the multiplication layer 6, the window layer 7, and the diffusion suppression layer 8 is formed. In the ICP dry etching in this case, for example, the antenna power is set to 200 W, the bias power is set to 100 W, SiCl ₄ / Ar is used as the etching gas, and the atmosphere is 0.5 Pa to 0.7 Pa and 150 ° C. to 150 ° C. Adjust to 250 ° C.

Next, as shown in FIG. 3C, a passivation film 13 made of InP is formed on the exposed portion of the buffer layer 2 and the side wall of the mesa structure 20. In the passivation in this case, the atmosphere is PH ₃ , the temperature is set to 600 ° C., and the growth rate is set to 2.0 μm / h. Next, as shown in FIG. 4A, the insulating layer 12 is removed, and a protective film 14 made of an insulator such as SiN is formed on the passivation film 13, the window layer 7, and the diffusion suppression layer 8. Thereafter, the protective film 14 on the diffusion suppression layer 8 is removed. Thereby, the diffusion suppression layer 8 is exposed.

  Next, as shown in FIG. 4B, a p-side electrode 15 made of Ti / Pt / Au or the like is formed on the diffusion suppression layer 8 and an n-side made of AuGe / Au or the like is formed on the lower surface of the semiconductor substrate 1. The electrode 16 is formed. Through the above steps, the avalanche photodiode type light receiving element 100 is completed. The light receiving element 100 is a surface incident type light receiving element in which light enters from the protective film 14 side.

  In the present embodiment, the p-type impurity diffusion rate in the diffusion suppression layer 8 is smaller than the p-type impurity diffusion rate in the window layer 7. This is because the diffusion suppression layer 8 is made of a ternary semiconductor or a quaternary semiconductor, whereas the window layer 7 is made of a binary semiconductor. That is, the number of semiconductor elements constituting the diffusion suppression layer 8 is larger than the number of semiconductor elements constituting the window layer 7.

  In this case, in the annealing process shown in FIG. 2A, diffusion of p-type impurities to the multiplication layer 6 below the light receiving region 7a is suppressed. Thereby, the fall of the light reception sensitivity of the light receiving element 100 which concerns on this embodiment can be suppressed. Moreover, since the diffusion suppression layer 8 is used as a contact layer, it is not necessary to form the diffusion suppression layer 8 and the contact layer separately. Therefore, the manufacturing process is simplified.

  If the diffusion suppressing layer 8 is provided in at least a part of the light receiving region 7a of the window layer 7 in the annealing process, diffusion of the p-type impurity to the multiplication layer 6 below the light receiving region 7a is suppressed. Therefore, the diffusion suppression layer 8 only needs to be provided in at least a part of the light receiving region 7a of the window layer 7 in the annealing process. However, if the diffusion suppression layer 8 is provided on the entire surface of the light receiving region 7a of the window layer 7, the diffusion of the p-type impurity into the multiplication layer 6 below the light receiving region 7a is further suppressed.

(Second Embodiment)
FIG. 5 is a flowchart for explaining the manufacturing method of the light receiving element according to the second embodiment of the present invention. Hereinafter, a method for manufacturing the light receiving element will be described with reference to FIG. First, as shown in FIG. 5A, the mesa structure 20 shown in FIG. 3C is prepared. Next, as shown in FIG. 5B, the insulating layer 12 is removed, and a protective film 14 made of an insulator such as SiN is formed on the passivation film 13, the window layer 7, and the diffusion suppression layer 8. Thereafter, a part of the passivation film 13 and the protective film 14 on the diffusion suppression layer 8, the window layer 7, and the buffer layer 2 are removed by etching. As a result, the diffusion suppressing layer 8 and the light receiving region 7a are exposed and a part of the buffer layer 2 is exposed.

  Next, as shown in FIG. 5C, a reflection film 17 made of SiN or the like is formed on the window layer 7 inside the diffusion suppression layer 8, and Ti / Pt / is formed on the diffusion suppression layer 8 and the reflection film 17. A p-side electrode 15 made of Au or the like is formed, and an n-side electrode 16 made of AuGe / Au or the like is formed in the exposed region of the buffer layer 2. The light receiving element 100a is completed through the above steps. The light receiving element 100a is a back-illuminated light receiving element that receives light from the semiconductor substrate 1 side.

  Also in the present embodiment, diffusion of p-type impurities to the multiplication layer 6 under the light receiving region 7a is suppressed in the annealing process. Thereby, the fall of the light reception sensitivity of the light receiving element 100a which concerns on this embodiment can be suppressed. Moreover, since the diffusion suppression layer 8 is used as a contact layer, it is not necessary to form the diffusion suppression layer 8 and the contact layer separately. Therefore, the manufacturing process is simplified.

  If the diffusion suppressing layer 8 is provided in at least a part of the light receiving region 7a of the window layer 7 in the annealing process, diffusion of the p-type impurity to the multiplication layer 6 below the light receiving region 7a is suppressed. Therefore, the diffusion suppression layer 8 only needs to be provided in at least a part of the light receiving region 7a of the window layer 7 in the annealing process. However, if the diffusion suppression layer 8 is provided on the entire surface of the light receiving region 7a of the window layer 7, the diffusion of the p-type impurity into the multiplication layer 6 below the light receiving region 7a is further suppressed.

  In each of the above embodiments, the diffusion suppression layer is provided in the light receiving region in the avalanche photodiode type light receiving element. However, in the PIN type photodiode type light receiving element, a diffusion suppression layer is provided in the light receiving region and annealed. Also good. In the above embodiment, the multiplication layer 6 corresponds to the first semiconductor layer, and the window layer 7 corresponds to the second semiconductor layer.

(Experimental example)
Hereinafter, experimental results for explaining the effect of the diffusion suppressing layer 8 will be described. First, a sample 200 shown in FIG. 6 was prepared. The sample 200 is the same as that shown in FIG. 1C except that the diffusion suppression layer 8 is provided only in the vicinity of the outer periphery of the light receiving region 7a and the insulating layer 9 is not provided in the outer peripheral portion of the diffusion suppression layer 8. This has the same structure as the laminate. The window layer 7 of the sample 200 includes a region A in which neither the diffusion suppression layer 8 nor the insulating layer 9 is provided, a region B in which the insulating layer 9 is provided but the diffusion suppression layer 8 is not provided, and diffusion suppression. It is divided into a region C in which the layer 8 is provided but the insulating layer 9 is not provided, and a region D in which both the diffusion suppression layer 8 and the insulating layer 9 are provided.

  The regions A to D were annealed in an atmosphere containing p-type impurities, and the state of diffusion of the p-type impurities in each region was examined. In this case, Zn was used as the p-type impurity. The annealing conditions are the same as in the annealing process of FIG. FIG. 7 shows a Zn concentration profile in the depth direction of each region. SIMS analysis was used to measure the Zn concentration. In FIG. 7, the vertical axis represents the Zn concentration, and the horizontal axis represents the depth from the upper surface of the window layer 7. Moreover, E of FIG. 7 has shown the measurement result of the area | region A which has not performed annealing treatment.

  As shown in FIG. 7, in the region A, the Zn profile reaches the deepest point. This is because neither the insulating layer 9 nor the diffusion suppression layer 8 is provided. In region B and region C, the Zn profile was shallower than in region A. This is because either the insulating layer 9 or the diffusion suppression layer 8 is provided. In the region D, the Zn profile was further shallower than those in the regions A to C, and was almost equal to the Zn profile in the region A (region E) before annealing. Therefore, it was found that the region D was hardly affected by the annealing process. This is presumably because the diffusion suppression layer 8 is provided under the insulating layer 9.

  FIG. 8 shows the relationship between the Zn diffusion depth and the annealing time in each region. In FIG. 8, the vertical axis indicates the Zn diffusion depth, and the horizontal axis indicates the annealing treatment time. In the region A, the Zn diffusion depth was the largest. In the region B and the region C, the Zn diffusion depth was smaller than that in the region A. On the other hand, in the region D, Zn is hardly diffused. This is considered to be because the diffusion of Zn was suppressed by providing the diffusion suppression layer 8 under the insulating layer 9. These relationships do not change even if the annealing time is increased.

  Next, voltage-current characteristics when a reverse bias was applied to the sample 200 in a state where light was incident on the light receiving region of the sample 200 were examined. FIG. 9A shows the voltage-current characteristics of the sample 200 when a reverse bias is applied. In FIG. 9A, the horizontal axis represents the applied voltage, the left vertical axis represents the net current (photocurrent) that flows due to light incidence, and the right vertical axis represents the value obtained by differentiating the photocurrent with the applied voltage. Show. The solid line shows the relationship between the voltage and the photocurrent, and the broken line shows the relationship between the voltage and the value obtained by differentiating the photocurrent with the applied voltage.

  As shown in FIG. 9A, the photocurrent increases as the voltage increases. This is due to the expansion of the depletion layer. As the voltage increases, the differential value indicates the initial maximum value α. This is presumably because the depletion layer in the region A has reached the light absorption layer 3 and the pn junction surface in the region A is closest to the light absorption layer 3. When the voltage is further increased, the differential value shows the next maximum value β. This is presumably because the depletion layer in the region B has reached the light absorption layer 3. When the voltage is further increased, the differential value shows the next maximum value γ. This is presumably because the depletion layer in the region D has reached the light absorption layer 3.

  From the result shown in FIG. 9A, it is considered that in the sample 200, the voltage-current characteristic is changed due to the Zn diffusion distance in each of the region A, the region B, and the region D. Therefore, it is proved that there is a difference between the Zn diffusion distance in the region B and the Zn diffusion distance in the region D based on the electrical characteristics. On the other hand, in the laminated body of FIG. 1C, since the diffusion suppression layer 8 is also provided in the region B, the maximum value β due to the region B appears as shown in FIG. 9B. It is not considered.

  From the above, it was revealed that the diffusion of the p-type impurity in the annealing process can be suppressed by providing the diffusion suppressing layer 8 in the light receiving region 7a.

It is a flowchart for demonstrating the manufacturing method of the light receiving element which concerns on the 1st Embodiment of this invention. It is a flowchart for demonstrating the manufacturing method of the light receiving element which concerns on the 1st Embodiment of this invention. It is a flowchart for demonstrating the manufacturing method of the light receiving element which concerns on the 1st Embodiment of this invention. It is a flowchart for demonstrating the manufacturing method of the light receiving element which concerns on the 1st Embodiment of this invention. It is a flowchart for demonstrating the manufacturing method of the light receiving element which concerns on the 2nd Embodiment of this invention. It is a figure for demonstrating the sample which concerns on an experiment example. It is a figure which shows Zn density | concentration in the depth direction of each area | region of a sample. It is a figure which shows the diffusion amount of Zn in each area | region of a sample. It is a figure which shows the voltage-current characteristic at the time of reverse bias application.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Buffer layer 3 Light absorption layer 4 Impact relaxation layer 5 Electric field drop layer 6 Multiplication layer 7 Window layer 7a Light reception area | region 8 Diffusion suppression layer 9 Insulating layer 15 p side electrode 16 n side electrode 20 Mesa structure 100 Light receiving element

Claims (14)

In a stacked body in which a first semiconductor layer made of a first conductivity type InP and a second semiconductor layer made of a second conductivity type InP are sequentially formed on a semiconductor substrate, at least a part of the light receiving region of the second semiconductor layer Forming a diffusion suppression layer containing at least one of InGaAs and InGaAsP on
Forming an insulating layer on the diffusion suppressing layer;
Using the diffusion suppression layer and the insulating layer as a thermal diffusion mask, thermal diffusion is performed in an atmosphere containing the second conductivity type impurity, whereby the second conductivity type impurity is part of the first semiconductor layer. And a step of thermally diffusing the light receiving element.   The method for manufacturing a light receiving element according to claim 1, further comprising a step of removing the diffusion suppression layer on the light receiving region.   The method for manufacturing a light receiving element according to claim 1, wherein in the step of removing the diffusion suppression layer, the diffusion suppression layer is etched in a substantially ring shape.   4. The method for manufacturing a light receiving element according to claim 2, further comprising a step of forming an electrode on the diffusion suppression layer after the step of removing the diffusion suppression layer.   5. The method for manufacturing a light receiving element according to claim 1, wherein in the step of forming the diffusion suppression layer, the diffusion suppression layer is formed over the entire light receiving region of the second semiconductor layer.   The method for manufacturing a light receiving element according to claim 1, wherein, in the step of forming the diffusion suppression layer, the diffusion suppression layer is formed wider than the light receiving region.   The method for manufacturing a light receiving element according to claim 1, wherein in the step of forming the diffusion suppression layer, the diffusion suppression layer is formed wider than the insulating layer.   The method for manufacturing a light receiving element according to claim 1, wherein the light receiving element is a PIN photodiode or an avalanche photodiode.   The method for manufacturing a light receiving element according to claim 1, wherein the light receiving element has a mesa structure defined by an upper surface and a side surface.   The light receiving element manufacturing method according to claim 1, wherein the second conductivity type impurity is Zn, Cd, or Mg. In a stacked body in which a first semiconductor layer made of a first conductivity type InP and a second semiconductor layer made of a second conductivity type InP are sequentially formed on a semiconductor substrate, at least a part of the light receiving region of the second semiconductor layer Forming a diffusion suppression layer having an impurity diffusion rate smaller than the impurity diffusion rate in the second semiconductor layer;
Forming an insulating layer on the diffusion suppressing layer;
Using the diffusion layer and the insulating layer as a thermal diffusion mask, thermal diffusion is performed in an atmosphere containing the second conductivity type impurity, thereby allowing the second conductivity type impurity to be part of the first semiconductor layer. And a step of thermally diffusing the light receiving element.   12. The method for manufacturing a light receiving element according to claim 11, wherein in the step of forming the diffusion suppression layer, the diffusion suppression layer is formed over the entire light receiving region of the second semiconductor layer.   The method for manufacturing a light receiving element according to claim 11, wherein the diffusion suppression layer is formed of a ternary semiconductor layer or a quaternary semiconductor layer. The method for manufacturing a light receiving element according to claim 11, wherein in the step of forming the diffusion suppression layer, the diffusion suppression layer is formed wider than the light receiving region.

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