JP2008251611A - Thin composite element and manufacturing process of the same - Google Patents

Thin composite element and manufacturing process of the same Download PDF

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JP2008251611A
JP2008251611A JP2007087712A JP2007087712A JP2008251611A JP 2008251611 A JP2008251611 A JP 2008251611A JP 2007087712 A JP2007087712 A JP 2007087712A JP 2007087712 A JP2007087712 A JP 2007087712A JP 2008251611 A JP2008251611 A JP 2008251611A
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JP4760753B2 (en
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Kensho Nagatomo
憲昭 長友
Kazutaka Fujiwara
和崇 藤原
Yoshinori Adachi
美紀 足立
Hitoshi Inaba
均 稲場
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Mitsubishi Materials Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To obtain a thin and small-sized composite element that is resistive to ESD by forming a thermistor and a varistor in the form of a thin-film single chip. <P>SOLUTION: The thin composite element 10 is provided with: a thin-film varistor 12 formed on an insulated substrate 11; a pair of interdigitized electrodes 13, 14 provided in opposition with each other and formed of a conductive layer formed on the thin-film varistor; a thin-film thermistor 16 covering the thin-film varistor and electrodes 13, 14 to expose each substrate of these electrodes bridging over a pair of interdigitized electrodes; first and a second leadout electrodes 17, 18 formed on the insulated substrate on which the thin-film varistor is not formed, for electrical connection with an exposed base portion of one of the pair of interdigitized electrodes; and a protection film 19 covering all elements 12, 13, 14, 16 on the substrate, except for the pads 17c, 18c for connection of the lead wires of the electrodes 17, 18. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、薄膜サーミスタと薄膜バリスタを有する薄型複合素子及びその製造方法に関するものである。   The present invention relates to a thin composite element having a thin film thermistor and a thin film varistor, and a method for manufacturing the same.

従来、負特性サーミスタでは、人体モデル(直列抵抗1.5kΩを介しての100pFからの放電)において15kVを超えるESD(Electro Static Discharge)が加わった場合、数%〜数十%の抵抗値の変動が生じる場合があり、必ずしも信頼性が十分ではなかった。この点を改善するために、負特性を有する半導体セラミックスからなる負特性サーミスタ素子と、バリスタ特性を有する半導体セラミックスからなるバリスタ素子とが、内部電極を介して積層一体化された積層複合素子を備え、負特性サーミスタ素子とバリスタ素子とが電気的に並列に接続されるように積層複合素子に外部電極を配設した、負特性サーミスタ装置が開示されている(例えば、特許文献1参照。)。   Conventionally, in a negative thermistor, when an ESD (Electro Static Discharge) exceeding 15 kV is applied to a human body model (discharge from 100 pF through a series resistance of 1.5 kΩ), the resistance value fluctuates by several to several tens of percent. May occur, and the reliability is not always sufficient. In order to improve this point, there is provided a multilayer composite element in which a negative characteristic thermistor element made of semiconductor ceramic having negative characteristics and a varistor element made of semiconductor ceramics having varistor characteristics are laminated and integrated through an internal electrode. In addition, a negative characteristic thermistor device is disclosed in which an external electrode is disposed in a multilayer composite element so that a negative characteristic thermistor element and a varistor element are electrically connected in parallel (see, for example, Patent Document 1).

この負特性サーミスタ装置の積層複合素子は、負特性を有する半導体セラミックス原料をシート状に成形した負特性サーミスタ素子形成用の所定枚数のグリーンシートであって、所定のものには内部電極パターンが配設されたグリーンシートと、バリスタ特性を有する半導体セラミックスをシート状に成形したバリスタ素子形成用の所定枚数のグリーンシートであって、所定のものには内部電極パターンが配設されたグリーンシートを一体に積層して積層体を形成した後、この積層体を焼成して、負特性サーミスタ素子とバリスタ素子が、内部電極を介して積層一体化して形成される。この負特性サーミスタ装置によれば、製造コストの増大を招くことなく、携帯機器の小型化に対応することが可能で、ESDに強く、小型で信頼性が高くなる。
特開2002−252103(請求項1、[0004]、要約)
The laminated composite element of this negative characteristic thermistor device is a predetermined number of green sheets for forming a negative characteristic thermistor element obtained by forming a semiconductor ceramic material having negative characteristics into a sheet shape, and an internal electrode pattern is arranged on the predetermined one. A predetermined number of green sheets for forming a varistor element in which a semiconductor ceramic having varistor characteristics is formed into a sheet shape, and a predetermined green sheet having an internal electrode pattern disposed thereon are integrated. After the laminate is formed, the laminate is fired, and the negative temperature coefficient thermistor element and the varistor element are laminated and integrated through the internal electrodes. According to this negative characteristic thermistor device, it is possible to cope with the downsizing of the portable device without increasing the manufacturing cost, and it is strong against ESD, small in size, and high in reliability.
JP 2002-252103 (Claim 1, [0004], summary)

特許文献1に示される負特性サーミスタ装置は、セラミックグリーンシートの積層体を一体的に焼結したバルク構造であるため、サーミスタ素子の熱容量が大きく、熱応答性が低い欠点があった。またこの装置は小型化したとは言え、バルク構造であるため、小型化の程度は未だ十分ではない。   Since the negative characteristic thermistor device shown in Patent Document 1 has a bulk structure in which a laminate of ceramic green sheets is integrally sintered, the thermistor element has a large heat capacity and a low thermal response. Although this device is downsized, it has a bulk structure, so the degree of downsizing is not sufficient.

本発明の目的は、サーミスタ及びバリスタをそれぞれ薄膜で構成して1チップ化することにより、ESDに強く、薄くて小型の高速熱応答性の高い薄型複合素子及びその製造方法を提供することにある。   An object of the present invention is to provide a thin composite element that is strong against ESD, is thin, small, and has high-speed thermal response, and a method of manufacturing the same, by forming a thermistor and a varistor into a single chip by forming each thermistor and varistor into one chip. .

本願請求項1に係る発明は、図1及び図2に示すように、絶縁基板11上に形成された薄膜バリスタ12と、この薄膜バリスタ12上に形成された導電層からなる相対向する一対の櫛型電極13,14と、この一対の櫛型電極13,14を跨いでかつ一対の櫛型電極の各基部が露出するように上記薄膜バリスタ12及び電極13,14を被覆する薄膜サーミスタ16と、この一対の櫛型電極13,14の一方の露出した基部と電気的に接続するように上記薄膜バリスタ12の形成されていない絶縁基板11上に形成された第1引出電極17と、一対の櫛型電極13,14の他方の露出した基部と電気的に接続するように上記薄膜バリスタ12の形成されていない絶縁基板11上に形成された第2引出電極18と、これらの第1及び第2引出電極17,18における引出線を接続するためのパッド部17c,18cを除いた基板上のすべての素子12,13,14,16を被覆する保護膜19とを備えた薄型複合素子10である。   As shown in FIGS. 1 and 2, the invention according to claim 1 of the present application is a pair of opposed thin film varistors 12 formed on an insulating substrate 11 and conductive layers formed on the thin film varistor 12. A comb-shaped electrode 13, 14 and a thin-film thermistor 16 covering the thin-film varistor 12 and the electrodes 13, 14 so as to straddle the pair of comb-shaped electrodes 13, 14 and expose the bases of the pair of comb-shaped electrodes; A first extraction electrode 17 formed on the insulating substrate 11 on which the thin film varistor 12 is not formed so as to be electrically connected to one exposed base of the pair of comb-shaped electrodes 13 and 14; A second extraction electrode 18 formed on the insulating substrate 11 where the thin film varistor 12 is not formed so as to be electrically connected to the other exposed base of the comb electrodes 13 and 14; 2 drawing electricity Pad portion 17c for connecting the lead wire of 17, a thin composite element 10 having a protective film 19 which covers all the elements 12,13,14,16 in the substrate except for 18c.

本願請求項5に係る発明は、図4に示すように、絶縁基板21上に形成された薄膜サーミスタ22と、この薄膜サーミスタ22上に形成された導電層からなる相対向する一対の櫛型電極23,24と、この一対の櫛型電極23,24を跨いでかつ一対の櫛型電極の各基部が露出するように上記薄膜サーミスタ22及び電極23,24を被覆する薄膜バリスタ26と、この一対の櫛型電極23,24の一方の露出した基部と電気的に接続するように上記薄膜サーミスタ22の形成されていない絶縁基板21上に形成された第3引出電極27と、一対の櫛型電極23,24の他方の露出した基部と電気的に接続するように上記薄膜サーミスタ22の形成されていない絶縁基板21上に形成された第4引出電極28と、これらの第3及び第4引出電極27,28における引出線を接続するためのパッド部27c,28cを除いた基板上のすべての素子22,23,24,26を被覆する保護膜29とを備えた薄型複合素子20である。   As shown in FIG. 4, the invention according to claim 5 of the present application is a pair of opposing comb electrodes comprising a thin film thermistor 22 formed on an insulating substrate 21 and a conductive layer formed on the thin film thermistor 22. 23, 24, and the thin film varistor 26 covering the thin film thermistor 22 and the electrodes 23, 24 so as to straddle the pair of comb electrodes 23, 24 and expose the bases of the pair of comb electrodes. A third lead electrode 27 formed on the insulating substrate 21 where the thin film thermistor 22 is not formed so as to be electrically connected to one exposed base of the comb electrodes 23, 24, and a pair of comb electrodes A fourth extraction electrode 28 formed on the insulating substrate 21 on which the thin film thermistor 22 is not formed so as to be electrically connected to the other exposed bases 23 and 24, and the third and fourth extraction powers. Pad portion 27c for connecting the lead wire of 27, a thin composite element 20 having a protective film 29 which covers all the elements 22,23,24,26 in the substrate except for 28c.

本願請求項9に係る発明は、図1及び図2に示すように、絶縁基板11上に所定のパターンで薄膜バリスタ12を形成する工程と、この薄膜バリスタ12上に導電層からなる相対向する一対の櫛型電極13,14を形成する工程と、この一対の櫛型電極13,14を跨いでかつ一対の櫛型電極の各基部が露出するように上記薄膜バリスタ12及び電極13,14を薄膜サーミスタ16で被覆する工程と、この一対の櫛型電極13,14の一方の露出した基部と電気的に接続するように上記薄膜バリスタ12の形成されていない絶縁基板11上に第1引出電極17を形成する工程と、この一対の櫛型電極13,14の他方の露出した基部と電気的に接続するように上記薄膜バリスタ12の形成されていない絶縁基板11上に第2引出電極18を形成する工程と、これらの第1及び第2引出電極17,18における引出線を接続するためのパッド部17c,18cを除いた基板上のすべての素子12,13,14,16を保護膜19により被覆する工程とを含む薄型複合素子10の製造方法である。   In the invention according to claim 9 of the present application, as shown in FIGS. 1 and 2, a process of forming a thin film varistor 12 with a predetermined pattern on an insulating substrate 11 and a conductive layer on the thin film varistor 12 are opposed to each other. The step of forming the pair of comb-shaped electrodes 13 and 14 and the thin film varistor 12 and the electrodes 13 and 14 so as to straddle the pair of comb-shaped electrodes 13 and 14 and expose the bases of the pair of comb-shaped electrodes. The step of covering with the thin film thermistor 16 and the first extraction electrode on the insulating substrate 11 on which the thin film varistor 12 is not formed so as to be electrically connected to one exposed base of the pair of comb electrodes 13 and 14 17 and a second extraction electrode 18 on the insulating substrate 11 where the thin film varistor 12 is not formed so as to be electrically connected to the other exposed base of the pair of comb electrodes 13 and 14. The protective film 19 includes all the elements 12, 13, 14, and 16 on the substrate except the pad portions 17c and 18c for connecting the lead lines in the first and second lead electrodes 17 and 18 and the process of forming the lead wires. And manufacturing the thin composite element 10.

本願請求項13に係る発明は、図4に示すように、絶縁基板21上に所定のパターンで薄膜サーミスタ22を形成する工程と、この薄膜サーミスタ22上に導電層からなる相対向する一対の櫛型電極23,24を形成する工程と、この一対の櫛型電極23,24を跨いでかつ一対の櫛型電極の各基部が露出するように上記薄膜サーミスタ22及び電極23,24を薄膜バリスタ26で被覆する工程と、この一対の櫛型電極23,24の一方の露出した基部と電気的に接続するように上記薄膜サーミスタ22の形成されていない絶縁基板21上に第3引出電極27を形成する工程と、この一対の櫛型電極23,24の他方の露出した基部と電気的に接続するように上記薄膜サーミスタ22の形成されていない絶縁基板21上に第4引出電極28を形成する工程と、これらの第3及び第4引出電極27,28における引出線を接続するためのパッド部27c,28cを除いた基板上のすべての素子22,23,24,26を保護膜29により被覆する工程とを含む薄型複合素子20の製造方法である。   As shown in FIG. 4, the invention according to claim 13 of the present invention is a process of forming a thin film thermistor 22 in a predetermined pattern on an insulating substrate 21, and a pair of opposing combs made of conductive layers on the thin film thermistor 22. The thin film thermistor 22 and the electrodes 23 and 24 are formed into a thin film varistor 26 so as to straddle the pair of comb electrodes 23 and 24 and to expose the bases of the pair of comb electrodes. And a third extraction electrode 27 is formed on the insulating substrate 21 on which the thin film thermistor 22 is not formed so as to be electrically connected to one exposed base portion of the pair of comb-shaped electrodes 23 and 24. And a fourth extraction electrode 28 on the insulating substrate 21 where the thin film thermistor 22 is not formed so as to be electrically connected to the other exposed base of the pair of comb-shaped electrodes 23, 24. A protective film 29 is formed on all the elements 22, 23, 24, 26 on the substrate except for the step of forming and the pad portions 27c, 28c for connecting the lead lines in the third and fourth lead electrodes 27, 28. And manufacturing the thin composite element 20.

本願請求項3又は7に係る発明は、請求項1又は5に係る発明であって、絶縁基板11,21が基板上面に絶縁膜11b,21bを有するシリコン基板11a,21aであり、薄膜バリスタ12又は薄膜サーミスタ22の下方に絶縁膜11b、21bを残してシリコン基板11a,21aの空洞又は凹部11c,21cが形成された薄型複合素子10,20である。   The invention according to claim 3 or 7 of the present application is the invention according to claim 1 or 5, wherein the insulating substrates 11 and 21 are silicon substrates 11 a and 21 a having insulating films 11 b and 21 b on the upper surface of the substrate. Alternatively, the thin composite elements 10 and 20 are formed in which the cavities or recesses 11c and 21c of the silicon substrates 11a and 21a are formed with the insulating films 11b and 21b left below the thin film thermistor 22.

本願請求項11又は15に係る発明は、請求項9又は13に係る発明であって、絶縁基板11,21が基板上面に絶縁膜11b,21bを有するシリコン基板11a,21aであって、薄膜バリスタ12又は薄膜サーミスタ22の下方に絶縁膜11b,21bをエッチングストッパとしてエッチングによりシリコン基板11a,21aの空洞又は凹部11c,21cを形成する薄型複合素子10,20の製造方法である。   The invention according to claim 11 or 15 of the present application is the invention according to claim 9 or 13, wherein the insulating substrates 11 and 21 are silicon substrates 11a and 21a having insulating films 11b and 21b on the upper surface of the substrate, respectively, and a thin film varistor. 12 or the thin film thermistor 22 is a method for manufacturing the thin composite elements 10 and 20 in which the cavities or recesses 11c and 21c of the silicon substrates 11a and 21a are formed by etching using the insulating films 11b and 21b as etching stoppers.

本願請求項1又は5に係る薄型複合素子では、サーミスタとバリスタとがそれぞれ薄膜であって、薄膜サーミスタと薄膜バリスタとが一対の櫛型電極を共通に利用するため、複合素子を薄型にすることができ、また薄膜サーミスタと薄膜バリスタが櫛型電極を共用しかつ並列接続されるため、この薄型複合素子はESDに強く、かつ高速熱応答性が高い。また薄膜サーミスタと薄膜バリスタとにより櫛型電極を挟む構造であるため両薄膜の電極との接合性が向上する。更に引出線を接続するためのパッド部を除いた基板上のすべての素子を保護膜で被覆するため、サーミスタが直接外部雰囲気に触れない。これにより複合素子が使用される雰囲気の湿度の影響を受けにくく、耐湿性に優れる。   In the thin composite element according to claim 1 or 5, the thermistor and the varistor are each a thin film, and the thin film thermistor and the thin film varistor commonly use a pair of comb-shaped electrodes. In addition, since the thin film thermistor and the thin film varistor share the comb-shaped electrode and are connected in parallel, the thin composite element is resistant to ESD and has high speed thermal response. Further, since the comb electrode is sandwiched between the thin film thermistor and the thin film varistor, the bonding property between the electrodes of both thin films is improved. Further, since all the elements on the substrate except for the pad portion for connecting the leader line are covered with the protective film, the thermistor does not directly touch the external atmosphere. Thereby, it is hard to be influenced by the humidity of the atmosphere in which the composite element is used, and is excellent in moisture resistance.

また本願請求項9又は13に係る薄型複合素子の製造方法によれば、上記特長のある薄型複合素子を製造できる。   According to the method for manufacturing a thin composite element according to claim 9 or 13 of the present application, it is possible to manufacture a thin composite element having the above features.

また本願請求項3又は7に係る薄型複合素子は薄膜バリスタ又は薄膜サーミスタの下方に絶縁膜を残してシリコン基板の空洞又は凹部が形成されるため、薄膜サーミスタがメンブレン構造になり、高速熱応答性が更に高くなる。   In addition, the thin composite element according to claim 3 or 7 of the present application forms a cavity or recess in the silicon substrate leaving an insulating film below the thin film varistor or thin film thermistor. Is even higher.

更に本願請求項11又は15に係る薄型複合素子の製造方法では、シリコン基板上の絶縁膜をエッチングストッパとして、エッチングによりシリコン基板に空洞又は凹部を容易に形成することができる。   Furthermore, in the method for manufacturing a thin composite element according to claim 11 or 15 of the present application, a cavity or a recess can be easily formed in the silicon substrate by etching using the insulating film on the silicon substrate as an etching stopper.

以下、本発明の最良の実施の形態について説明する。   The best mode of the present invention will be described below.

<第1の実施の形態>
図1に示すように、本発明の第1実施形態の薄型複合素子10は、絶縁基板11上に薄膜バリスタ12と一対の櫛型電極13,14と薄膜サーミスタ16と第1引出電極17と第2引出電極18と保護膜19を備える。絶縁基板11としては、シリコン基板11aとこの基板上面に形成された絶縁膜11bとを有するものが例示される。絶縁膜付きシリコン基板11は、後述する空洞又は凹部(図5及び図6参照)を絶縁膜の下にエッチングにより形成し易いため、好ましい。その他の絶縁基板としては、ガラス基板、セラミック基板等が挙げられる。基板は厚さ0.1〜0.5mmの範囲から決められる。絶縁膜付きシリコン基板は、シリコン基板を熱酸化することにより、またシリコン基板表面に化学気相成長法により、基板表面に厚さ100〜1000nmのSiO2膜を有するように形成される。
<First Embodiment>
As shown in FIG. 1, the thin composite element 10 according to the first embodiment of the present invention includes a thin film varistor 12, a pair of comb electrodes 13, 14, a thin film thermistor 16, a first extraction electrode 17, and a first electrode on an insulating substrate 11. Two extraction electrodes 18 and a protective film 19 are provided. Examples of the insulating substrate 11 include those having a silicon substrate 11a and an insulating film 11b formed on the upper surface of the substrate. The silicon substrate 11 with an insulating film is preferable because a cavity or a recess (see FIGS. 5 and 6) described later can be easily formed by etching under the insulating film. Examples of other insulating substrates include glass substrates and ceramic substrates. The substrate is determined from a thickness range of 0.1 to 0.5 mm. The silicon substrate with an insulating film is formed so as to have a SiO 2 film having a thickness of 100 to 1000 nm on the substrate surface by thermally oxidizing the silicon substrate and by chemical vapor deposition on the silicon substrate surface.

絶縁基板11上に形成される薄膜バリスタ12は、ZnOを主成分としてBi又はPrを含み、更にCo、Sb、Mn、Ni、Cr、Ti、Al等を添加した複合金属酸化物膜であって、ウルツ鉱型の結晶構造を有している。ZnOに対するBi、Pr、Co、Sb、Mn、Ni、Cr、Ti、Al等の添加含有量は所望のバリスタ特性に応じて決められる。薄膜バリスタ12は絶縁基板11の基板上面中心部にスパッタリング法により形成される。この薄膜バリスタ12の厚さは所望の特性に応じて100〜1000nmの範囲から決められる。この薄膜バリスタ12上には、薄膜バリスタより小面積で、Au、Pt等の導電層からなる相対向する一対の櫛型電極13,14が形成される。   A thin film varistor 12 formed on an insulating substrate 11 is a complex metal oxide film containing ZnO as a main component and containing Bi or Pr, and further adding Co, Sb, Mn, Ni, Cr, Ti, Al, or the like. It has a wurtzite crystal structure. The additive content of Bi, Pr, Co, Sb, Mn, Ni, Cr, Ti, Al, etc. with respect to ZnO is determined according to desired varistor characteristics. The thin film varistor 12 is formed by sputtering at the center of the upper surface of the insulating substrate 11. The thickness of the thin film varistor 12 is determined from a range of 100 to 1000 nm according to desired characteristics. On the thin film varistor 12, a pair of comb-shaped electrodes 13 and 14 which are smaller in area than the thin film varistor and are made of conductive layers such as Au and Pt are formed.

薄膜バリスタ12及び一対の櫛型電極13,14上には薄膜サーミスタ16が形成される。薄膜サーミスタ16は薄膜バリスタ12より小面積であって、一対の櫛型電極13,14を跨いでかつ一対の櫛型電極の各基部が露出するように薄膜バリスタ12及び電極13,14を被覆する。薄膜サーミスタは、Mn−Co系複合金属酸化物(MnxCo1-x)34、又はMn−Co系複合金属酸化物にNi、Fe、Cu及びAlからなる群より選ばれた少なくとも1種を含む複合金属酸化物(例えば、(MnxCoyNi1-x-y)34からなる複合金属酸化物である。この複合金属酸化物はスピネル型結晶構造を有し、膜厚方向に延在する柱状結晶構造を有している。Mn、Co、Ni、Fe、Cu、Al等の組成比はサーミスタの所望の特性に応じて決められる。この薄膜サーミスタ16の厚さは所望の特性に応じて100〜1000nmの範囲から決められる。 A thin film thermistor 16 is formed on the thin film varistor 12 and the pair of comb electrodes 13 and 14. The thin film thermistor 16 has a smaller area than the thin film varistor 12 and covers the thin film varistor 12 and the electrodes 13 and 14 so as to straddle the pair of comb electrodes 13 and 14 and to expose the bases of the pair of comb electrodes. . The thin film thermistor is at least one selected from the group consisting of Mn—Co based composite metal oxide (Mn x Co 1-x ) 3 O 4 or Mn—Co based composite metal oxide comprising Ni, Fe, Cu and Al. A composite metal oxide containing a seed (for example, a composite metal oxide made of (Mn x Co y Ni 1-xy ) 3 O 4. This composite metal oxide has a spinel crystal structure, and has a thickness direction. It has an extended columnar crystal structure, and the composition ratio of Mn, Co, Ni, Fe, Cu, Al, etc. is determined according to the desired characteristics of the thermistor. Depending on the range of 100 to 1000 nm.

薄膜サーミスタで被覆されていない櫛型電極13,14の各基部と薄膜バリスタ12の部分には第1及び第2引出電極17,18の各一端が電気的に接続される。これらの引出電極17,18の各他端は薄膜バリスタ12の形成されていない絶縁基板11上に形成される。第1及び第2引出電極17,18は、絶縁基板上に成膜されたCr、Ti等の接合層17a,18aと、この接合層上に接合層と同形同大に成膜されたAu、Pt等の導電層17b,18bとにより構成される。接合層は導電層の下地電極として導電層の櫛型電極等への接合度を高める機能を有する。更にこれらの第1及び第2引出電極17,18におけるリード線等の引出線(図示せず)を接続するためのパッド部17c,18cを除いた基板上のすべての素子、即ち薄膜バリスタ12,櫛型電極13,14,及び薄膜サーミスタ16は、二酸化ケイ素(SiO2)、窒化ケイ素(Si34)等の保護膜19により被覆される。これにより総厚0.1〜0.5mmのたて0.4〜1mm、よこ0.2〜0.5mmの薄型複合素子10が得られる。 One end of each of the first and second lead electrodes 17 and 18 is electrically connected to the bases of the comb electrodes 13 and 14 and the thin film varistor 12 which are not covered with the thin film thermistor. The other ends of the extraction electrodes 17 and 18 are formed on the insulating substrate 11 on which the thin film varistor 12 is not formed. The first and second lead electrodes 17 and 18 are formed of Cr, Ti, and other bonding layers 17a and 18a formed on an insulating substrate, and Au formed on the bonding layer in the same shape and size as the bonding layer. , Pt or the like and the conductive layers 17b and 18b. The bonding layer has a function of increasing the degree of bonding of the conductive layer to the comb electrode or the like as a base electrode of the conductive layer. Further, all elements on the substrate except the pad portions 17c and 18c for connecting lead wires (not shown) such as lead wires in the first and second lead electrodes 17 and 18, that is, the thin film varistor 12, The comb electrodes 13 and 14 and the thin film thermistor 16 are covered with a protective film 19 such as silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ). As a result, a thin composite element 10 having a total thickness of 0.1 to 0.5 mm and a length of 0.4 to 1 mm and a width of 0.2 to 0.5 mm is obtained.

<第2の実施の形態>
図4に示すように、本発明の第2実施形態の薄型複合素子20は、絶縁基板21上に薄膜サーミスタ22と一対の櫛型電極23,24と薄膜バリスタ26と第3引出電極27と第4引出電極28と保護膜29を備える。絶縁基板21としては、シリコン基板21aとこの基板上面に形成された絶縁膜21bとを有するものが例示される。絶縁膜付きシリコン基板21は、後述する空洞又は凹部(図5及び図6参照)を絶縁膜の下にエッチングにより形成し易いため、好ましい。絶縁基板の厚さ、種類及び絶縁膜付きシリコン基板の製造方法は第1の実施形態と同じである。
<Second Embodiment>
As shown in FIG. 4, the thin composite element 20 of the second embodiment of the present invention includes a thin film thermistor 22, a pair of comb-shaped electrodes 23 and 24, a thin film varistor 26, a third extraction electrode 27, and a first electrode on an insulating substrate 21. Four extraction electrodes 28 and a protective film 29 are provided. Examples of the insulating substrate 21 include those having a silicon substrate 21a and an insulating film 21b formed on the upper surface of the substrate. The silicon substrate 21 with an insulating film is preferable because a cavity or a recess (see FIGS. 5 and 6) described later can be easily formed by etching under the insulating film. The thickness and type of the insulating substrate and the method for manufacturing the silicon substrate with the insulating film are the same as those in the first embodiment.

絶縁基板21上に形成される薄膜サーミスタ22の組成は、第1の実施形態の薄膜サーミスタ16の組成と同じであり、薄膜サーミスタ22の形状、大きさ、配置は、第1の実施形態の薄膜バリスタ12の形状、大きさ、配置と同じである。同様に一対の櫛型電極23,24の組成、形状、大きさ、配置は一対の櫛型電極13,14の組成、形状、大きさ、配置と同じである。薄膜バリスタ26の組成は、第1の実施形態の薄膜バリスタ12の組成と同じであり、薄膜バリスタ26の形状、大きさ、配置は、第1の実施形態の薄膜サーミスタ16の形状、大きさ、配置と同じである。第3及び第4引出電極27,28の組成、形状、大きさ、配置は、第1の実施形態の第1及び第2引出電極17,18の形状、大きさ、配置と同じである。更に保護膜29の組成、形状、大きさ、配置は、第1の実施形態の保護膜19の形状、大きさ、配置と同じである。これにより総厚0.1〜0.5mmのたて0.4〜1mm、よこ0.2〜0.5mmの薄型複合素子20が得られる。   The composition of the thin film thermistor 22 formed on the insulating substrate 21 is the same as the composition of the thin film thermistor 16 of the first embodiment, and the shape, size, and arrangement of the thin film thermistor 22 are the same as those of the thin film of the first embodiment. The shape, size, and arrangement of the varistor 12 are the same. Similarly, the composition, shape, size and arrangement of the pair of comb electrodes 23 and 24 are the same as the composition, shape, size and arrangement of the pair of comb electrodes 13 and 14. The composition of the thin film varistor 26 is the same as that of the thin film varistor 12 of the first embodiment, and the shape, size, and arrangement of the thin film varistor 26 are the same as those of the thin film thermistor 16 of the first embodiment. Same as placement. The composition, shape, size, and arrangement of the third and fourth extraction electrodes 27, 28 are the same as the shape, size, and arrangement of the first and second extraction electrodes 17, 18 of the first embodiment. Furthermore, the composition, shape, size, and arrangement of the protective film 29 are the same as the shape, size, and arrangement of the protective film 19 of the first embodiment. As a result, a thin composite element 20 having a total thickness of 0.1 to 0.5 mm and a length of 0.4 to 1 mm and a width of 0.2 to 0.5 mm is obtained.

<第3の実施の形態>
図5に示すように、本発明の第3実施形態の薄型複合素子10は、第1の実施形態の薄型複合素子10の薄膜バリスタ12の下方に絶縁膜11bを残してシリコン基板11aの凹部11cが形成される。図示しないが、凹部11cの代わりに空洞でもよい。
<Third Embodiment>
As shown in FIG. 5, the thin composite element 10 of the third embodiment of the present invention has a recess 11c in the silicon substrate 11a, leaving an insulating film 11b below the thin film varistor 12 of the thin composite element 10 of the first embodiment. Is formed. Although not shown, a cavity may be used instead of the recess 11c.

<第4の実施の形態>
図6に示すように、本発明の第4実施形態の薄型複合素子20は、第2の実施形態の薄型複合素子20の薄膜サーミスタ22の下方に絶縁膜21bを残してシリコン基板21aの凹部21cが形成される。図示しないが、凹部21cの代わりに空洞でもよい。
<Fourth embodiment>
As shown in FIG. 6, the thin composite element 20 of the fourth embodiment of the present invention has a recess 21c of the silicon substrate 21a, leaving an insulating film 21b below the thin film thermistor 22 of the thin composite element 20 of the second embodiment. Is formed. Although not shown, a cavity may be used instead of the recess 21c.

次に本発明の実施例を説明する。   Next, examples of the present invention will be described.

<実施例1>
図1及び図2に示される薄型複合素子の製造方法を説明する。先ず図3(a)に示すように、熱酸化法により、厚さ0.25mmのシリコン基板11aに層厚500nmのSiO2層11bを形成する。このSiO2層11bの上面全体にZnO:98.6mol%、Bi23:0.2mol%、Sb25:0.1mol%、CoO:0.5mol%、MnO2:0.2mol%、Cr23:0.2mol%、NiO:0.2mol%を含む薄膜を膜厚が500nmとなるようにスパッタリング法によって形成する。この薄膜の全面に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、リフトオフ法により薄膜を所望の形状にパターニングする。この基板を900℃で2時間熱処理することにより、図3(b)に示すように、バリスタ電圧が安定した信頼性の高い薄膜バリスタ12を得る。
<Example 1>
A method for manufacturing the thin composite element shown in FIGS. 1 and 2 will be described. First, as shown in FIG. 3A, an SiO 2 layer 11b having a layer thickness of 500 nm is formed on a silicon substrate 11a having a thickness of 0.25 mm by a thermal oxidation method. ZnO on the entire upper surface of the SiO 2 layer 11b: 98.6mol%, Bi 2 O 3: 0.2mol%, Sb 2 O 5: 0.1mol%, CoO: 0.5mol%, MnO 2: 0.2mol% A thin film containing Cr 2 O 3 : 0.2 mol% and NiO: 0.2 mol% is formed by a sputtering method so as to have a film thickness of 500 nm. A photosensitive resin is formed on the entire surface of the thin film, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, the thin film is patterned into a desired shape by a lift-off method. By heat-treating this substrate at 900 ° C. for 2 hours, as shown in FIG. 3B, a highly reliable thin film varistor 12 having a stable varistor voltage is obtained.

次いで薄膜バリスタ12及びSiO2層11bの全面に電極を形成するためのAu薄膜を、膜厚が200nmとなるようにスパッタリング法によって形成する。Au薄膜の全面に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、ヨウ素ヨウ化カリウム溶液を用いたウエットエッチングによりAu薄膜をパターニングし、図3(c)に示すように、導電膜からなる所望の一対の櫛型電極13,14を得る。 Next, an Au thin film for forming electrodes on the entire surface of the thin film varistor 12 and the SiO 2 layer 11b is formed by sputtering so that the film thickness becomes 200 nm. A photosensitive resin is formed on the entire surface of the Au thin film, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, the Au thin film is patterned by wet etching using a potassium iodide iodide solution. As shown in FIG. 3C, a desired pair of comb-shaped electrodes 13 and 14 made of a conductive film are formed. obtain.

次に櫛型電極の形成された基板上面全体に(Mn0.4Co0.6)34のスピネル構造の薄膜を膜厚が500nmとなるようにスパッタリング法によって形成する。この薄膜の全面に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、希塩酸溶液を用いたウエットエッチングによりこの薄膜を所望の形状にパターニングする。この基板を600℃で1時間熱処理し、図3(d)に示すように、抵抗値及びB定数の信頼性の高い薄膜サーミスタ16を得る。 Next, a thin film having a spinel structure of (Mn 0.4 Co 0.6 ) 3 O 4 is formed on the entire upper surface of the substrate on which the comb-shaped electrode is formed by sputtering. A photosensitive resin is formed on the entire surface of the thin film, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, the thin film is patterned into a desired shape by wet etching using a diluted hydrochloric acid solution. The substrate is heat-treated at 600 ° C. for 1 hour to obtain a thin film thermistor 16 having a high resistance value and high B constant reliability, as shown in FIG.

次に薄膜サーミスタ16及びSiO2層11bの全面に接合層となる下地電極を形成するためのCr薄膜を膜厚が100nmとなるようにスパッタリング法によって形成する。続けてこのCr薄膜全面に導電層となるAu薄膜を膜厚が200nmとなるようにスパッタリング法により形成する。Au薄膜の全面に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、ヨウ素ヨウ化カリウム溶液を用いたウエットエッチングによりAu薄膜をパターニングし、所望の形状の導電層を得る。続けて、硝酸セリウムアンモニウム溶液を用いたウエットエッチングにより、下地電極となるCr薄膜をAu薄膜と同構造にパターニングし、薄膜バリスタ上にて、図3(e)に示すように、一対の櫛型電極13,14の基部と電気的に接続した引出電極17,18を得る。 Next, a Cr thin film for forming a base electrode serving as a bonding layer is formed on the entire surface of the thin film thermistor 16 and the SiO 2 layer 11b by sputtering so that the film thickness becomes 100 nm. Subsequently, an Au thin film serving as a conductive layer is formed on the entire surface of the Cr thin film by a sputtering method so as to have a film thickness of 200 nm. A photosensitive resin is formed on the entire surface of the Au thin film, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, the Au thin film is patterned by wet etching using a potassium iodide iodide solution to obtain a conductive layer having a desired shape. Subsequently, by wet etching using a cerium ammonium nitrate solution, a Cr thin film serving as a base electrode is patterned into the same structure as the Au thin film, and a pair of comb-shaped elements is formed on the thin film varistor as shown in FIG. Lead electrodes 17 and 18 electrically connected to the bases of the electrodes 13 and 14 are obtained.

更に基板全面にSiO2薄膜を膜厚が600nmとなるようにスパッタリング法により形成する。SiO2薄膜の全面に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、フッ酸を用いたウエットエッチングによりSiO2薄膜をパターニングし、図3(f)に示すように、リード線等の引出し線を接続するパッド部17c,18cのみを露出させる。これにより総厚0.25mmのたて1.0mm、よこ0.5mmの薄型複合素子10が得られる。 Further, a SiO 2 thin film is formed on the entire surface of the substrate by sputtering so that the film thickness becomes 600 nm. A photosensitive resin is formed on the entire surface of the SiO 2 thin film, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, the SiO 2 thin film is patterned by wet etching using hydrofluoric acid, and as shown in FIG. 3 (f), only the pad portions 17c and 18c for connecting lead wires such as lead wires are exposed. Let As a result, a thin composite element 10 having a total thickness of 0.25 mm and a length of 1.0 mm and a width of 0.5 mm is obtained.

以上、単一の複合素子の製造方法について述べたが、複合素子を量産するときには、1枚のシリコン基板上に多数のバリスタ機能付き薄膜サーミスタを形成し、その基板を切断により個々のバリスタ機能付き薄膜サーミスタの薄型複合素子を得る。   The manufacturing method of a single composite element has been described above. When a composite element is mass-produced, a number of thin film thermistors with varistor functions are formed on a single silicon substrate, and the substrate is cut to have individual varistor functions. A thin composite element of a thin film thermistor is obtained.

<実施例2>
図5に示される薄型複合素子の製造方法を説明する。図3(f)に示される複合素子を裏返した後、図7(a)に示すように基板中心部にSiO2層11dを取り除いた四角形の窓31を形成する。このシリコン基板11aには上面にSiO2層11bが下面にSiO2層11dが形成されている。この窓31は、窓となる部分以外のSiO2層11dを感光性樹脂でマスクし、フッ酸を用いたウエットエッチングによりSiO2層11dをパターニングすることにより、形成される。続いて、上記感光性樹脂をマスクとし、水酸化テトラメチルアンモニア水溶液(TMAH)を用いたウエットエッチングにより薄膜バリスタの下部(図7では上部)に相当するシリコン基板11aの一部をエッチングし、図7(b)に示すようにメンブレン構造にしたバリスタ機能付き薄膜サーミスタの薄型複合素子を得る。
<Example 2>
A method of manufacturing the thin composite element shown in FIG. 5 will be described. After turning over the composite element shown in FIG. 3F, a rectangular window 31 is formed by removing the SiO 2 layer 11d at the center of the substrate as shown in FIG. 7A. The silicon substrate 11a has an SiO 2 layer 11b formed on the upper surface and an SiO 2 layer 11d formed on the lower surface. The window 31 is formed by masking the SiO 2 layer 11d other than the window portion with a photosensitive resin and patterning the SiO 2 layer 11d by wet etching using hydrofluoric acid. Subsequently, using the photosensitive resin as a mask, a part of the silicon substrate 11a corresponding to the lower part (upper part in FIG. 7) of the thin film varistor is etched by wet etching using a tetramethylammonium hydroxide aqueous solution (TMAH). A thin composite element of a thin film thermistor with a varistor function having a membrane structure as shown in 7 (b) is obtained.

本発明第1実施形態の薄型複合素子の図3(f)のA−A線断面図である。It is the sectional view on the AA line of FIG.3 (f) of the thin composite element of 1st Embodiment of this invention. 本発明第1実施形態の薄型複合素子の分解斜視図である。It is a disassembled perspective view of the thin composite element of 1st Embodiment of this invention. 本発明第1実施形態の薄型複合素子の製造工程を示す斜視図である。It is a perspective view which shows the manufacturing process of the thin composite element of 1st Embodiment of this invention. 本発明第2実施形態の図1に対応する薄型複合素子の断面図である。It is sectional drawing of the thin composite element corresponding to FIG. 1 of 2nd Embodiment of this invention. 本発明第3実施形態の図1に対応する薄型複合素子の断面図である。It is sectional drawing of the thin composite element corresponding to FIG. 1 of 3rd Embodiment of this invention. 本発明第4実施形態の図1に対応する薄型複合素子の断面図である。It is sectional drawing of the thin composite element corresponding to FIG. 1 of 4th Embodiment of this invention. 本発明第3実施形態の薄型複合素子の製造工程を示す斜視図である。It is a perspective view which shows the manufacturing process of the thin composite element of 3rd Embodiment of this invention.

符号の説明Explanation of symbols

10: 薄型複合素子
11: 絶縁基板
12: 薄膜バリスタ
13,14: 一対の櫛型電極
16: 薄膜サーミスタ
17: 第1引出電極
17a: 接合層
17b: 導電層
17c: パッド部
18: 第2引出電極
18a: 接合層
18b: 導電層
18c: パッド部
19: 保護膜
20: 薄型複合素子
21: 絶縁基板
22: 薄膜サーミスタ
23,24: 一対の櫛型電極
26: 薄膜バリスタ
27: 第3引出電極
27a: 接合層
27b: 導電層
27c: パッド部
28: 第4引出電極
28a: 接合層
28b: 導電層
28c: パッド部
29: 保護膜
10: Thin composite element 11: Insulating substrate 12: Thin film varistor 13, 14: Pair of comb electrodes 16: Thin film thermistor 17: First extraction electrode 17a: Bonding layer 17b: Conductive layer 17c: Pad part 18: Second extraction electrode 18a: bonding layer 18b: conductive layer 18c: pad portion 19: protective film 20: thin composite element 21: insulating substrate 22: thin film thermistor 23, 24: pair of comb electrodes 26: thin film varistor 27: third extraction electrode 27a: Bonding layer 27b: Conductive layer 27c: Pad portion 28: Fourth extraction electrode 28a: Bonding layer 28b: Conductive layer 28c: Pad portion 29: Protective film

Claims (16)

絶縁基板上に形成された薄膜バリスタと、
前記薄膜バリスタ上に形成された導電層からなる相対向する一対の櫛型電極と、
前記一対の櫛型電極を跨いでかつ一対の櫛型電極の各基部が露出するように前記薄膜バリスタ及び前記電極を被覆する薄膜サーミスタと、
前記一対の櫛型電極の一方の露出した基部と電気的に接続するように前記薄膜バリスタの形成されていない前記絶縁基板上に形成された第1引出電極と、
前記一対の櫛型電極の他方の露出した基部と電気的に接続するように前記薄膜バリスタの形成されていない前記絶縁基板上に形成された第2引出電極と、
前記第1及び第2引出電極における引出線を接続するためのパッド部を除いた前記基板上のすべての素子を被覆する保護膜と
を備えた薄型複合素子。
A thin film varistor formed on an insulating substrate;
A pair of opposing comb electrodes made of a conductive layer formed on the thin film varistor;
A thin film thermistor that covers the thin film varistor and the electrode so that the bases of the pair of comb electrodes are exposed across the pair of comb electrodes;
A first extraction electrode formed on the insulating substrate on which the thin film varistor is not formed so as to be electrically connected to one exposed base of the pair of comb electrodes;
A second extraction electrode formed on the insulating substrate on which the thin film varistor is not formed so as to be electrically connected to the other exposed base of the pair of comb electrodes;
A thin composite element comprising: a protective film covering all elements on the substrate excluding a pad portion for connecting a lead line in the first and second lead electrodes.
絶縁基板が、セラミック基板、ガラス基板又は基板上面に絶縁膜を有するシリコン基板である請求項1記載の薄型複合素子。   2. The thin composite element according to claim 1, wherein the insulating substrate is a ceramic substrate, a glass substrate, or a silicon substrate having an insulating film on the upper surface of the substrate. 絶縁基板が基板上面に絶縁膜を有するシリコン基板であって、薄膜バリスタの下方に前記絶縁膜を残して前記シリコン基板の空洞又は凹部が形成された請求項1又は2記載の薄型複合素子。   3. The thin composite element according to claim 1, wherein the insulating substrate is a silicon substrate having an insulating film on the upper surface of the substrate, and the cavity or recess of the silicon substrate is formed leaving the insulating film below the thin film varistor. 第1及び第2引出電極が、絶縁基板上に成膜された接合層と前記接合層上に前記接合層と同形同大に成膜された導電層とにより構成された請求項1ないし3いずれか1項に記載の薄型複合素子。   The first and second lead electrodes are constituted by a bonding layer formed on an insulating substrate and a conductive layer formed on the bonding layer in the same shape and size as the bonding layer. The thin composite element according to any one of the above. 絶縁基板上に形成された薄膜サーミスタと、
前記薄膜サーミスタ上に形成された導電層からなる相対向する一対の櫛型電極と、
前記一対の櫛型電極を跨いでかつ一対の櫛型電極の各基部が露出するように前記薄膜サーミスタ及び前記電極を被覆する薄膜バリスタと、
前記一対の櫛型電極の一方の露出した基部と電気的に接続するように前記薄膜サーミスタの形成されていない前記絶縁基板上に形成された第3引出電極と、
前記一対の櫛型電極の他方の露出した基部と電気的に接続するように前記薄膜サーミスタの形成されていない前記絶縁基板上に形成された第4引出電極と、
前記第3及び第4引出電極における引出線を接続するためのパッド部を除いた前記基板上のすべての素子を被覆する保護膜と
を備えた薄型複合素子。
A thin film thermistor formed on an insulating substrate;
A pair of opposing comb electrodes made of a conductive layer formed on the thin film thermistor;
A thin film varistor that covers the thin film thermistor and the electrode so as to straddle the pair of comb electrodes and expose each base of the pair of comb electrodes;
A third extraction electrode formed on the insulating substrate on which the thin film thermistor is not formed so as to be electrically connected to one exposed base of the pair of comb electrodes;
A fourth extraction electrode formed on the insulating substrate on which the thin film thermistor is not formed so as to be electrically connected to the other exposed base of the pair of comb electrodes;
A thin composite element comprising: a protective film covering all elements on the substrate except for a pad portion for connecting a lead line in the third and fourth lead electrodes.
絶縁基板が、セラミック基板、ガラス基板又は基板上面に絶縁膜を有するシリコン基板である請求項5記載の薄型複合素子。   6. The thin composite element according to claim 5, wherein the insulating substrate is a ceramic substrate, a glass substrate, or a silicon substrate having an insulating film on the upper surface of the substrate. 絶縁基板が基板上面に絶縁膜を有するシリコン基板であって、薄膜サーミスタの下方に前記絶縁膜を残して前記シリコン基板の空洞又は凹部が形成された請求項5又は6記載の薄型複合素子。   The thin composite element according to claim 5 or 6, wherein the insulating substrate is a silicon substrate having an insulating film on the upper surface of the substrate, and the cavity or recess of the silicon substrate is formed leaving the insulating film below the thin film thermistor. 第3及び第4引出電極が、絶縁基板上に成膜された接合層と前記接合層上に前記接合層と同形同大に成膜された導電層とにより構成された請求項5ないし7いずれか1項に記載の薄型複合素子。   The third and fourth extraction electrodes are constituted by a bonding layer formed on an insulating substrate and a conductive layer formed on the bonding layer in the same shape and size as the bonding layer. The thin composite element according to any one of the above. 絶縁基板上に所定のパターンで薄膜バリスタを形成する工程と、
前記薄膜バリスタ上に導電層からなる相対向する一対の櫛型電極を形成する工程と、
前記一対の櫛型電極を跨いでかつ一対の櫛型電極の各基部が露出するように前記薄膜バリスタ及び前記電極を薄膜サーミスタで被覆する工程と、
前記一対の櫛型電極の一方の露出した基部と電気的に接続するように前記薄膜バリスタの形成されていない前記絶縁基板上に第1引出電極を形成する工程と、
前記一対の櫛型電極の他方の露出した基部と電気的に接続するように前記薄膜バリスタの形成されていない前記絶縁基板上に第2引出電極を形成する工程と、
前記第1及び第2引出電極における引出線を接続するためのパッド部を除いた前記基板上のすべての素子を保護膜により被覆する工程と
を含む薄型複合素子の製造方法。
Forming a thin film varistor with a predetermined pattern on an insulating substrate;
Forming a pair of opposing comb electrodes made of a conductive layer on the thin film varistor;
Covering the thin film varistor and the electrode with a thin film thermistor so as to straddle the pair of comb electrodes and expose each base of the pair of comb electrodes;
Forming a first extraction electrode on the insulating substrate on which the thin film varistor is not formed so as to be electrically connected to one exposed base of the pair of comb electrodes;
Forming a second extraction electrode on the insulating substrate on which the thin film varistor is not formed so as to be electrically connected to the other exposed base of the pair of comb electrodes;
A method of manufacturing a thin composite element, comprising: covering all elements on the substrate except for a pad portion for connecting lead lines in the first and second lead electrodes with a protective film.
絶縁基板が、セラミック基板、ガラス基板又は基板上面に絶縁膜を有するシリコン基板である請求項9記載の薄型複合素子の製造方法。   The method for manufacturing a thin composite element according to claim 9, wherein the insulating substrate is a ceramic substrate, a glass substrate, or a silicon substrate having an insulating film on an upper surface of the substrate. 絶縁基板が基板上面に絶縁膜を有するシリコン基板であって、薄膜バリスタの下方に前記絶縁膜をエッチングストッパとしてエッチングにより前記シリコン基板の空洞又は凹部を形成する請求項9又は10記載の薄型複合素子の製造方法。   The thin composite element according to claim 9 or 10, wherein the insulating substrate is a silicon substrate having an insulating film on an upper surface of the substrate, and a cavity or a recess of the silicon substrate is formed by etching using the insulating film as an etching stopper below the thin film varistor. Manufacturing method. 第1及び第2引出電極が、絶縁基板上に接合層を成膜した後、前記接合層上に前記接合層と同形同大に導電層を成膜することにより構成される請求項9ないし11いずれか1項に記載の薄型複合素子の製造方法。   The first and second extraction electrodes are formed by forming a bonding layer on an insulating substrate and then forming a conductive layer on the bonding layer in the same shape and size as the bonding layer. 11. A method for manufacturing a thin composite element according to any one of 11 above. 絶縁基板上に所定のパターンで薄膜サーミスタを形成する工程と、
前記薄膜サーミスタ上に導電層からなる相対向する一対の櫛型電極を形成する工程と、
前記一対の櫛型電極を跨いでかつ一対の櫛型電極の各基部が露出するように前記薄膜サーミスタ及び前記電極を薄膜バリスタで被覆する工程と、
前記一対の櫛型電極の一方の露出した基部と電気的に接続するように前記薄膜サーミスタの形成されていない前記絶縁基板上に第3引出電極を形成する工程と、
前記一対の櫛型電極の他方の露出した基部と電気的に接続するように前記薄膜サーミスタの形成されていない前記絶縁基板上に第4引出電極を形成する工程と、
前記第3及び第4引出電極における引出線を接続するためのパッド部を除いた前記基板上のすべての素子を保護膜により被覆する工程と
を含む薄型複合素子の製造方法。
Forming a thin film thermistor in a predetermined pattern on an insulating substrate;
Forming a pair of opposing comb electrodes made of a conductive layer on the thin film thermistor;
Covering the thin film thermistor and the electrode with a thin film varistor so as to straddle the pair of comb electrodes and expose each base of the pair of comb electrodes;
Forming a third extraction electrode on the insulating substrate on which the thin film thermistor is not formed so as to be electrically connected to one exposed base of the pair of comb electrodes;
Forming a fourth extraction electrode on the insulating substrate on which the thin film thermistor is not formed so as to be electrically connected to the other exposed base of the pair of comb electrodes;
A method of manufacturing a thin composite element including a step of covering all elements on the substrate except a pad portion for connecting lead lines in the third and fourth lead electrodes with a protective film.
絶縁基板が、セラミック基板、ガラス基板又は基板上面に絶縁膜を有するシリコン基板である請求項13記載の薄型複合素子の製造方法。   The method for producing a thin composite element according to claim 13, wherein the insulating substrate is a ceramic substrate, a glass substrate, or a silicon substrate having an insulating film on an upper surface of the substrate. 絶縁基板が基板上面に絶縁膜を有するシリコン基板であって、薄膜サーミスタの下方に前記絶縁膜をエッチングストッパとしてエッチングにより前記シリコン基板の空洞又は凹部を形成する請求項13又は14記載の薄型複合素子の製造方法。   15. The thin composite element according to claim 13, wherein the insulating substrate is a silicon substrate having an insulating film on the upper surface of the substrate, and a cavity or a recess of the silicon substrate is formed by etching using the insulating film as an etching stopper below the thin film thermistor. Manufacturing method. 第3及び第4引出電極が、絶縁基板上に接合層を成膜した後、前記接合層上に前記接合層と同形同大に導電層を成膜することにより構成される請求項13ないし15いずれか1項に記載の薄型複合素子の製造方法。   The third and fourth extraction electrodes are formed by forming a bonding layer on the insulating substrate and then forming a conductive layer on the bonding layer in the same shape and size as the bonding layer. 15. A method for producing a thin composite element according to any one of 15 items.
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