JP2008270447A - Thin composite element and method of manufacturing the same - Google Patents

Thin composite element and method of manufacturing the same Download PDF

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JP2008270447A
JP2008270447A JP2007110086A JP2007110086A JP2008270447A JP 2008270447 A JP2008270447 A JP 2008270447A JP 2007110086 A JP2007110086 A JP 2007110086A JP 2007110086 A JP2007110086 A JP 2007110086A JP 2008270447 A JP2008270447 A JP 2008270447A
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substrate
thin film
electrode
thin
lower electrode
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Kensho Nagatomo
憲昭 長友
Hitoshi Inaba
均 稲場
Yoshinori Adachi
美紀 足立
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Mitsubishi Materials Corp
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Mitsubishi Materials Corp
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<P>PROBLEM TO BE SOLVED: To obtain a small and thin composite element having high speed thermal response by forming each of a thermistor, a resistor and a capacitor with a thin film and forming them in one chip. <P>SOLUTION: In the thin composite element 10, a thin film thermistor 12, a thin film resistor 16, and a thin film capacitor 21 are spaced apart from each other and formed on an insulating substrate 11. A pair of opposed comb-type electrodes 13 and 14 are formed on the thin film thermistor, and the thin film capacitor has a lower electrode 17, a dielectric layer 18 and an upper electrode 19. One comb-type electrode 14, one end of the thin film resistor 16 and one end of the upper electrode 19 are mutually electrically connected by a connecting layer 22 on the substrate. A first led out electrode 23 electrically connected to the other comb-type electrode 13, and a second led out electrode 24 electrically connected to the other end of the thin resistor are formed on the substrate, respectively. All elements on the substrate except pads 17c, 23c, 24c for connecting the leads at the lower electrode, the first and the second led out electrodes are covered with a protective film 26. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、薄膜サーミスタと薄膜抵抗体と薄膜コンデンサを有する薄型複合素子及びその製造方法に関するものである。   The present invention relates to a thin composite element having a thin film thermistor, a thin film resistor, and a thin film capacitor, and a method for manufacturing the same.

従来、サーミスタと抵抗とコンデンサを含む回路として、発振形測温回路が開示されている(例えば、特許文献1参照。)。この発振形測温回路では、直流電源に抵抗とコンデンサを直列接続し、これら抵抗とコンデンサの時定数に対応した周期でこのコンデンサを充放電させる弛緩発振回路を構成し、かつ上記抵抗として測温用のサーミスタと基準抵抗とを交互に切換接続するスイッチング手段を設け、上記サーミスタ接続時の発振周波数と上記基準抵抗接続時の発振周波数とを比較することにより上記サーミスタの温度を求めている。この発振形測温回路では、サーミスタの両端接続点と直流電源の両端ラインとの間にそれぞれサージ吸収用のツエナーダイオードを逆方向に接続したことを特徴とする。この発明の発振形測温回路によれば、サーミスタの両端いずれのリード線に正負いずれのサージ電圧が誘起されても、ツエナーダイオードを通じて直流電源側にサージ電圧が吸収され、内部回路に直接的に伝わらないので、従来のような誤動作や素子破壊が生じなくなり、回路の信頼性が大いに向上する。しかし、このような発振形測温回路では、サーミスタ、抵抗、コンデンサ等の個々の電子部品を複数個用いて回路が構成され、これらの部品を同一基板上に実装するときには、必然的に実装面積が増大し、回路の小型化を進める上で大きな制約となっていた。   Conventionally, an oscillation type temperature measuring circuit has been disclosed as a circuit including a thermistor, a resistor, and a capacitor (for example, see Patent Document 1). In this oscillation type temperature measuring circuit, a resistor and a capacitor are connected in series to a DC power source, and a relaxation oscillation circuit that charges and discharges this capacitor in a cycle corresponding to the time constant of these resistors and the capacitor is formed, and the temperature is measured as the resistor. Switching means for alternately switching and connecting the thermistor and the reference resistor is provided, and the temperature of the thermistor is obtained by comparing the oscillation frequency when the thermistor is connected with the oscillation frequency when the reference resistor is connected. In this oscillation type temperature measuring circuit, a surge absorbing Zener diode is connected in the opposite direction between the both-end connection point of the thermistor and the both-end line of the DC power supply. According to the oscillating temperature measuring circuit of the present invention, even if a positive or negative surge voltage is induced at any of the lead wires at both ends of the thermistor, the surge voltage is absorbed to the DC power source side through the Zener diode and directly into the internal circuit. Since it is not transmitted, the conventional malfunction and element destruction do not occur, and the reliability of the circuit is greatly improved. However, in such an oscillation type temperature measuring circuit, a circuit is configured by using a plurality of individual electronic components such as a thermistor, a resistor, and a capacitor. When these components are mounted on the same substrate, the mounting area is inevitably required. As a result, the size of the circuit has been greatly reduced.

この点を改良した構造的に特徴のある素子として、サーミスタと抵抗を直列に接続し、これらのサーミスタと抵抗に対してコンデンサを並列接続した回路と等価な特性を1チップで実現した複合素子が開示されている(例えば、特許文献2参照。)。この複合素子を利用すれば、サーミスタ、抵抗及びコンデンサより構成している温度補償回路等、電子回路の小型化が可能となる。特に、小型化ニーズの強い温度補償型水晶発振器等の温度補償用回路として有用な複合素子を実現できる。
特開昭61−68526(特許請求の範囲、作用、発明の効果) 特開平11−307318([0004]、[0006])
As an element having a structural feature improved in this respect, there is a composite element in which a thermistor and a resistor are connected in series, and a characteristic equivalent to a circuit in which a capacitor is connected in parallel to these thermistor and the resistor is realized on a single chip. (For example, refer to Patent Document 2). By using this composite element, it is possible to reduce the size of electronic circuits such as a temperature compensation circuit composed of a thermistor, a resistor and a capacitor. In particular, it is possible to realize a composite element useful as a temperature compensation circuit such as a temperature compensation crystal oscillator having a strong need for miniaturization.
JP 61-68526 (Claims, functions, effects of the invention) JP-A-11-307318 ([0004], [0006])

特許文献2に示される複合素子は単一のチップにサーミスタ、抵抗及びコンデンサを構成できるため、回路の小型化が図れる特長があるけれども、この複合素子では、サーミスタ素体の一方の面上に抵抗体層を設け、その他方の面上に誘電体層を設けるバルク構造によって、抵抗体とコンデンサとサーミスタの3つの部品を複合しているため、サーミスタの熱容量が大きく、熱応答性が低い欠点があった。   The composite element disclosed in Patent Document 2 has a feature that a thermistor, a resistor, and a capacitor can be configured on a single chip, so that the circuit can be miniaturized. However, in this composite element, a resistor is provided on one surface of the thermistor body. The bulk structure in which the body layer is provided and the dielectric layer is provided on the other surface combines the three parts of the resistor, the capacitor, and the thermistor, so the thermistor has a large heat capacity and low thermal response. there were.

本発明の目的は、サーミスタ、抵抗及びコンデンサをそれぞれ薄膜で構成して1チップ化することにより、薄くて小型の高速熱応答性のある薄型複合素子及びその製造方法を提供することにある。   It is an object of the present invention to provide a thin composite element having a thin and small high-speed thermal response and a method for manufacturing the same by forming a thermistor, a resistor and a capacitor from thin films into one chip.

本願請求項1に係る発明は、図1及び図2に示すように、絶縁基板11上に薄膜サーミスタ12と薄膜抵抗16と薄膜コンデンサ21とが互いに離間して形成され、薄膜サーミスタ12上に相対向する一対の櫛型電極13,14が形成され、薄膜コンデンサ21が基板11上に形成された下部電極17とこの下部電極上に形成された誘電体層18とこの誘電体層上に形成された上部電極19とにより構成され、基板11上に一対の櫛型電極の一方14と薄膜抵抗16の一端と上部電極19又は下部電極の一端とを互いに電気的に接続するように接続層22が形成され、基板11上に一対の櫛型電極の他方13に電気的に接続するように第1引出電極23が形成され、基板11上に薄膜抵抗16の他端に電気的に接続するように第2引出電極24が形成され、下部電極17又は上部電極、第1引出電極23及び第2引出電極24における引出線を接続するためのパッド部17c,23c,24cを除いた基板上のすべての素子12,13,14,16,18,19,22を被覆するように保護膜26が形成されたことを特徴とする薄型複合素子10である。   In the invention according to claim 1 of the present application, as shown in FIGS. 1 and 2, a thin film thermistor 12, a thin film resistor 16, and a thin film capacitor 21 are formed on an insulating substrate 11 so as to be separated from each other. A pair of facing comb electrodes 13 and 14 is formed, and a thin film capacitor 21 is formed on the lower electrode 17 formed on the substrate 11, the dielectric layer 18 formed on the lower electrode, and the dielectric layer. The connection layer 22 is formed on the substrate 11 so as to electrically connect one of the pair of comb electrodes 14, one end of the thin film resistor 16, and one end of the upper electrode 19 or the lower electrode on the substrate 11. A first extraction electrode 23 is formed on the substrate 11 so as to be electrically connected to the other 13 of the pair of comb electrodes, and is electrically connected to the other end of the thin film resistor 16 on the substrate 11. Second extraction electrode 2 Are formed, and all elements 12, 13, 13 on the substrate excluding the pad portions 17 c, 23 c, 24 c for connecting the lead lines in the lower electrode 17 or the upper electrode, the first lead electrode 23 and the second lead electrode 24, The thin composite element 10 is characterized in that a protective film 26 is formed so as to cover 14, 16, 18, 19, and 22.

本願請求項5に係る発明は、図7及び図8に示すように、絶縁基板31上に薄膜サーミスタ32と薄膜抵抗36と薄膜コンデンサ用下部電極41とが互いに離間して形成され、薄膜サーミスタ32上に相対向する一対の櫛型電極33,34が形成され、基板31上に一対の櫛型電極の一方34と薄膜抵抗36の一端と下部電極41の一端とを互いに電気的に接続するように接続層37が形成され、基板31上に一対の櫛型電極の他方33に電気的に接続するように第3引出電極38が形成され、基板31上に薄膜抵抗36の他端に電気的に接続するように第4引出電極39が形成され、第3及び第4引出電極38,39における引出線を接続するためのパッド部38c,39cを除いた基板上のすべての素子32,33,34,36,37,41を被覆するようにSiO2からなる保護膜42が形成され、この保護膜42を介して下部電極41上に薄膜コンデンサ用上部電極43が形成され、下部電極41と保護膜42と上部電極43により薄膜コンデンサ44(図8)を構成したことを特徴とする薄型複合素子30である。 7 and 8, the thin film thermistor 32, the thin film resistor 36, and the thin film capacitor lower electrode 41 are formed on the insulating substrate 31 so as to be separated from each other. A pair of comb-shaped electrodes 33 and 34 facing each other is formed on the substrate 31, and one of the pair of comb-shaped electrodes 34, one end of the thin film resistor 36, and one end of the lower electrode 41 are electrically connected to each other on the substrate 31. A connection layer 37 is formed on the substrate 31, a third extraction electrode 38 is formed on the substrate 31 so as to be electrically connected to the other of the pair of comb electrodes 33, and the other end of the thin film resistor 36 is electrically connected to the substrate 31. The fourth lead electrode 39 is formed so as to be connected to each other, and all the elements 32, 33, on the substrate except the pad portions 38c, 39c for connecting the lead lines in the third and fourth lead electrodes 38, 39 are formed. 34, 36, 37, 4 A protective film 42 made of SiO 2 is formed so as to cover 1, and an upper electrode 43 for a thin film capacitor is formed on the lower electrode 41 via the protective film 42, and the lower electrode 41, the protective film 42, and the upper electrode 43 are formed. This is a thin composite element 30 characterized in that a thin film capacitor 44 (FIG. 8) is formed.

本願請求項9に係る発明は、図1、図2及び図4に示すように、絶縁基板11上に所定のパターンで薄膜コンデンサ用下部電極17を形成する工程と、この下部電極17の上に誘電体層18を形成する工程と、基板11上に下部電極17とは別に所定のパターンで薄膜サーミスタ12を形成する工程と、基板11上に下部電極17及び薄膜サーミスタ12とは別に所定のパターンで薄膜抵抗16を形成する工程と、薄膜サーミスタ12上に相対向する一対の櫛型電極13,14を形成するとともに誘電体層18上薄膜コンデンサ用上部電極19を形成する工程と、基板11上に一対の櫛型電極の一方14と薄膜抵抗16の一端と上部電極19又は下部電極の一端とを互いに電気的に接続するように接続層22を形成する工程と、基板11上に一対の櫛型電極の他方13に電気的に接続するように第1引出電極23を形成する工程と、基板11上に薄膜抵抗16の他端に電気的に接続するように第2引出電極24を形成する工程と、下部電極17又は上部電極、第1引出電極23及び第2引出電極24における引出線を接続するためのパッド部17c,23c,24cを除いた基板上のすべての素子12,13,14,16,18,19,22を被覆するように保護膜26を形成する工程とを含む薄型複合素子10の製造方法である。   As shown in FIGS. 1, 2 and 4, the invention according to claim 9 of the present application forms a thin film capacitor lower electrode 17 in a predetermined pattern on an insulating substrate 11, and a step of forming a thin film capacitor lower electrode 17 on the lower electrode 17. A step of forming the dielectric layer 18, a step of forming the thin film thermistor 12 in a predetermined pattern separately from the lower electrode 17 on the substrate 11, and a predetermined pattern separately from the lower electrode 17 and the thin film thermistor 12 on the substrate 11. Forming a thin film resistor 16, forming a pair of comb-shaped electrodes 13 and 14 on the thin film thermistor 12, forming a thin film capacitor upper electrode 19 on the dielectric layer 18, and on the substrate 11. Forming a connection layer 22 so as to electrically connect one of the pair of comb-shaped electrodes 14, one end of the thin film resistor 16, and one end of the upper electrode 19 or the lower electrode; A step of forming a first extraction electrode 23 so as to be electrically connected to the other 13 of the pair of comb electrodes, and a second extraction electrode 24 so as to be electrically connected to the other end of the thin film resistor 16 on the substrate 11. All the elements 12 on the substrate excluding the pad portions 17c, 23c, 24c for connecting the lead lines in the lower electrode 17 or the upper electrode, the first lead electrode 23, and the second lead electrode 24, 13, 14, 16, 18, 19, 22 and forming a protective film 26 so as to cover the thin composite element 10.

本願請求項13に係る発明は、図7、図8及び図9に示すように、絶縁基板31上に所定のパターンで薄膜サーミスタ32を形成する工程と、基板31上に所定のパターンで薄膜サーミスタ32とは別に薄膜抵抗36を形成する工程と、薄膜サーミスタ32上に相対向する一対の櫛型電極33,34を形成する工程と、基板31上に一対の櫛型電極の一方34と薄膜抵抗36の一端とを互いに電気的に接続するように接続層37を形成する工程と、基板31上に一対の櫛型電極の他方33に電気的に接続するように第3引出電極38を形成する工程と、基板31上に薄膜抵抗36の他端に電気的に接続するように第4引出電極39を形成する工程と、基板31上に接続層37に電気的に接続するように薄膜コンデンサ用下部電極41を形成する工程と、第3及び第4引出電極38,39における引出線を接続するためのパッド部38c,39cを除いた基板上のすべての素子32,33,34,36,37,41を被覆するようにSiO2からなる保護膜42を形成する工程と、保護膜42を介して下部電極41上に薄膜コンデンサ用上部電極43を形成する工程とを含む薄型複合素子30の製造方法である。 As shown in FIGS. 7, 8, and 9, the invention according to claim 13 includes a step of forming a thin film thermistor 32 with a predetermined pattern on an insulating substrate 31, and a thin film thermistor with a predetermined pattern on the substrate 31. The step of forming a thin film resistor 36 separately from 32, the step of forming a pair of comb electrodes 33, 34 opposite to each other on the thin film thermistor 32, and one of the pair of comb electrodes 34 on the substrate 31 and the thin film resistor Forming a connection layer 37 so as to electrically connect one end of 36 to each other, and forming a third lead electrode 38 on the substrate 31 so as to be electrically connected to the other 33 of the pair of comb electrodes. A step of forming a fourth lead electrode 39 so as to be electrically connected to the other end of the thin film resistor 36 on the substrate 31, and a thin film capacitor so as to be electrically connected to the connection layer 37 on the substrate 31. Form lower electrode 41 All the elements 32, 33, 34, 36, 37, 41 on the substrate except for the pad portions 38 c, 39 c for connecting the lead lines in the process and the third and fourth lead electrodes 38, 39 are covered. The method of manufacturing the thin composite element 30 includes a step of forming a protective film 42 made of SiO 2 and a step of forming an upper electrode 43 for a thin film capacitor on the lower electrode 41 via the protective film 42.

本願請求項3又は7に係る発明は、請求項1又は5に係る発明であって、絶縁基板11,31が基板上面に絶縁膜11b,31bを有するシリコン基板11a,31aであって、薄膜サーミスタ12,32の下方に絶縁膜11b,31bを残してシリコン基板11a,31aの空洞又は凹部11c,31cが形成された薄型複合素子10,30である。   The invention according to claim 3 or 7 of the present application is the invention according to claim 1 or 5, wherein the insulating substrates 11 and 31 are silicon substrates 11 a and 31 a having insulating films 11 b and 31 b on the upper surface of the substrate, and a thin film thermistor The thin composite elements 10 and 30 are formed in which the cavities or recesses 11c and 31c of the silicon substrates 11a and 31a are formed, leaving the insulating films 11b and 31b below the layers 12 and 32.

本願請求項11又は15に係る発明は、請求項9又は13に係る発明であって、絶縁基板11,31が基板上面に絶縁膜11b,31bを有するシリコン基板11a,31aであって、薄膜サーミスタ12,32の下方に絶縁膜11b,31bをエッチングストッパとしてエッチングによりシリコン基板11a,31aの空洞又は凹部11c,31cを形成する薄型複合素子10,30の製造方法である。   The invention according to claim 11 or 15 of the present application is the invention according to claim 9 or 13, wherein the insulating substrates 11 and 31 are silicon substrates 11a and 31a having insulating films 11b and 31b on the upper surface of the substrate, respectively, and a thin film thermistor This is a method for manufacturing the thin composite elements 10 and 30 in which the cavities or recesses 11c and 31c of the silicon substrates 11a and 31a are formed by etching using the insulating films 11b and 31b as etching stoppers below the layers 12 and 32.

本願請求項1又は5に係る薄型複合素子では、サーミスタ、抵抗及びコンデンサがそれぞれ薄膜であって、同一の基板上に設けられるため、複合素子を1チップ化するとともに薄型にすることができ、この複合素子は熱容量が小さくなり、高速熱応答性が高い。またこの薄型複合素子は、図3に示すように、サーミスタ12、抵抗16及びコンデンサ21と電極17,23,24を備えた発振形測温回路を形成する。更に引出線を接続するためのパッド部を除いた基板上のすべての素子を保護膜で被覆するため、サーミスタが直接外部雰囲気に触れない。これにより複合素子が使用される雰囲気の湿度の影響を受けにくく、耐湿性に優れる。   In the thin composite element according to claim 1 or 5 of the present application, the thermistor, the resistor and the capacitor are each a thin film and are provided on the same substrate. The composite element has a small heat capacity and high rapid thermal response. Further, as shown in FIG. 3, this thin composite element forms an oscillation type temperature measuring circuit including a thermistor 12, a resistor 16, a capacitor 21, and electrodes 17, 23, and 24. Further, since all the elements on the substrate except for the pad portion for connecting the leader line are covered with the protective film, the thermistor does not directly touch the external atmosphere. Thereby, it is hard to be influenced by the humidity of the atmosphere in which the composite element is used, and is excellent in moisture resistance.

また本願請求項9又は13に係る薄型複合素子の製造方法によれば、上記特長のある薄型複合素子を製造できる。   According to the method for manufacturing a thin composite element according to claim 9 or 13 of the present application, it is possible to manufacture a thin composite element having the above features.

また本願請求項3又は7に係る薄型複合素子は薄膜サーミスタの下方に絶縁膜を残してシリコン基板の空洞又は凹部が形成されるため、薄膜サーミスタがメンブレン構造になり、高速熱応答性が更に高くなる。   Further, in the thin composite element according to claim 3 or 7 of the present invention, since the cavity or recess of the silicon substrate is formed leaving the insulating film below the thin film thermistor, the thin film thermistor has a membrane structure, and the high-speed thermal response is further improved. Become.

更に本願請求項11又は15に係る薄型複合素子の製造方法では、シリコン基板上の絶縁膜をエッチングストッパとして、エッチングによりシリコン基板に空洞又は凹部を容易に形成することができる。   Furthermore, in the method for manufacturing a thin composite element according to claim 11 or 15 of the present application, a cavity or a recess can be easily formed in the silicon substrate by etching using the insulating film on the silicon substrate as an etching stopper.

以下、本発明を実施するための最良の実施の形態について説明する。   The best mode for carrying out the present invention will be described below.

<第1の実施の形態>
図1及び図2に示すように、本発明の第1実施形態の薄型複合素子10は、絶縁基板11上に薄膜サーミスタ12と一対の櫛型電極13,14と薄膜抵抗16と薄膜コンデンサ21と接続層22と第1引出電極23と第2引出電極24と保護膜26を備える。薄膜サーミスタ12と薄膜抵抗16と薄膜コンデンサ21とは基板上に互いに離間して形成される。絶縁基板11としては、シリコン基板11aとこの基板上面に形成された絶縁膜11bとを有するものが例示される。絶縁膜付きシリコン基板11は、後述する空洞又は凹部(図5及び図6参照)を絶縁膜の下にエッチングにより形成し易いため、好ましい。その他の絶縁基板としては、ガラス基板、セラミック基板等が挙げられる。基板は厚さ0.1〜0.5mmの範囲から決められる。絶縁膜付きシリコン基板は、シリコン基板を熱酸化することにより、またシリコン基板表面に化学気相成長法により、基板表面に厚さ100〜1000nmのSiO2膜を有するように形成される。
<First Embodiment>
As shown in FIGS. 1 and 2, the thin composite element 10 according to the first embodiment of the present invention includes a thin film thermistor 12, a pair of comb electrodes 13 and 14, a thin film resistor 16, and a thin film capacitor 21 on an insulating substrate 11. A connection layer 22, a first extraction electrode 23, a second extraction electrode 24, and a protective film 26 are provided. The thin film thermistor 12, the thin film resistor 16, and the thin film capacitor 21 are formed on the substrate so as to be separated from each other. Examples of the insulating substrate 11 include those having a silicon substrate 11a and an insulating film 11b formed on the upper surface of the substrate. The silicon substrate 11 with an insulating film is preferable because a cavity or a recess (see FIGS. 5 and 6) described later can be easily formed by etching under the insulating film. Examples of other insulating substrates include glass substrates and ceramic substrates. The substrate is determined from a thickness range of 0.1 to 0.5 mm. The silicon substrate with an insulating film is formed so as to have a SiO 2 film having a thickness of 100 to 1000 nm on the substrate surface by thermally oxidizing the silicon substrate and by chemical vapor deposition on the silicon substrate surface.

薄膜サーミスタ12は、Mn−Co系複合金属酸化物(MnxCo1-x)34(但し0.3≦x≦0.6)、又はMn−Co系複合金属酸化物にNi、Fe、Cu及びAlからなる群より選ばれた少なくとも1種を含む複合金属酸化物(例えば、(MnxCoyFe1-x-y)34(但し0.2≦x≦0.6、0.02≦y≦0.65)からなる複合金属酸化物である。この複合金属酸化物はスピネル型結晶構造を有し、膜厚方向に延在する柱状結晶構造を有している。Mn、Co、Ni、Fe、Cu、Al等の組成比はサーミスタの所望の特性に応じて決められる。この薄膜サーミスタ12の厚さは所望の特性に応じて100〜1000nmの範囲から決められる。薄膜抵抗はNi−Cr系合金からなる。この実施の形態では、薄膜抵抗は所望の抵抗値を得るために抵抗線を折り畳んだような形状に成膜される。 The thin film thermistor 12 is made of Mn—Co based composite metal oxide (Mn x Co 1-x ) 3 O 4 (where 0.3 ≦ x ≦ 0.6), or Mn—Co based composite metal oxide with Ni, Fe , Cu and Al, a composite metal oxide containing at least one selected from the group consisting of Cu and Al (for example, (Mn x Co y Fe 1-xy ) 3 O 4 (provided that 0.2 ≦ x ≦ 0.6, 0. 02 ≦ y ≦ 0.65) This composite metal oxide has a spinel crystal structure and a columnar crystal structure extending in the film thickness direction.Mn, Co The composition ratio of Ni, Fe, Cu, Al, etc. is determined according to the desired characteristics of the thermistor, and the thickness of the thin film thermistor 12 is determined from the range of 100 to 1000 nm according to the desired characteristics. In this embodiment, the thin film resistance is a desired value. It is formed in a shape like folded resistance wire in order to obtain the anti-values.

薄膜コンデンサ21は絶縁基板11上に形成された下部電極17とこの下部電極より小面積で下部電極上に形成された誘電体層18とこの誘電体層より小面積で誘電体層上に形成された上部電極19とにより構成される。即ち、下部電極における引出線を接続するためのパッド部17cを形成するために下部電極17の一部が誘電体層及び上部電極を積層した後も露出する。この誘電体層18は(Ba1-xSrx)TiO3(但し0≦x≦1.0)からなる複合酸化物であって、ペロブスカイト型構造を有する。誘電体層の厚さは所望の特性に応じて100〜1000nmの範囲から決められる。 The thin film capacitor 21 is formed on the dielectric layer with a lower electrode 17 formed on the insulating substrate 11, a dielectric layer 18 formed on the lower electrode with a smaller area than the lower electrode, and with a smaller area than the dielectric layer. And the upper electrode 19. That is, a part of the lower electrode 17 is exposed even after the dielectric layer and the upper electrode are laminated in order to form the pad portion 17c for connecting the lead line in the lower electrode. The dielectric layer 18 is a complex oxide made of (Ba 1-x Sr x ) TiO 3 (where 0 ≦ x ≦ 1.0) and has a perovskite structure. The thickness of the dielectric layer is determined from the range of 100 to 1000 nm according to desired characteristics.

一対の櫛型電極13,14は、薄膜サーミスタ12上に成膜されたCr、Ti等の接合層13a,14aと、この接合層上に接合層と同形同大に成膜されたAu、Pt等の導電層13b,14bとにより構成される。また薄膜コンデンサ用下部電極17及び上部電極19は、絶縁基板及び誘電体層上にそれぞれ成膜されたCr、Ti等の接合層17a,19aと、この接合層上に接合層と同形同大に成膜されたAu、Pt等の導電層17b,19bとにより構成される。また接続層22は、絶縁基板上に成膜されたCr、Ti等の接合層22aと、この接合層上に接合層と同形同大に成膜されたAu、Pt等の導電層22bとにより構成される。この接続層22は、一方の櫛型電極14と薄膜抵抗16の一端と上部電極19の一端とを互いに電気的に接続するように基板上に形成される。   The pair of comb-shaped electrodes 13 and 14 are formed by bonding layers 13a and 14a such as Cr and Ti formed on the thin film thermistor 12, Au formed on the bonding layer in the same shape and size as the bonding layers, It is composed of conductive layers 13b and 14b such as Pt. Also, the lower electrode 17 and the upper electrode 19 for the thin film capacitor are formed by bonding layers 17a and 19a such as Cr and Ti formed on the insulating substrate and the dielectric layer, respectively, and the same shape and size as the bonding layer on the bonding layer. And the conductive layers 17b and 19b made of Au, Pt or the like. The connection layer 22 includes a bonding layer 22a made of Cr, Ti or the like formed on an insulating substrate, and a conductive layer 22b made of Au, Pt or the like formed on the bonding layer in the same shape and size as the bonding layer. Consists of. The connection layer 22 is formed on the substrate so as to electrically connect one of the comb electrodes 14, one end of the thin film resistor 16, and one end of the upper electrode 19.

また第1引出電極23は、絶縁基板上に成膜されたCr、Ti等の接合層23aと、この接合層上に接合層と同形同大に成膜されたAu、Pt等の導電層23bとにより構成され、第2引出電極24も同様に構成される。第1引出電極23は他方の櫛型電極13に、また第2引出電極24は薄膜抵抗16の他端に電気的に接続する。接合層は導電層の下地層として導電層の絶縁基板等への接合度を高める機能を有する。更に下部電極17、第1及び第2引出電極23,24におけるリード線等の引出線(図示せず)を接続するためのパッド部17c,23c,24を除いた基板上のすべての素子、即ち薄膜サーミスタ12、一対の櫛型電極13,14、薄膜抵抗16、誘電体層18、上部電極19,接続層22は、二酸化ケイ素(SiO2)、窒化ケイ素(Si34)等の保護膜26により被覆される。これにより図3に示すように、サーミスタ12、抵抗16及びコンデンサ21と電極17,23,24を備えた発振形測温回路を形成した、総厚0.1〜0.5mmのたて1〜4mm、よこ1〜4mmの薄型複合素子10が得られる。 The first extraction electrode 23 includes a bonding layer 23a made of Cr, Ti or the like formed on an insulating substrate, and a conductive layer made of Au, Pt or the like formed on the bonding layer in the same shape and size as the bonding layer. 23b, and the second extraction electrode 24 is similarly configured. The first extraction electrode 23 is electrically connected to the other comb electrode 13, and the second extraction electrode 24 is electrically connected to the other end of the thin film resistor 16. The bonding layer has a function of increasing the degree of bonding of the conductive layer to an insulating substrate or the like as a base layer of the conductive layer. Further, all elements on the substrate except for the pad portions 17c, 23c, 24 for connecting lead wires (not shown) such as lead wires in the lower electrode 17, the first and second lead electrodes 23, 24, that is, The thin film thermistor 12, the pair of comb electrodes 13, 14, the thin film resistor 16, the dielectric layer 18, the upper electrode 19, and the connection layer 22 are protective films such as silicon dioxide (SiO 2 ) and silicon nitride (Si 3 N 4 ). 26. As a result, as shown in FIG. 3, an oscillation type temperature measuring circuit having the thermistor 12, the resistor 16, the capacitor 21, and the electrodes 17, 23, 24 is formed. A thin composite element 10 of 4 mm and a width of 1 to 4 mm is obtained.

なお、上記実施の形態では、薄膜コンデンサの下部電極17の一部を露出してリード線等の引出線を接続するためのパッド部17cを形成するようにしたが、下部電極、誘電体層及び上部電極の順に面積を大きくして上部電極にこのパッド部を設けるようにしてもよい。この場合、下部電極の一端が接続層に接続される。   In the above embodiment, a part of the lower electrode 17 of the thin film capacitor is exposed to form the pad portion 17c for connecting a lead line such as a lead wire. However, the lower electrode, the dielectric layer, The pads may be provided on the upper electrode by increasing the area in the order of the upper electrode. In this case, one end of the lower electrode is connected to the connection layer.

<第2の実施の形態>
図7及び図8に示すように、本発明の第2実施形態の薄型複合素子30は、絶縁基板31上に薄膜サーミスタ32と一対の櫛型電極33,34と薄膜抵抗36と接続層37と第3引出電極38と第4引出電極39と保護膜42と下部電極41−保護膜42−上部電極43で構成される薄膜コンデンサ44を備える。絶縁基板31としては、シリコン基板31aとこの基板上面に形成された絶縁膜31bとを有するものが例示される。絶縁膜付きシリコン基板31は、後述する空洞又は凹部(図10及び図11参照)を絶縁膜の下にエッチングにより形成し易いため、好ましい。絶縁基板の厚さ、種類及び絶縁膜付きシリコン基板の製造方法は第1の実施形態と同じである。
<Second Embodiment>
As shown in FIGS. 7 and 8, the thin composite element 30 according to the second embodiment of the present invention includes a thin film thermistor 32, a pair of comb-shaped electrodes 33 and 34, a thin film resistor 36, and a connection layer 37 on an insulating substrate 31. A thin film capacitor 44 including a third extraction electrode 38, a fourth extraction electrode 39, a protective film 42, a lower electrode 41, a protective film 42, and an upper electrode 43 is provided. Examples of the insulating substrate 31 include those having a silicon substrate 31a and an insulating film 31b formed on the upper surface of the substrate. The silicon substrate 31 with an insulating film is preferable because a cavity or a concave portion (see FIGS. 10 and 11) described later can be easily formed by etching under the insulating film. The thickness and type of the insulating substrate and the method for manufacturing the silicon substrate with the insulating film are the same as those in the first embodiment.

絶縁基板31上に形成される薄膜サーミスタ32の組成は、第1の実施形態の薄膜サーミスタ12の組成と同じであり、薄膜サーミスタ32の形状、大きさ、配置は、第1の実施形態の薄膜サーミスタ12の形状、大きさ、配置とほぼ同じである。同様に一対の櫛型電極33,34の組成、形状、大きさ、配置は一対の櫛型電極13,14の組成、形状、大きさ、配置と同じである。薄膜抵抗36の組成は、第1の実施形態の薄膜抵抗16の組成と同じであり、薄膜抵抗36の形状、大きさ、配置は、第1の実施形態の薄膜抵抗16の形状、大きさ、配置とほぼ同じである。第3及び第4引出電極38,39の組成、形状、大きさ、配置は、第1の実施形態の第1及び第2引出電極23,24の形状、大きさ、配置とほぼ同じである。   The composition of the thin film thermistor 32 formed on the insulating substrate 31 is the same as that of the thin film thermistor 12 of the first embodiment, and the shape, size and arrangement of the thin film thermistor 32 are the same as those of the thin film thermistor 32 of the first embodiment. The thermistor 12 has almost the same shape, size and arrangement. Similarly, the composition, shape, size and arrangement of the pair of comb electrodes 33 and 34 are the same as the composition, shape, size and arrangement of the pair of comb electrodes 13 and 14. The composition of the thin film resistor 36 is the same as that of the thin film resistor 16 of the first embodiment, and the shape, size, and arrangement of the thin film resistor 36 are the same as those of the thin film resistor 16 of the first embodiment. Almost the same as the arrangement. The composition, shape, size, and arrangement of the third and fourth extraction electrodes 38, 39 are substantially the same as the shape, size, and arrangement of the first and second extraction electrodes 23, 24 of the first embodiment.

この実施の形態の特徴ある構成は薄膜コンデンサの構成にある。図8に示すように、この薄膜コンデンサ44は、絶縁基板31上に下部電極41を形成し、この下部電極を後述する保護膜42で被覆し、下部電極上に保護膜42を介して上部電極43を形成することにより構成される。接続層37は、一方の櫛型電極34と薄膜抵抗36の一端と下部電極41の一端とを互いに電気的に接続するように基板上に形成される。この実施の形態における保護膜42は、誘電体の特性を有する二酸化ケイ素(SiO2)で構成される。第1の実施形態の保護膜26と同様に、リード線等の引出線(図示せず)を接続するための第3引出電極38cのパッド部38c及び第4引出電極39のパッド部39cを除いたすべての素子、即ち薄膜サーミスタ32、一対の櫛型電極33,34、薄膜抵抗36、接続層37及び下部電極41を保護膜42は被覆する。薄膜コンデンサ44を上記のように構成することにより、小型化、低コスト化を図ることができる特長を有する。これにより総厚0.1〜0.5mmのたて1〜4mm、よこ1〜4mmの薄型複合素子30が得られる。 The characteristic configuration of this embodiment is the configuration of a thin film capacitor. As shown in FIG. 8, in this thin film capacitor 44, a lower electrode 41 is formed on an insulating substrate 31, this lower electrode is covered with a protective film 42 to be described later, and the upper electrode is placed on the lower electrode via the protective film 42. It is comprised by forming 43. The connection layer 37 is formed on the substrate so as to electrically connect one comb electrode 34, one end of the thin film resistor 36, and one end of the lower electrode 41 to each other. The protective film 42 in this embodiment is made of silicon dioxide (SiO 2 ) having dielectric properties. Similar to the protective film 26 of the first embodiment, the pad portion 38c of the third lead electrode 38c and the pad portion 39c of the fourth lead electrode 39 for connecting a lead wire (not shown) such as a lead wire are excluded. The protective film 42 covers all the elements, that is, the thin film thermistor 32, the pair of comb electrodes 33 and 34, the thin film resistor 36, the connection layer 37, and the lower electrode 41. By configuring the thin film capacitor 44 as described above, the thin film capacitor 44 can be reduced in size and cost. As a result, a thin composite element 30 having a total thickness of 0.1 to 0.5 mm and a length of 1 to 4 mm and a width of 1 to 4 mm is obtained.

<第3の実施の形態>
図5に示すように、本発明の第3実施形態の薄型複合素子10は、第1の実施形態の薄型複合素子10の薄膜サーミスタ12の下方に絶縁膜11bを残してシリコン基板11aの凹部11cが形成される。図示しないが、凹部11cの代わりに空洞でもよい。
<Third Embodiment>
As shown in FIG. 5, the thin composite element 10 according to the third embodiment of the present invention includes a recess 11c in the silicon substrate 11a, leaving an insulating film 11b below the thin film thermistor 12 of the thin composite element 10 according to the first embodiment. Is formed. Although not shown, a cavity may be used instead of the recess 11c.

<第4の実施の形態>
図10に示すように、本発明の第4実施形態の薄型複合素子30は、第2の実施形態の薄型複合素子30の薄膜サーミスタ32の下方に絶縁膜31bを残してシリコン基板31aの凹部31cが形成される。図示しないが、凹部31cの代わりに空洞でもよい。
<Fourth embodiment>
As shown in FIG. 10, the thin composite element 30 of the fourth embodiment of the present invention has a recess 31c in the silicon substrate 31a, leaving an insulating film 31b below the thin film thermistor 32 of the thin composite element 30 of the second embodiment. Is formed. Although not shown, a cavity may be used instead of the recess 31c.

次に本発明の実施例を説明する。   Next, examples of the present invention will be described.

<実施例1>
図1及び図2に示される薄型複合素子の製造方法を説明する。先ず図4(a)に示すように、熱酸化法により、厚さ0.25mmのシリコン基板11aに層厚500nmのSiO2層11bを形成する。
(a) 上部電極を除く薄膜コンデンサの形成
薄膜コンデンサ用下部電極17を形成するために、SiO2層11bの上面全体にCr薄膜を膜厚が100nmとなるようにスパッタリング法により形成する。続けて、このCr薄膜上にAu薄膜を膜厚が200nmとなるようにスパッタリング法により形成する。このAu薄膜の全面に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、ヨウ素ヨウ化カリウム溶液を用いたウエットエッチングによりAu薄膜をパターニングし、所望の下部電極17の導電層17bを得る(図2)。続けて、硝酸セリウムアンモニウム溶液を用いたウエットエッチングにより、上記Cr薄膜をAu薄膜と同構造にパターニングし、SiO2層11b上に、図4(b)に示すように、接合層17aを形成して(図2)、薄膜コンデンサ用下部電極17を得る。
<Example 1>
A method for manufacturing the thin composite element shown in FIGS. 1 and 2 will be described. First, as shown in FIG. 4A, a SiO 2 layer 11b having a layer thickness of 500 nm is formed on a silicon substrate 11a having a thickness of 0.25 mm by a thermal oxidation method.
(a) Formation of Thin Film Capacitor Excluding Upper Electrode In order to form the lower electrode 17 for the thin film capacitor, a Cr thin film is formed on the entire upper surface of the SiO 2 layer 11b by a sputtering method so as to have a film thickness of 100 nm. Subsequently, an Au thin film is formed on the Cr thin film by sputtering so that the film thickness becomes 200 nm. A photosensitive resin is formed on the entire surface of the Au thin film, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, the Au thin film is patterned by wet etching using a potassium iodide iodide solution to obtain a desired conductive layer 17b of the lower electrode 17 (FIG. 2). Subsequently, the Cr thin film is patterned into the same structure as the Au thin film by wet etching using a cerium ammonium nitrate solution, and a bonding layer 17a is formed on the SiO 2 layer 11b as shown in FIG. 4B. (FIG. 2), the thin film capacitor lower electrode 17 is obtained.

SiO2層11b及び下部電極17の上面全体に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、Ba0.7Sr0.3TiO3からなる複合酸化物の薄膜を膜厚が1μmとなるように下部電極17上にスパッタリング法により形成する。次に、図4(c)に示すようにリフトオフ法により、上記複合酸化物の薄膜を所望の形状にパターニングして、誘電体層18を得る。
(b) 薄膜サーミスタの形成
SiO2層11b、下部電極17及び誘電体層18の上面全体に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。次いで、(Mn0.4Co0.6)34のスピネル構造の薄膜を膜厚が500nmとなるようにスパッタリング法により形成する。次に、リフトオフ法により、上記スピネル構造の薄膜を所望の形状にパターニングする。この基板を800℃で1時間熱処理し、図4(d)に示すように、抵抗値及びB定数の信頼性の高い薄膜サーミスタ12を得る。
(c) 薄膜抵抗の形成
SiO2層11b、下部電極17、誘電体層18及び薄膜サーミスタ12の上面全体にNi−Cr系の薄膜を膜厚が500nmとなるようにスパッタリング法により形成する。この薄膜の上面全体に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、塩化第2鉄溶液を用いたウエットエッチングにより、Ni−Cr系の薄膜を所望の形状にパターニングして、図4(e)に示すように、薄膜抵抗16を得る。
(d) 櫛型電極、薄膜コンデンサ用上部電極、引出電極及び接続層の形成
SiO2層11b、下部電極17、誘電体層18、薄膜サーミスタ12及び薄膜抵抗16の上面全体にCr薄膜を膜厚が100nmとなるようにスパッタリング法により形成する。続けて、このCr薄膜上にAu薄膜を膜厚が200nmとなるようにスパッタリング法により形成する。このAu薄膜の全面に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、ヨウ素ヨウ化カリウム溶液を用いたウエットエッチングによりAu薄膜をパターニングし、所望の電極及び接続層の導電層13b,14b,19b,23b及び22bを得る(図2)。続けて、硝酸セリウムアンモニウム溶液を用いたウエットエッチングにより、上記Cr薄膜をAu薄膜と同構造にパターニングし、接合層13a,14a,19a,23a及び22aを形成して(図2)、図1及び図4(f)に示すように、櫛型電極13,14、薄膜コンデンサ用上部電極19、引出電極23,24及び接続層22を得る。
(e) 保護膜の形成
各種電極及び接続層を形成した後、基板の上面全体にSiO2薄膜を膜厚が600nmとなるようにスパッタリング法により形成する。SiO2薄膜の全面に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、フッ酸を用いたウエットエッチングによりSiO2薄膜をパターニングし、図4(g)に示すように、リード線等の引出し線を接続するパッド部17c,23c及び24cのみを露出させ、他のすべての素子をSiO2からなる保護膜26で被覆する。これにより総厚0.25mmのたて3mm、よこ2mmの薄型複合素子10が得られる。
A photosensitive resin is formed on the entire upper surface of the SiO 2 layer 11b and the lower electrode 17, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, a thin film of composite oxide made of Ba 0.7 Sr 0.3 TiO 3 is formed on the lower electrode 17 by sputtering so that the film thickness becomes 1 μm. Next, as shown in FIG. 4C, the composite oxide thin film is patterned into a desired shape by a lift-off method to obtain the dielectric layer 18.
(b) Formation of thin film thermistor A photosensitive resin is formed on the entire upper surface of the SiO 2 layer 11b, the lower electrode 17 and the dielectric layer 18, and is exposed to light and developed using a predetermined photomask. Is patterned. Next, a thin film having a spinel structure of (Mn 0.4 Co 0.6 ) 3 O 4 is formed by a sputtering method so as to have a film thickness of 500 nm. Next, the thin film having the spinel structure is patterned into a desired shape by a lift-off method. The substrate is heat-treated at 800 ° C. for 1 hour to obtain a thin film thermistor 12 having a high resistance value and a highly reliable B constant, as shown in FIG.
(c) Formation of Thin Film Resistor A Ni—Cr thin film is formed on the entire upper surface of the SiO 2 layer 11b, the lower electrode 17, the dielectric layer 18 and the thin film thermistor 12 by a sputtering method so as to have a film thickness of 500 nm. A photosensitive resin is formed on the entire upper surface of the thin film, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, the Ni—Cr thin film is patterned into a desired shape by wet etching using a ferric chloride solution to obtain a thin film resistor 16 as shown in FIG. .
(d) Formation of comb-shaped electrode, upper electrode for thin film capacitor, lead electrode and connection layer Cr thin film is formed on the entire upper surface of SiO 2 layer 11b, lower electrode 17, dielectric layer 18, thin film thermistor 12 and thin film resistor 16. Is formed by a sputtering method so as to be 100 nm. Subsequently, an Au thin film is formed on the Cr thin film by sputtering so that the film thickness becomes 200 nm. A photosensitive resin is formed on the entire surface of the Au thin film, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, the Au thin film is patterned by wet etching using a potassium iodide iodide solution to obtain conductive layers 13b, 14b, 19b, 23b, and 22b of desired electrodes and connection layers (FIG. 2). Subsequently, the Cr thin film is patterned into the same structure as the Au thin film by wet etching using a cerium ammonium nitrate solution to form bonding layers 13a, 14a, 19a, 23a, and 22a (FIG. 2), and FIG. As shown in FIG. 4F, the comb electrodes 13 and 14, the thin film capacitor upper electrode 19, the lead electrodes 23 and 24, and the connection layer 22 are obtained.
(e) Formation of Protective Film After forming various electrodes and connection layers, a SiO 2 thin film is formed on the entire upper surface of the substrate by sputtering so as to have a film thickness of 600 nm. A photosensitive resin is formed on the entire surface of the SiO 2 thin film, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, the SiO 2 thin film is patterned by wet etching using hydrofluoric acid, and as shown in FIG. 4G, only the pad portions 17c, 23c, and 24c for connecting lead lines such as lead wires are provided. And all other elements are covered with a protective film 26 made of SiO 2 . As a result, a thin composite element 10 having a total thickness of 0.25 mm and a length of 3 mm and a width of 2 mm is obtained.

以上、単一の複合素子の製造方法について述べたが、複合素子を量産するときには、1枚のシリコン基板上に薄膜のサーミスタ・抵抗・コンデンサからなる多数の複合素子を形成し、その基板を切断により個々の薄型複合素子を得る。   The manufacturing method of a single composite element has been described above. When mass-producing composite elements, a large number of composite elements composed of thin film thermistors, resistors, and capacitors are formed on a single silicon substrate, and the substrate is cut. Thus, individual thin composite elements are obtained.

<実施例2>
図5に示される薄型複合素子の製造方法を説明する。図4(g)に示される複合素子10を裏返した後、図6(a)に示すように薄膜サーミスタ12の裏側に相当する部分にSiO2層11dを取り除いた四角形の窓27を形成する。このシリコン基板11aには上面にSiO2層11bが下面にSiO2層11dが形成されている。この窓27は、窓となる部分以外のSiO2層11dを感光性樹脂でマスクし、フッ酸を用いたウエットエッチングによりSiO2層11dをパターニングすることにより、形成される。続いて、上記感光性樹脂をマスクとし、水酸化テトラメチルアンモニア水溶液(TMAH)を用いたウエットエッチングにより薄膜サーミスタの下部(図6では上部)に相当するシリコン基板11aの一部をエッチングし、図6(b)に示すようにサーミスタをメンブレン構造にした薄型複合素子を得る。
<Example 2>
A method of manufacturing the thin composite element shown in FIG. 5 will be described. After turning over the composite element 10 shown in FIG. 4G, a rectangular window 27 is formed by removing the SiO 2 layer 11d in a portion corresponding to the back side of the thin film thermistor 12 as shown in FIG. 6A. The silicon substrate 11a has an SiO 2 layer 11b formed on the upper surface and an SiO 2 layer 11d formed on the lower surface. This window 27 is formed by masking the SiO 2 layer 11d other than the window portion with a photosensitive resin and patterning the SiO 2 layer 11d by wet etching using hydrofluoric acid. Subsequently, using the photosensitive resin as a mask, a part of the silicon substrate 11a corresponding to the lower part (upper part in FIG. 6) of the thin film thermistor is etched by wet etching using a tetramethylammonium hydroxide aqueous solution (TMAH). As shown in FIG. 6B, a thin composite element having a thermistor in a membrane structure is obtained.

<実施例3>
図7及び図8に示される薄型複合素子の製造方法を説明する。先ず図9(a)に示すように、熱酸化法により、厚さ0.25mmのシリコン基板31aに層厚500nmのSiO2層31bを形成する。
(a) 薄膜サーミスタの形成
SiO2層31bの上面全体に(Mn0.4Co0.6)34のスピネル構造の薄膜を膜厚が500nmとなるようにスパッタリング法により形成する。このスピネル構造の薄膜の上面全体に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、希塩酸溶液を用いたウエットエッチングにより上記スピネル構造の薄膜を所望の形状にパターニングする。この基板を800℃で1時間熱処理し、図9(b)に示すように、抵抗値及びB定数の信頼性の高い薄膜サーミスタ32を得る。
(b) 薄膜抵抗の形成
SiO2層31b及び薄膜サーミスタ32の上面全体にNi−Cr系の薄膜を膜厚が500nmとなるようにスパッタリング法によって形成する。この薄膜の上面全体に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、塩化第2鉄溶液を用いたウエットエッチングにより、Ni−Cr系の薄膜を所望の形状にパターニングして、図9(c)に示すように、薄膜抵抗36を得る。
(c) 櫛型電極、薄膜コンデンサ用下部電極、引出電極及び接続層の形成
SiO2層31b、薄膜サーミスタ32及び薄膜抵抗36の上面全体にCr薄膜を膜厚が100nmとなるようにスパッタリング法により形成する。続けて、このCr薄膜上にAu薄膜を膜厚が200nmとなるようにスパッタリング法により形成する。このAu薄膜の全面に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、ヨウ素ヨウ化カリウム溶液を用いたウエットエッチングによりAu薄膜をパターニングし、所望の電極及び接続層の導電層33b,34b,41b,38b及び37bを得る(図8)。続けて、硝酸セリウムアンモニウム溶液を用いたウエットエッチングにより、上記Cr薄膜をAu薄膜と同構造にパターニングし、接合層33a,34a,41a,38a及び37aを形成して(図8)、図7及び図9(d)に示すように、櫛型電極33,34、薄膜コンデンサ用下部電極41、引出電極38,39及び接続層37を得る。
(d) 保護膜の形成
各種電極及び接続層を形成した後、基板の上面全体にSiO2薄膜を膜厚が600nmとなるようにスパッタリング法により形成する。SiO2薄膜の全面に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、フッ酸を用いたウエットエッチングによりSiO2薄膜をパターニングし、図9(e)に示すように、リード線等の引出し線を接続するパッド部38c及び39cのみを露出させ、他のすべての素子をSiO2からなる保護膜42で被覆する。
(e) 薄膜コンデンサ用上部電極の形成
薄膜コンデンサ用下部電極41の対向電極となる上部電極を形成するために、保護膜42の上面の所定の位置にCr薄膜を膜厚が100nmとなるようにスパッタリング法により形成する。続けて、このCr薄膜上にAu薄膜を膜厚が200nmとなるようにスパッタリング法により形成する。このAu薄膜の全面に感光性樹脂を形成し、所定のフォトマスクを用いて、露光し、現像処理を行い、感光性樹脂をパターニングする。その感光性樹脂をマスクとし、ヨウ素ヨウ化カリウム溶液を用いたウエットエッチングによりAu薄膜をパターニングし、所望の上部電極43の導電層43bを得る(図8)。続けて、硝酸セリウムアンモニウム溶液を用いたウエットエッチングにより、上記Cr薄膜をAu薄膜と同構造にパターニングし、接合層43aを形成して(図8)、図7及び図9(f)に示すように、薄膜コンデンサ用上部電極43を得る。下部電極43、保護膜42及びこの上部電極43により薄膜コンデンサ44が作製される(図8)。これにより総厚0.25mmのたて2mm、よこ2mmの薄型複合素子30が得られる。
<Example 3>
A method for manufacturing the thin composite element shown in FIGS. 7 and 8 will be described. First, as shown in FIG. 9A, a SiO 2 layer 31b having a thickness of 500 nm is formed on a silicon substrate 31a having a thickness of 0.25 mm by a thermal oxidation method.
(a) Formation of Thin Film Thermistor A thin film having a spinel structure of (Mn 0.4 Co 0.6 ) 3 O 4 is formed on the entire upper surface of the SiO 2 layer 31b by a sputtering method so as to have a film thickness of 500 nm. A photosensitive resin is formed on the entire upper surface of the spinel-structured thin film, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, the spinel-structured thin film is patterned into a desired shape by wet etching using a diluted hydrochloric acid solution. This substrate is heat-treated at 800 ° C. for 1 hour to obtain a thin film thermistor 32 having a high resistance value and a highly reliable B constant, as shown in FIG. 9B.
(b) Formation of Thin Film Resistor A Ni—Cr thin film is formed on the entire upper surface of the SiO 2 layer 31b and the thin film thermistor 32 by a sputtering method so as to have a film thickness of 500 nm. A photosensitive resin is formed on the entire upper surface of the thin film, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, the Ni—Cr thin film is patterned into a desired shape by wet etching using a ferric chloride solution to obtain a thin film resistor 36 as shown in FIG. 9C. .
(c) Formation of comb-shaped electrode, lower electrode for thin film capacitor, lead electrode and connection layer A thin Cr film is formed on the entire upper surface of the SiO 2 layer 31b, the thin film thermistor 32 and the thin film resistor 36 by a sputtering method. Form. Subsequently, an Au thin film is formed on the Cr thin film by sputtering so that the film thickness becomes 200 nm. A photosensitive resin is formed on the entire surface of the Au thin film, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, the Au thin film is patterned by wet etching using a potassium iodide iodide solution to obtain conductive layers 33b, 34b, 41b, 38b and 37b of desired electrodes and connection layers (FIG. 8). Subsequently, the Cr thin film is patterned into the same structure as the Au thin film by wet etching using a cerium ammonium nitrate solution to form bonding layers 33a, 34a, 41a, 38a and 37a (FIG. 8), and FIG. As shown in FIG. 9D, comb electrodes 33 and 34, a thin film capacitor lower electrode 41, lead electrodes 38 and 39, and a connection layer 37 are obtained.
(d) Formation of protective film After forming various electrodes and connection layers, a SiO 2 thin film is formed on the entire upper surface of the substrate by sputtering so that the film thickness becomes 600 nm. A photosensitive resin is formed on the entire surface of the SiO 2 thin film, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, the SiO 2 thin film is patterned by wet etching using hydrofluoric acid, and as shown in FIG. 9E, only the pad portions 38c and 39c for connecting the lead lines such as lead wires are exposed. All other elements are covered with a protective film 42 made of SiO 2 .
(e) Formation of upper electrode for thin film capacitor In order to form an upper electrode which is a counter electrode of lower electrode 41 for thin film capacitor, a Cr thin film is formed at a predetermined position on the upper surface of protective film 42 so that the film thickness becomes 100 nm. It is formed by a sputtering method. Subsequently, an Au thin film is formed on the Cr thin film by sputtering so that the film thickness becomes 200 nm. A photosensitive resin is formed on the entire surface of the Au thin film, exposed using a predetermined photomask, developed, and patterned. Using the photosensitive resin as a mask, the Au thin film is patterned by wet etching using a potassium iodide iodide solution to obtain a desired conductive layer 43b of the upper electrode 43 (FIG. 8). Subsequently, the Cr thin film is patterned into the same structure as the Au thin film by wet etching using a cerium ammonium nitrate solution to form a bonding layer 43a (FIG. 8), as shown in FIGS. 7 and 9 (f). Then, an upper electrode 43 for a thin film capacitor is obtained. The lower electrode 43, the protective film 42, and the upper electrode 43 form a thin film capacitor 44 (FIG. 8). As a result, a thin composite element 30 having a total thickness of 0.25 mm and a length of 2 mm and a width of 2 mm is obtained.

以上、単一の複合素子の製造方法について述べたが、複合素子を量産するときには、1枚のシリコン基板上に薄膜のサーミスタ・抵抗・コンデンサからなる多数の複合素子を形成し、その基板を切断により個々の薄型複合素子を得る。   The manufacturing method of a single composite element has been described above. When mass-producing composite elements, a large number of composite elements composed of thin film thermistors, resistors, and capacitors are formed on a single silicon substrate, and the substrate is cut. Thus, individual thin composite elements are obtained.

<実施例4>
図10に示される薄型複合素子の製造方法を説明する。図9(f)に示される複合素子30を裏返した後、図11(a)に示すように薄膜サーミスタ32の裏側に相当する部分にSiO2層31dを取り除いた四角形の窓46を形成する。このシリコン基板31aには上面にSiO2層31bが下面にSiO2層31dが形成されている。この窓46は、窓となる部分以外のSiO2層31dを感光性樹脂でマスクし、フッ酸を用いたウエットエッチングによりSiO2層31dをパターニングすることにより、形成される。続いて、上記感光性樹脂をマスクとし、水酸化テトラメチルアンモニア水溶液(TMAH)を用いたウエットエッチングにより薄膜サーミスタの下部(図11では上部)に相当するシリコン基板31aの一部をエッチングし、図11(b)に示すようにサーミスタをメンブレン構造にした薄型複合素子を得る。
<Example 4>
A method for manufacturing the thin composite element shown in FIG. 10 will be described. After turning over the composite element 30 shown in FIG. 9 (f), a rectangular window 46 is formed by removing the SiO 2 layer 31 d in the portion corresponding to the back side of the thin film thermistor 32 as shown in FIG. 11 (a). The silicon substrate 31a has an SiO 2 layer 31b formed on the upper surface and an SiO 2 layer 31d formed on the lower surface. The window 46 is formed by masking the SiO 2 layer 31d other than the window portion with a photosensitive resin and patterning the SiO 2 layer 31d by wet etching using hydrofluoric acid. Subsequently, using the photosensitive resin as a mask, a part of the silicon substrate 31a corresponding to the lower part (upper part in FIG. 11) of the thin film thermistor is etched by wet etching using a tetramethylammonium hydroxide aqueous solution (TMAH). A thin composite element having a thermistor in the membrane structure as shown in FIG.

本発明第1実施形態の薄型複合素子の分解斜視図である。It is a disassembled perspective view of the thin composite element of 1st Embodiment of this invention. 本発明第1実施形態の薄型複合素子の図1のA−A線断面図である。It is the sectional view on the AA line of FIG. 1 of the thin composite element of 1st Embodiment of this invention. 本発明第1実施形態の薄型複合素子の等価回路図である。It is an equivalent circuit diagram of the thin composite element of the first embodiment of the present invention. 本発明第1実施形態の薄型複合素子の製造工程を示す斜視図である。It is a perspective view which shows the manufacturing process of the thin composite element of 1st Embodiment of this invention. 本発明第2実施形態の図2に対応する薄型複合素子の断面図である。It is sectional drawing of the thin composite element corresponding to FIG. 2 of 2nd Embodiment of this invention. 本発明第2実施形態の薄型複合素子の製造工程を示す斜視図である。It is a perspective view which shows the manufacturing process of the thin composite element of 2nd Embodiment of this invention. 本発明第3実施形態の薄型複合素子の分解斜視図である。It is a disassembled perspective view of the thin composite element of 3rd Embodiment of this invention. 本発明第3実施形態の薄型複合素子の図7のB−B線断面図である。It is the BB sectional view taken on the line of FIG. 7 of the thin composite element of 3rd Embodiment of this invention. 本発明第3実施形態の薄型複合素子の製造工程を示す斜視図である。It is a perspective view which shows the manufacturing process of the thin composite element of 3rd Embodiment of this invention. 本発明第4実施形態の図8に対応する薄型複合素子の断面図である。It is sectional drawing of the thin composite element corresponding to FIG. 8 of 4th Embodiment of this invention. 本発明第4実施形態の薄型複合素子の製造工程を示す斜視図である。It is a perspective view which shows the manufacturing process of the thin composite element of 4th Embodiment of this invention.

符号の説明Explanation of symbols

10: 薄型複合素子
11: 絶縁基板
12: 薄膜サーミスタ
13,14: 一対の櫛型電極
16: 薄膜抵抗
17: 下部電極
17a: 接合層
17b: 導電層
17c: パッド部
18: 誘電体層
19: 上部電極
21: 薄膜コンデンサ
22: 接続層
23: 第1引出電極
23a: 接合層
23b: 導電層
23c: パッド部
24: 第2引出電極
24c: パッド部
26: 保護膜
30: 薄型複合素子
31: 絶縁基板
32: 薄膜サーミスタ
33,34: 一対の櫛型電極
36: 薄膜抵抗
37: 接続層
37a: 接合層
37b: 導電層
38: 第3引出電極
38a: 接合層
38b: 導電層
38c: パッド部
39: 第4引出電極
39c: パッド部
41: 下部電極
41a: 接合層
41b: 導電層
42: 保護膜
43: 上部電極
43a: 接合層
43b: 導電層
44: 薄膜コンデンサ
10: Thin composite element 11: Insulating substrate 12: Thin film thermistor 13, 14: A pair of comb electrodes 16: Thin film resistor 17: Lower electrode 17a: Bonding layer 17b: Conductive layer 17c: Pad portion 18: Dielectric layer 19: Upper portion Electrode 21: Thin film capacitor 22: Connection layer 23: First extraction electrode 23a: Bonding layer 23b: Conductive layer 23c: Pad part 24: Second extraction electrode 24c: Pad part 26: Protective film 30: Thin composite element 31: Insulating substrate 32: Thin film thermistor 33, 34: A pair of comb-shaped electrodes 36: Thin film resistor 37: Connection layer 37a: Bonding layer 37b: Conductive layer 38: Third extraction electrode 38a: Bonding layer 38b: Conductive layer 38c: Pad portion 39: First 4 extraction electrode 39c: pad part 41: lower electrode 41a: bonding layer 41b: conductive layer 42: protective film 43: upper electrode 3a: bonding layer 43 b: conductive layer 44: thin-film capacitor

Claims (16)

絶縁基板上に薄膜サーミスタと薄膜抵抗と薄膜コンデンサとが互いに離間して形成され、
前記薄膜サーミスタ上に相対向する一対の櫛型電極が形成され、
前記薄膜コンデンサが前記基板上に形成された下部電極と前記下部電極上に形成された誘電体層と前記誘電体層上に形成された上部電極とにより構成され、
前記基板上に前記一対の櫛型電極の一方と前記薄膜抵抗の一端と前記上部電極又は下部電極の一端とを互いに電気的に接続するように接続層が形成され、
前記基板上に前記一対の櫛型電極の他方に電気的に接続するように第1引出電極が形成され、
前記基板上に前記薄膜抵抗の他端に電気的に接続するように第2引出電極が形成され、
前記下部電極又は上部電極、前記第1引出電極及び前記第2引出電極における引出線を接続するためのパッド部を除いた前記基板上のすべての素子を被覆するように保護膜が形成された
ことを特徴とする薄型複合素子。
A thin film thermistor, a thin film resistor, and a thin film capacitor are formed on an insulating substrate and separated from each other.
A pair of comb electrodes facing each other is formed on the thin film thermistor,
The thin film capacitor includes a lower electrode formed on the substrate, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer,
A connection layer is formed on the substrate so as to electrically connect one of the pair of comb electrodes, one end of the thin film resistor, and one end of the upper electrode or the lower electrode,
A first extraction electrode is formed on the substrate so as to be electrically connected to the other of the pair of comb electrodes;
A second extraction electrode is formed on the substrate to be electrically connected to the other end of the thin film resistor;
A protective film is formed so as to cover all the elements on the substrate except the pad portion for connecting the lead lines in the lower electrode or the upper electrode, the first lead electrode, and the second lead electrode. A thin composite element.
絶縁基板が、セラミック基板、ガラス基板又は基板上面に絶縁膜を有するシリコン基板である請求項1記載の薄型複合素子。   2. The thin composite element according to claim 1, wherein the insulating substrate is a ceramic substrate, a glass substrate, or a silicon substrate having an insulating film on the upper surface of the substrate. 絶縁基板が基板上面に絶縁膜を有するシリコン基板であって、薄膜サーミスタの下方に前記絶縁膜を残して前記シリコン基板の空洞又は凹部が形成された請求項1又は2記載の薄型複合素子。   3. The thin composite element according to claim 1, wherein the insulating substrate is a silicon substrate having an insulating film on the upper surface of the substrate, and the cavity or recess of the silicon substrate is formed leaving the insulating film below the thin film thermistor. 下部電極、接続層、第1引出電極及び第2引出電極が、絶縁基板上に成膜された接合層と前記接合層上に前記接合層と同形同大に成膜された導電層とによりそれぞれ構成された請求項1ないし3いずれか1項に記載の薄型複合素子。   A lower electrode, a connection layer, a first extraction electrode, and a second extraction electrode are formed of a bonding layer formed on an insulating substrate and a conductive layer formed on the bonding layer in the same shape and size as the bonding layer. The thin composite element according to any one of claims 1 to 3, each configured. 絶縁基板上に薄膜サーミスタと薄膜抵抗と薄膜コンデンサ用下部電極とが互いに離間して形成され、
前記薄膜サーミスタ上に相対向する一対の櫛型電極が形成され、
前記基板上に前記一対の櫛型電極の一方と前記薄膜抵抗の一端と前記下部電極の一端とを互いに電気的に接続するように接続層が形成され、
前記基板上に前記一対の櫛型電極の他方に電気的に接続するように第3引出電極が形成され、
前記基板上に前記薄膜抵抗の他端に電気的に接続するように第4引出電極が形成され、
前記第3及び第4引出電極における引出線を接続するためのパッド部を除いた前記基板上のすべての素子を被覆するようにSiO2からなる保護膜が形成され、
前記保護膜を介して前記下部電極上に薄膜コンデンサ用上部電極が形成され、
前記下部電極と前記保護膜と前記上部電極により薄膜コンデンサを構成したことを特徴とする薄型複合素子。
A thin film thermistor, a thin film resistor, and a lower electrode for a thin film capacitor are formed on an insulating substrate so as to be separated from each other.
A pair of comb electrodes facing each other is formed on the thin film thermistor,
A connection layer is formed on the substrate so as to electrically connect one of the pair of comb electrodes, one end of the thin film resistor, and one end of the lower electrode,
A third extraction electrode is formed on the substrate so as to be electrically connected to the other of the pair of comb electrodes;
A fourth extraction electrode is formed on the substrate to be electrically connected to the other end of the thin film resistor;
A protective film made of SiO 2 is formed so as to cover all the elements on the substrate except the pad portion for connecting the lead lines in the third and fourth lead electrodes;
An upper electrode for a thin film capacitor is formed on the lower electrode through the protective film,
A thin composite element comprising a thin film capacitor composed of the lower electrode, the protective film, and the upper electrode.
絶縁基板が、セラミック基板、ガラス基板又は基板上面に絶縁膜を有するシリコン基板である請求項5記載の薄型複合素子。   6. The thin composite element according to claim 5, wherein the insulating substrate is a ceramic substrate, a glass substrate, or a silicon substrate having an insulating film on the upper surface of the substrate. 絶縁基板が基板上面に絶縁膜を有するシリコン基板であって、薄膜サーミスタの下方に前記絶縁膜を残して前記シリコン基板の空洞又は凹部が形成された請求項5又は6記載の薄型複合素子。   The thin composite element according to claim 5 or 6, wherein the insulating substrate is a silicon substrate having an insulating film on the upper surface of the substrate, and the cavity or recess of the silicon substrate is formed leaving the insulating film below the thin film thermistor. 下部電極、接続層、第3引出電極及び第4引出電極が、絶縁基板上に成膜された接合層と前記接合層上に前記接合層と同形同大に成膜された導電層とによりそれぞれ構成された請求項5ないし7いずれか1項に記載の薄型複合素子。   The lower electrode, the connection layer, the third extraction electrode, and the fourth extraction electrode are formed of a bonding layer formed on an insulating substrate and a conductive layer formed on the bonding layer in the same shape and size as the bonding layer. The thin composite element according to any one of claims 5 to 7, each configured. 絶縁基板上に所定のパターンで薄膜コンデンサ用下部電極を形成する工程と、
前記下部電極の上に誘電体層を形成する工程と、
前記基板上に前記下部電極とは別に所定のパターンで薄膜サーミスタを形成する工程と、
前記基板上に前記下部電極及び前記薄膜サーミスタとは別に所定のパターンで薄膜抵抗を形成する工程と、
前記薄膜サーミスタ上に相対向する一対の櫛型電極を形成するとともに前記誘電体層上に薄膜コンデンサ用上部電極を形成する工程と、
前記基板上に前記一対の櫛型電極の一方と前記薄膜抵抗の一端と前記上部電極又は下部電極の一端とを互いに電気的に接続するように接続層を形成する工程と、
前記基板上に前記一対の櫛型電極の他方に電気的に接続するように第1引出電極を形成する工程と、
前記基板上に前記薄膜抵抗の他端に電気的に接続するように第2引出電極を形成する工程と、
前記下部電極又は上部電極、前記第1引出電極及び前記第2引出電極における引出線を接続するためのパッド部を除いた前記基板上のすべての素子を被覆するように保護膜を形成する工程と
を含む薄型複合素子の製造方法。
Forming a lower electrode for a thin film capacitor in a predetermined pattern on an insulating substrate;
Forming a dielectric layer on the lower electrode;
Forming a thin film thermistor in a predetermined pattern separately from the lower electrode on the substrate;
Forming a thin film resistor in a predetermined pattern separately from the lower electrode and the thin film thermistor on the substrate;
Forming a pair of opposing comb electrodes on the thin film thermistor and forming an upper electrode for the thin film capacitor on the dielectric layer;
Forming a connection layer on the substrate so as to electrically connect one of the pair of comb electrodes, one end of the thin film resistor, and one end of the upper electrode or the lower electrode;
Forming a first extraction electrode on the substrate so as to be electrically connected to the other of the pair of comb electrodes;
Forming a second extraction electrode on the substrate so as to be electrically connected to the other end of the thin film resistor;
Forming a protective film so as to cover all the elements on the substrate except for a pad portion for connecting lead lines in the lower electrode or the upper electrode, the first lead electrode, and the second lead electrode; A method for manufacturing a thin composite element including:
絶縁基板が、セラミック基板、ガラス基板又は基板上面に絶縁膜を有するシリコン基板である請求項9記載の薄型複合素子の製造方法。   The method for manufacturing a thin composite element according to claim 9, wherein the insulating substrate is a ceramic substrate, a glass substrate, or a silicon substrate having an insulating film on an upper surface of the substrate. 絶縁基板が基板上面に絶縁膜を有するシリコン基板であって、薄膜サーミスタの下方に前記絶縁膜をエッチングストッパとしてエッチングにより前記シリコン基板の空洞又は凹部を形成する請求項9又は10記載の薄型複合素子の製造方法。   The thin composite element according to claim 9 or 10, wherein the insulating substrate is a silicon substrate having an insulating film on an upper surface of the substrate, and a cavity or a recess of the silicon substrate is formed by etching using the insulating film as an etching stopper below the thin film thermistor. Manufacturing method. 下部電極、接続層、第1引出電極及び第2引出電極が、絶縁基板上に接合層を成膜した後、前記接合層上に前記接合層と同形同大に導電層を成膜することにより構成される請求項9ないし11いずれか1項に記載の薄型複合素子の製造方法。   After the lower electrode, the connection layer, the first extraction electrode, and the second extraction electrode form a bonding layer on the insulating substrate, a conductive layer having the same shape and size as the bonding layer is formed on the bonding layer. The manufacturing method of the thin composite element of any one of Claims 9 thru | or 11 comprised by these. 絶縁基板上に所定のパターンで薄膜サーミスタを形成する工程と、
前記基板上に所定のパターンで前記薄膜サーミスタとは別に薄膜抵抗を形成する工程と、
前記薄膜サーミスタ上に相対向する一対の櫛型電極を形成する工程と、
前記基板上に前記一対の櫛型電極の一方と前記薄膜抵抗の一端とを互いに電気的に接続するように接続層を形成する工程と、
前記基板上に前記一対の櫛型電極の他方に電気的に接続するように第3引出電極を形成する工程と、
前記基板上に前記薄膜抵抗の他端に電気的に接続するように第4引出電極を形成する工程と、
前記基板上に前記接続層に電気的に接続するように薄膜コンデンサ用下部電極を形成する工程と、
前記第3及び第4引出電極における引出線を接続するためのパッド部を除いた前記基板上のすべての素子を被覆するようにSiO2からなる保護膜を形成する工程と、
前記保護膜を介して前記下部電極上に薄膜コンデンサ用上部電極を形成する工程とを含む薄型複合素子の製造方法。
Forming a thin film thermistor in a predetermined pattern on an insulating substrate;
Forming a thin film resistor separately from the thin film thermistor in a predetermined pattern on the substrate;
Forming a pair of opposing comb electrodes on the thin film thermistor;
Forming a connection layer on the substrate so as to electrically connect one of the pair of comb electrodes and one end of the thin film resistor;
Forming a third extraction electrode on the substrate so as to be electrically connected to the other of the pair of comb electrodes;
Forming a fourth extraction electrode on the substrate so as to be electrically connected to the other end of the thin film resistor;
Forming a lower electrode for a thin film capacitor so as to be electrically connected to the connection layer on the substrate;
Forming a protective film made of SiO 2 so as to cover all elements on the substrate except for the pad portion for connecting the lead lines in the third and fourth lead electrodes;
Forming a thin film capacitor upper electrode on the lower electrode through the protective film.
絶縁基板が、セラミック基板、ガラス基板又は基板上面に絶縁膜を有するシリコン基板である請求項13記載の薄型複合素子の製造方法。   The method for producing a thin composite element according to claim 13, wherein the insulating substrate is a ceramic substrate, a glass substrate, or a silicon substrate having an insulating film on an upper surface of the substrate. 絶縁基板が基板上面に絶縁膜を有するシリコン基板であって、薄膜サーミスタの下方に前記絶縁膜をエッチングストッパとしてエッチングにより前記シリコン基板の空洞又は凹部を形成する請求項13又は14記載の薄型複合素子の製造方法。   15. The thin composite element according to claim 13, wherein the insulating substrate is a silicon substrate having an insulating film on the upper surface of the substrate, and a cavity or a recess of the silicon substrate is formed by etching using the insulating film as an etching stopper below the thin film thermistor. Manufacturing method. 下部電極、接続層、第3引出電極及び第4引出電極が、絶縁基板上に接合層を成膜した後、前記接合層上に前記接合層と同形同大に導電層を成膜することにより構成される請求項13ないし15いずれか1項に記載の薄型複合素子の製造方法。   After the lower electrode, the connection layer, the third extraction electrode, and the fourth extraction electrode form a bonding layer on the insulating substrate, a conductive layer having the same shape and size as the bonding layer is formed on the bonding layer. The method for manufacturing a thin composite element according to claim 13, comprising:
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