JP2008251571A - Method and program for designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for designing a semiconductor integrated circuit in which the optimal resistance of the resistance element in a decoupling capacitor with a resistor being inserted between power supply lines in order to stabilize the power supply voltage can be calculated automatically. <P>SOLUTION: A first resonance frequency fa dependent on the combined resistance of the resistance components 32A and 32B of power supply lines, the combined inductance of the inductor components 33A and 33B and the value C1 of a capacitance 34 between the power supply lines, and a second resonance frequency fb dependent on the combined resistance of the resistance components 32A and 32B of the power supply lines, the combined inductance of the inductor components 33A and 33B, the value C1 of the capacitance 34 between the power supply lines, and the value C2 of a decoupling capacitor 35 with a resistor are calculated. A value equal to the impedance of a capacitor 36 in the decoupling capacitor 35 with a resistor at the average value (fa+fb)/2 of the first resonance frequency fa and the second resonance frequency fb is calculated as the optimal resistance of the resistance element 37 in the decoupling capacitor 35 with a resistor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a design method and a design program for a semiconductor integrated circuit suitable for use in designing a semiconductor integrated circuit in which a decoupling capacitor with a resistor is connected between power supply wirings having different voltages.

  In a semiconductor integrated circuit, the scale-up and speeding-up are achieved with the miniaturization. When a semiconductor integrated circuit is scaled up and speeded up, its operating current contains a lot of high frequency components. When this operating current flows through the power supply wiring having impedance, the power supply voltage fluctuates in accordance with the current amplitude and frequency.

  If the power supply voltage fluctuates greatly during the operation of the internal circuit, the internal circuit may cause a variation in delay time or erroneous logic recognition. As a result, such a semiconductor integrated circuit malfunctions. Therefore, in the semiconductor integrated circuit, it is necessary to suppress fluctuations in the power supply voltage during the operation of the internal circuit.

  Here, if the impedance of the power supply wiring system of the semiconductor integrated circuit can be lowered from direct current to high frequency, fluctuations in the power supply voltage due to the high frequency component of the operating current can be reduced. Therefore, the power supply wiring system is desired to have a low impedance regardless of the operating state of the internal circuit.

  One technique for reducing the impedance of the power supply wiring system is to use a decoupling capacitor. A decoupling capacitor is a capacitor inserted between power supply wirings having different voltages for the purpose of stabilizing the power supply voltage, and has a function of lowering the impedance of the power supply wiring system with respect to an alternating current. In some cases, the parasitic capacitance of the power supply wiring in the semiconductor integrated circuit also functions in the same manner as the decoupling capacitor.

Here, the impedance Z _C of the capacitor is expressed as Z _C = 1 / j2πfC, where C [F] is the capacitance value of the capacitor and f [Hz] is the frequency of the current flowing through the capacitor. Therefore, when using a decoupling capacitor, the higher the current frequency, the higher the impedance reduction effect of the power supply wiring system.

  In many semiconductor integrated circuit layouts, the required amount of decoupling capacitors is intentionally placed in advance, then the rest of the circuits are placed, or decoupling capacitors are placed in the free space after the layout of the semiconductor integrated circuit. In some cases, the impedance of the power supply wiring system is reduced.

  Another method for reducing the impedance of the power supply wiring system is to increase the width of the power supply wiring. In this method, the impedance of the power supply wiring system is reduced and made uniform by multilayering the power supply wiring of the semiconductor integrated circuit or by making it mesh. Furthermore, the impedance of the power supply wiring system is lowered by providing a plurality of electrodes for connecting to the package electrodes on the die and using a plurality of wires for connection with the package electrodes.

Here, the impedance Z _L of the inductor is expressed as Z _L = j2πfL where _L is the inductance of the inductor and f is the frequency of the current flowing through the inductor. Therefore, lowering the impedance of the power supply wiring system by increasing the width of the power supply wiring is a sufficient technique for reducing the impedance of the power supply with respect to the direct current, but for alternating current, particularly for currents containing a lot of high frequency components. The impedance increases due to the inductor component of the power supply wiring.

  By the way, the impedance reduction technique for the power supply wiring system using a decoupling capacitor and the power impedance reduction technique for the power supply wiring system by increasing the width of the power supply wiring are generally used simultaneously in the layout of the semiconductor integrated circuit. In recent large-scale and high-speed operation semiconductor integrated circuits, there have been cases where malfunctions occur in the semiconductor integrated circuits even if these methods for reducing the impedance of the power supply wiring system are used.

  This includes the resistance component, inductor component, and parasitic capacitance of the power supply wiring including the package (power supply wiring in the semiconductor integrated circuit, bonding wire between the semiconductor integrated circuit and the package, and power supply wiring in the interposer constituting the package). This is because the power supply voltage largely fluctuates due to resonance by the RLC resonance circuit system constituted by the decoupling capacitor connected between the power supply wirings. This will be described below with reference to FIG.

  FIG. 8 is an equivalent circuit diagram of the power supply wiring system as seen from the semiconductor integrated circuit incorporated in the package. In FIG. 8, 1 is an external power supply, 2A and 2B are resistance components of the power supply wiring including the package, 3A and 3B are inductor components of the power supply wiring including the package, and 4 is a capacitance between the power supply wirings. 4 includes the parasitic capacitance of the power supply wiring and the capacitance of the decoupling capacitor intentionally inserted between the power supply wirings.

  Here, if the combined resistance value of the resistance components 2A and 2B of the power supply wiring is R, the combined inductance of the inductor components 3A and 3B of the power supply wiring is L, and the capacitance value of the capacitor 4 is C, the power supply wiring system shown in FIG. Fr = 1 / 2π√LC, and the Q value at the time of resonance is Q = 2πfrL / R. In the power supply wiring system of the semiconductor integrated circuit incorporated in the package, In many cases, the Q value has a high value. This is because the semiconductor integrated circuit is designed so that the impedance of the power supply wiring system is particularly small with respect to the direct current.

  As described above, the reason why the impedance of the power supply wiring system is reduced with respect to the direct current is that if the impedance of the power supply wiring system is large with respect to the direct current, the voltage drop in the power supply wiring is increased. In addition to the fact that the voltage of the external power supply of the semiconductor integrated circuit and the voltage actually applied to the semiconductor integrated circuit are different, the current flowing in the power supply wiring varies depending on the operating state of the semiconductor integrated circuit. This is because the voltage applied to the capacitor fluctuates, causing malfunction of the semiconductor integrated circuit.

  There is also a method of shifting the resonance frequency as a countermeasure against resonance of the power supply wiring system of the semiconductor integrated circuit incorporated in the package. This technique is applied to a package so that the Q value becomes sufficiently small in the vicinity of the inherent operating current frequency of the semiconductor integrated circuit and the noise current frequency superimposed on the power supply wiring on the printed circuit board outside the semiconductor integrated circuit. The resonance frequency of the power supply wiring system of the integrated semiconductor integrated circuit is adjusted. Specifically, the combined inductance L of the inductor components 3A and 3B and the capacitance value C of the capacitor 4 are changed.

  However, with this method, the Q value at the resonance frequency after shifting the resonance frequency may be higher than the Q value at the original resonance frequency. This is a case where the combined inductance L of the inductor components 3A and 3B of the power supply wiring is increased or the capacitance value C of the capacitor 4 between the power supply wirings is reduced.

  Conversely, if the combined inductance L of the inductor components 3A and 3B of the power supply wiring can be reduced and the capacitance value C of the capacitor 4 between the power supply wirings can be increased, the Q value can be lowered to some extent along with the shift of the resonance frequency. The Q value reduction effect is small. For example, in order to halve the Q value, assuming that the combined resistance value R of the resistance components 2A and 2B and the combined inductance L of the inductor components 3A and 3B are constant values, the capacitance value of the capacitor 4 between the power supply wires C must be 4 times the original value. This means a significant increase in the area of the semiconductor integrated circuit, which is not realistic in terms of the cost of the semiconductor integrated circuit.

  Further, if the combined resistance value R of the resistance components 2A and 2B of the power supply wiring and the capacitance value C of the capacitor 4 between the power supply wirings can be made constant and the combined inductance L of the inductor components 3A and 3B of the power supply wiring can be reduced, For example, if the combined inductance L can be reduced to 0.25 times the original value, the Q value can be halved, but the power supply wiring can be greatly increased, the number of bonding wires can be increased, and the width of the interposer wiring can be increased. Multilayering is necessary, which is also not practical in terms of cost.

  Therefore, conventionally, as a technique for reducing the Q value of the power supply wiring system of the semiconductor integrated circuit incorporated in the package in an area-efficient manner, a method using a decoupling capacitor with a resistor has been proposed. For example, Patent Document 1 discloses a Q value reduction circuit for a power supply wiring system using a decoupling capacitor in which resistance elements are connected in series, that is, a so-called resistance decoupling capacitor.

  FIG. 9 is a diagram showing a Q value reduction circuit of the power supply wiring system proposed by Patent Document 1. In FIG. In FIG. 9, 11 is a power supply, 12A and 12B are inductor components of the power supply wiring, 13 is a decoupling capacitor in which resistance elements are not connected in series, so-called decoupling capacitor without resistance, 14 is a decoupling capacitor with resistance, and 15 is resistance. A capacitor constituting the attached decoupling capacitor 14, 16 a resistance element constituting the resistor decoupling capacitor 14, and 17 an electronic circuit element.

In this power supply wiring system Q value reduction circuit, a decoupling capacitor 14 with a resistor is connected between power supply wirings of different voltages, and the resistance element 16 constituting the decoupling capacitor 14 functions as a damping resistor, thereby allowing the Q of the power supply wiring system to function. The value is reduced.
JP-A-6-132668

  According to Patent Document 1, the resistance value of the resistive element 16 is selected to be sufficiently lower than the impedance of the resonance peak of the power supply wiring system when the resistive element 16 is not connected. A specific method for determining the resistance value of 16 is not shown. According to the knowledge of the present inventor, the resistance value of the resistance element 16 has an optimum value, and a sufficient Q value reduction effect in the power supply wiring system can be obtained regardless of whether the resistance value of the resistance element 16 is too high or too low. Can't get. This will be described below with reference to FIG.

  FIG. 10 is a diagram showing an equivalent circuit of a power supply wiring system used for studying an optimum resistance value of a resistance element constituting a decoupling capacitor with a resistance inserted between power supply wirings, and a semiconductor integrated circuit incorporated in a package An equivalent circuit of a power supply wiring system viewed from (a semiconductor integrated circuit in which a decoupling capacitor with a resistor is inserted between power supply wirings) is shown.

  In FIG. 10, 21 is an external power supply, 22A and 22B are resistance components of the power supply wiring including the package, 23A and 23B are inductor components of the power supply wiring including the package, and 24 is a capacitance between the power supply wirings. 24 includes the parasitic capacitance of the power supply wiring and the capacity of the decoupling capacitor intentionally inserted between the power supply wirings. Reference numeral 25 denotes a decoupling capacitor with resistance inserted between power supply wirings, 26 denotes a capacitor constituting the decoupling capacitor 25 with resistance, and 27 denotes a resistance element constituting the decoupling capacitor 25 with resistance.

  FIG. 11 is a diagram showing the relationship between the resonance frequency fr and the Q value of the power supply wiring system shown in FIG. 10, and is obtained by a circuit simulator. In this example, the combined resistance value of the resistance components 22A and 22B is 250 mΩ, the combined inductance of the inductor components 23A and 23B is 10 nH, the capacitance value of the capacitor 24 is 0.8 nF, and the capacitance value of the capacitor 26 is 0.2 nF. 27 shows a case where the resistance value Rd of 27 is changed.

  As can be seen from FIG. 11, the resistance value Rd of the resistance element 27 is too high or too low, the effect of reducing the Q value is low. In this example, an optimum value is about 16Ω as the resistance value Rd of the resistance element 27. In this case, the Q value does not use the decoupling capacitor 25 with resistance but uses a decoupling capacitor without resistance, that is, resistance. Compared with the case where the resistance value Rd of the element 27 is 0Ω, it is reduced from 12.6 to 5.39. In this case, the resonance frequency fr is 52.7 MHz.

  If an attempt is made to realize the same Q value reduction effect by merely increasing the decoupling capacitor without resistance without using the decoupling capacitor 25 with resistance, about 5 nF is required as the capacitance value, and the original capacitance value (capacitance of 24) 5 times as large as (capacitance value + capacitance value of capacitor 26). Naturally, in order to realize this, the area of the semiconductor integrated circuit must be greatly increased.

  From the above, it can be said that the Q value reduction method of the power supply wiring system in the semiconductor integrated circuit using the decoupling capacitor with resistance is a method with good area efficiency, but the resistance value of the resistance element constituting the resistance decoupling capacitor is It can be seen that there is an optimum value in the decision, and that this must be taken into account when designing.

  In view of this point, the present invention can automatically calculate the optimum resistance value of a resistance element that constitutes a decoupling capacitor with a resistance inserted between power supply wirings having different voltages in a semiconductor integrated circuit to stabilize the power supply voltage. An object of the present invention is to provide a design method and a design program for a semiconductor integrated circuit.

  In the present invention, the first invention is a method for designing a semiconductor integrated circuit in which a decoupling capacitor without resistance and a decoupling capacitor with resistance are connected between power supply lines, wherein the first calculation means includes a resistance of the power supply line. A first resonance frequency determined by a component, an inductor component and a parasitic capacitance, and the decoupling capacitor without resistance, a resistance component of the power supply wiring, an inductor component and a parasitic capacitance, the decoupling capacitor without resistance, and the decoupling with resistance A step of calculating a second resonance frequency determined by a capacitor constituting the ring capacitor, and a second calculation means calculates an average value of the first resonance frequency and the second resonance frequency, and the average A value equal to the impedance of the capacitor constituting the resistor decoupling capacitor in value It is intended to include a step of calculating an optimum resistance value of the resistance elements constituting the resistance with decoupling capacitors.

  In the present invention, the second invention is a program for designing a semiconductor integrated circuit in which a decoupling capacitor without resistance and a decoupling capacitor with resistance are connected between power supply wires, the computer comprising a resistance component of the power supply wire, an inductor A first resonance frequency determined by a component and a parasitic capacitance, and the decoupling capacitor without resistance, a resistance component of the power supply wiring, an inductor component and a parasitic capacitance, and the decoupling capacitor without resistance and the decoupling capacitor with resistance A first calculating means for calculating a second resonance frequency determined by a capacitor to be configured; and an average value of the first resonance frequency and the second resonance frequency is calculated, and the resistance is added to the average value. A value equal to the impedance of the capacitor that makes up the decoupling capacitor It is intended to include a program to function as a second calculating means for calculating the optimum resistance of the resistor constituting the decoupling capacitor with the resistor.

  According to the present invention, the resistance element of the decoupling capacitor with a resistor inserted for stabilizing the power supply voltage between the power supply wirings having different voltages in the semiconductor integrated circuit by the first calculation means and the second calculation means. The optimum resistance value can be automatically calculated.

  FIG. 1 is an equivalent circuit diagram of a power supply wiring system as seen from a semiconductor integrated circuit to which an embodiment of a semiconductor integrated circuit design method of the present invention is applied. In FIG. 1, 31 is an external power supply, 32A and 32B are power supply wirings including a package (power supply wiring in the semiconductor integrated circuit, bonding wires between the semiconductor integrated circuit and the package, and power supply wiring in the interposer constituting the package). A resistance component, 33A and 33B are inductor components of the power supply wiring including the package, and 34 is a capacitance between the power supply wirings. The capacitance 34 between the power supply wirings is intentionally inserted between the parasitic capacitance of the power supply wiring and the power supply wiring. The capacitance of the decoupling capacitor is included.

  Reference numeral 35 denotes a resistor decoupling capacitor inserted between power supply wirings in the semiconductor integrated circuit, 36 denotes a capacitor constituting the resistor decoupling capacitor 35, and 37 denotes a resistor element constituting the resistor decoupling capacitor 35. . One embodiment of the method for designing a semiconductor integrated circuit of the present invention includes a step of automatically calculating the resistance value of the resistance element 37 constituting the decoupling capacitor 35 with resistance.

  FIG. 2 is a functional block diagram of a computer system for carrying out an embodiment of the semiconductor integrated circuit design method of the present invention. In FIG. 2, 41 is a first resonance frequency calculation means, 42 is a second resonance frequency calculation means, 43 is a resonance frequency average value calculation means, 44 is an optimum resistance value calculation means, and 45 is a storage means.

  The storage means 45 includes the combined resistance value R of the resistance components 32A and 32B of the power supply wiring of the power supply wiring system shown in FIG. 1, the combined inductance L of the inductor components 33A and 33B of the power supply wiring, and the capacitance value of the capacitor 34 between the power supply wirings. C1 and the capacitance value C2 of the capacitor 36 constituting the decoupling capacitor 35 with resistance are stored.

  The first resonance frequency calculation means 41 is the resonance frequency when the resistance decoupling capacitor 35 is not inserted in the power supply wiring system shown in FIG. 1, that is, the combined resistance value R of the resistance components 32A and 32B of the power supply wiring, A first resonance frequency fa determined by the combined inductance L of the inductor components 33A and 33B of the power supply wiring and the capacitance value C1 of the capacitor 34 between the power supply wirings is calculated. The first resonance frequency fa is stored in the storage means 45.

  The second resonance frequency calculating means 42 is the resonance frequency when the resistance value of the resistance element 37 is 0, that is, the combined resistance value R of the resistance components 32A and 32B of the power supply wiring, for the power supply wiring system shown in FIG. The second resonance frequency determined by the combined inductance L of the inductor components 33A and 33B of the power supply wiring, the capacitance value C1 of the capacitor 34 between the power supply wirings, and the capacitance value C2 of the capacitor 36 constituting the resistor decoupling capacitor 35 fb is calculated, and the second resonance frequency fb calculated by the second resonance frequency calculation means 42 is stored in the storage means 45.

  The resonance frequency average value calculation means 43 is an average value of the first resonance frequency fa calculated by the first resonance frequency calculation means 41 and the second resonance frequency fb calculated by the second resonance frequency calculation means 42 ( fa + fb) / 2, and the average value (fa + fb) / 2 of the first resonance frequency fa and the second resonance frequency fb calculated by the resonance frequency average value calculation means 43 is stored in the storage means 45. .

  The optimum resistance value calculation means 44 is a capacitor constituting the decoupling capacitor 35 with resistance at the average value (fa + fb) / 2 of the first resonance frequency fa and the second resonance frequency fb calculated by the resonance frequency average value calculation means 43. A value equal to the impedance of 36 is calculated as the optimum resistance value of the resistance element 37 constituting the decoupling capacitor 35 with resistance.

  That is, in one embodiment of the method for designing a semiconductor integrated circuit of the present invention, first, the first resonance frequency calculation means 41 uses the combined resistance value of the resistance components 32A and 32B of the power supply wiring for the power supply wiring system shown in FIG. A first resonance frequency fa determined by R, the combined inductance L of the inductor components 33A and 33B of the power supply wiring, and the capacitance value C1 of the capacitor 34 between the power supply wirings is calculated.

  Next, the second resonance frequency calculation means 42 uses the combined resistance value R of the resistance components 32A and 32B of the power supply wiring and the combined inductance L of the inductor components 33A and 33B of the power supply wiring for the power supply wiring system shown in FIG. Then, the second resonance frequency fb determined by the capacitance value C1 of the capacitor 34 between the power supply wires and the capacitance value C2 of the capacitor 36 constituting the decoupling capacitor 35 with resistance is calculated.

  Next, the first resonance frequency fa calculated by the first resonance frequency calculation means 41 and the second resonance frequency fb calculated by the second resonance frequency calculation means 42 by the resonance frequency average value calculation means 43. An average value (fa + fb) / 2 is calculated.

  Next, the decoupling capacitor 35 with resistance at the average value (fa + fb) / 2 of the first resonance frequency fa and the second resonance frequency fb calculated by the resonance frequency average value calculation means 43 is obtained by the optimum resistance value calculation means 44. A value equal to the impedance of the constituting capacitor 36 is calculated as the optimum resistance value of the resistance element 37 constituting the resistor decoupling capacitor 35.

  Here, a value equal to the impedance of the capacitor 36 constituting the resistor decoupling capacitor 35 at the average value (fa + fb) / 2 of the first resonance frequency fa and the second resonance frequency fb is applied to the resistor decoupling capacitor 35. It will be described with reference to FIG. 10 and FIG.

  FIG. 11 shows that the combined resistance value of the resistance components 22A and 22B is 250 mΩ, the combined inductance of the inductor components 23A and 23B is 10 nH, the capacitance value of the capacitor 24 is 0.8 nF, and the capacitance value of the capacitor 26 is 0.2 nF. The simulation result of the relationship between the resonance frequency fr and the Q value when the resistance value Rd of the resistance element 27 is changed is shown.

  According to this simulation result, when the resistance value Rd of the resistance element 27 is changed, the Q value due to the resonance of the circuit is most reduced when the frequency is 52.7 MHz. The resistance value Rd of 27 is about 16Ω.

  When the optimum resistance value of the resistance element 27 is calculated according to an embodiment of the semiconductor integrated circuit design method of the present invention, first, the first resonance frequency fa is calculated by the first resonance frequency calculation means 41. However, fa = 1 / 2π√ (LC) = 1 / 2π√ (10 [nH] × 0.8 [nF]) = 56.4 MHz.

  Next, the second resonance frequency calculation means 42 calculates the second resonance frequency fb. Fb = 1 / 2π√ (LC) = 1 / 2π√ (10 [nH] × 1 [nF ]) = 50 MHz.

  Next, the average value (fa + fb) / 2 of the first resonance frequency fa and the second resonance frequency fb is calculated by the resonance frequency average value calculating means 43, but (fa + fb) / 2 = (56. 4 MHz + 50 MHz) /2=53.2 MHz.

  Next, the optimum resistance value calculating means 44 calculates the impedance | Zc | of the capacitor 26 at the frequency (fa + fb) /2=53.2 MHz. | Zc | = 1 / 2πfC = 1 / 2π × 53 0.2 [MHz] × 0.2 [nF] = 15Ω.

  Thus, according to one embodiment of the method for designing a semiconductor integrated circuit of the present invention, the optimum resistance value of the resistance element 27 is 15Ω, which is a number that is quite close to the calculation result by the simulation result shown in FIG. The Q value at that time has a small error from the simulation result. Therefore, according to the embodiment of the method for designing a semiconductor integrated circuit of the present invention, the optimum resistance value can be calculated also for the resistance element 37 constituting the decoupling capacitor 35 with resistance.

  In one embodiment of the semiconductor integrated circuit design method of the present invention, the first resonance frequency calculation means 41 and the second resonance frequency calculation means 42 constitute the first calculation means, and the resonance frequency average value calculation. The means 43 and the resistance value calculating means 44 constitute a second calculating means. However, either the calculation of the first resonance frequency fa by the first resonance frequency calculation means 41 or the calculation of the second resonance frequency fb by the second resonance frequency calculation means 42 may be executed first.

  FIG. 3 is a schematic configuration diagram of a computer system for carrying out an embodiment of the method for designing a semiconductor integrated circuit of the present invention. In FIG. 3, 51 is a central processing unit (CPU), 52 is a read only memory (ROM), 53 is a random access memory (RAM), 54 is an input device such as a keyboard or mouse, 55 is an output device such as a display or printer. , 56 is a communication device for communicating with an external device, 57 is a hard disk device (HDD), and 58 is a hard disk driven by the hard disk device 57.

  The hard disk 58 includes an embodiment 59 of a semiconductor integrated circuit design program according to the present invention, circuit constant information 60 of the power supply wiring system shown in FIG. 1 (the combined resistance value R of the resistance components 32A and 32B of the power supply wiring, the power supply It is used to store the combined inductance L of the wiring inductor components 33A and 33B, the capacitance value C1 of the capacitor 34 between the power supply wires, the capacitance value C2 of the capacitor 36 constituting the decoupling capacitor 35 with resistance, and the like.

  The embodiment 59 of the semiconductor integrated circuit design program of the present invention includes a first resonance frequency calculation program 61, a second resonance frequency calculation program 62, a resonance frequency average value calculation program 63, and an optimum resistance value calculation program 64. Is included.

  The first resonance frequency calculation program 61 causes the CPU 51 to function as the first resonance frequency calculation means 41. The second resonance frequency calculation program 62 causes the CPU 52 to function as the second resonance frequency calculation means 42. The resonance frequency average value calculation program 63 causes the CPU 51 to function as the resonance frequency average value calculation means 43. The optimum resistance value calculation program 64 causes the CPU 51 to function as the optimum resistance value calculation means 44.

  FIG. 4 is a conceptual diagram for explaining an example of a semiconductor integrated circuit in which an embodiment of the semiconductor integrated circuit design method of the present invention is used. In FIG. 4, reference numeral 71 denotes a semiconductor integrated circuit die, 72 denotes a circuit disposed on the die 71, and a circuit in which a power source is separated from other circuits. Normally, such a circuit 72 is called a macro, and corresponds to, for example, a PLL (phase locked loop), an AD (analog / digital) converter, a DA (digital / analog) converter, or the like. 73 is a bonding wire of the package, and 74 is a power supply wiring in the interposer of the package.

  One embodiment of the semiconductor integrated circuit design method of the present invention can be used when designing the macro 72. The example shown in FIG. 4 is a case where there is no decoupling capacitor arrangement region outside the macro 72. In this case, the resistance component, the inductor component, and the parasitic capacitance of the power supply wiring in the macro 72, the bonding wire 73 of the package, and the power supply wiring 74 in the package interposer, and the non-resistance decoupling capacitor arranged in the macro 72 A resonant circuit is formed.

  In many cases, the macro 72 cannot be equipped with a resistance-free decoupling capacitor having a capacity sufficient to reduce the Q value due to the physical size limitation. In this case, the resistance decoupling with optimized resistance value is not possible. It can be expected that the Q value reduction technique using a ring capacitor is highly effective. Specifically, a part or all of the non-resistive decoupling capacitors, which are arranged in the macro 72, do not affect the operation of the macro 72, to the decoupling capacitors with resistance. replace.

  FIG. 5 is a conceptual diagram for explaining another example of a semiconductor integrated circuit in which an embodiment of the semiconductor integrated circuit design method of the present invention is used. In FIG. 5, 81 is a semiconductor integrated circuit die, 82 is a macro disposed on the die 81, 83 is a bonding wire of the package, 84 is a wiring of a package interposer, and 85 is a macro 82 provided on the die 81. This is a decoupling capacitor arrangement region. All the decoupling capacitors placed in the decoupling capacitor placement region 85 are connected to the power supply wiring of the macro 82.

  One embodiment of the method for designing a semiconductor integrated circuit of the present invention can be used when the macro 82 is designed. The example shown in FIG. 5 is a case where a decoupling capacitor arrangement region 85 is provided outside the macro 82. In this case, the resistance component, the inductor component, and the parasitic capacitance of the power supply wiring of the macro 82, the bonding wire 83 of the package, and the power supply wiring 84 of the package interposer, and the non-resistance decoupling capacitor arranged in the decoupling capacitor arrangement region 85 Thus, a resonance circuit is formed.

  In this example, due to the physical size limitation of the decoupling capacitor placement region 85, there are many cases where it is not possible to mount a resistance-free decoupling capacitor having a sufficient capacity to reduce the Q value. It can be expected that the Q value reduction technique using a decoupling capacitor is highly effective. Specifically, a part or all of the non-resisting decoupling capacitors in the decoupling capacitors placed in the decoupling capacitor placement region 85 are in a range that does not affect the operation of the macro 82. Replace with a ring capacitor.

  FIG. 6 is a flowchart showing an example of use of an embodiment of the semiconductor integrated circuit design method of the present invention, and shows a case where the macros 72 and 82 shown in FIGS. In FIG. 6, 91 is semiconductor integrated circuit layout information, and 92 is package electrical characteristic information.

  In this example, first, the first resonance frequency / Q value calculation means 93 performs decoupling with resistance for the macro 72 (or the macro 82) based on the semiconductor integrated circuit layout information 91 and the package electrical characteristic information 92. With no ring capacitor inserted, calculate the combined resistance value of the resistance component of the power supply wiring including the package, the combined impedance of the inductor component, and the combined capacitance value of the capacitance between the power supply wiring, and calculate the resonance frequency and Q value of the power supply wiring system. Is calculated (step S1).

  Next, within a range that does not affect the operation of the macro 72 (or the macro 82), a resistance-free decoupling that can be replaced with a resistance-type decoupling capacitor among the resistance-free decoupling capacitors connected between the power supply wirings. The sum of the capacitance values of the capacitors is set in the decoupling capacitor replacement means 94 (step S2). This step may be performed by the user directly setting, for example, a capacitance value on the display screen of the computer, or may be performed by designating a ratio with respect to the total power source capacity.

  Next, based on the sum of the capacitance values of the non-resistive decoupling capacitors that can be replaced with the set decoupling capacitors with resistors, the decoupling capacitor replacing means 94 causes the resistance-free decoupling capacitors connected between the power supply wirings to be replaced. Among them, those that can be replaced with a decoupling capacitor with a resistor are replaced with a decoupling capacitor with a resistor (step S3).

  Next, the optimum resistance value calculation means 95 calculates the optimum resistance value of the resistance element constituting the resistor-equipped decoupling capacitor by carrying out an embodiment of the semiconductor integrated circuit design method of the present invention (step S4).

  Next, the resonance frequency and Q value of the power supply wiring system with the decoupling capacitor with resistance inserted are calculated by the second resonance frequency / Q value calculating means 96 (step S5), and these resonance frequency and Q value are calculated. (Step S6), and if the Q value is higher than the criterion (allowable value) of the macro 72 (or macro 82), the process returns to step S2, and the ratio of the decoupling capacitor with resistance is again reviewed. On the other hand, when the Q value is appropriate, the optimum resistance value determining step is terminated.

  FIG. 7 is a schematic configuration diagram of a computer system for carrying out an example of use of an embodiment of a semiconductor integrated circuit design method of the present invention. The computer system shown in FIG. 7 includes a semiconductor integrated circuit layout information 91, package electrical characteristic information 92, a first resonance frequency / Q value calculation program 101, and a decoupling capacitor replacement program 102 in the hard disk 58 shown in FIG. The second resonance frequency / Q value calculation program 103 is stored, and the others are configured similarly to the computer system shown in FIG.

  The first resonance frequency / Q value calculation program 101 causes the CPU 51 to function as the first resonance frequency / Q value calculation means 93. The decoupling capacitor replacement program 102 causes the CPU 51 to function as the decoupling capacitor replacement unit 94. The second resonance frequency / Q value calculation program 103 causes the CPU 51 to function as the second resonance frequency / Q value calculation means 96. In this example, one embodiment 59 of the semiconductor integrated circuit design method of the present invention causes the CPU 51 to function as the optimum resistance value calculation means 95.

  As described above, according to an embodiment of the semiconductor integrated circuit design method of the present invention, the first resonance frequency calculation means 41, the second resonance frequency calculation means 42, the resonance frequency average value calculation means 43, The optimum resistance value calculating means 44 can automatically calculate the optimum resistance value of the resistance element of the decoupling capacitor with resistance inserted between the power supply wirings having different voltages in the semiconductor integrated circuit to stabilize the power supply voltage. .

1 is an equivalent circuit diagram of a power supply wiring system viewed from a semiconductor integrated circuit to which an embodiment of a semiconductor integrated circuit design method of the present invention is applied. 1 is a functional block diagram of a computer system for carrying out an embodiment of a semiconductor integrated circuit design method of the present invention. FIG. 1 is a schematic configuration diagram of a computer system for carrying out an embodiment of a semiconductor integrated circuit design method of the present invention. It is a conceptual diagram for demonstrating an example of the semiconductor integrated circuit in which one Embodiment of the design method of the semiconductor integrated circuit of this invention is used. It is a conceptual diagram for demonstrating the other example of the semiconductor integrated circuit with which one Embodiment of the design method of the semiconductor integrated circuit of this invention is used. It is a flowchart which shows the usage example of one Embodiment of the design method of the semiconductor integrated circuit of this invention. 1 is a schematic configuration diagram of a computer system for implementing an example of use of an embodiment of a semiconductor integrated circuit design method of the present invention. FIG. 3 is an equivalent circuit diagram of a power supply wiring system as viewed from a semiconductor integrated circuit incorporated in a package. It is a figure which shows the Q value reduction circuit of the power supply wiring system which patent document 1 proposes. It is a figure which shows the equivalent circuit of the power supply wiring system used in order to examine the optimal resistance value of the resistance element which comprises the decoupling capacitor with a resistance inserted between power supply wiring. It is a figure which shows the relationship between the resonant frequency and Q value of the power supply wiring system shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... External power supply, 2A, 2B ... Resistance component of power supply wiring, 3A, 3B ... Inductor component of power supply wiring, 4 ... Capacity between power supply wirings, 11 ... Power supply, 12A, 12B ... Inductor component of power supply wiring, 13 ... Resistance None Decoupling capacitor, 14 ... Decoupling capacitor with resistor, 15 ... Capacitor, 16 ... Resistance element, 17 ... Electronic circuit element, 21 ... External power supply, 22A, 22B ... Resistance component of power supply wiring, 23A, 23B ... Power supply wiring Inductor component, 24: capacitance between power supply lines, 25 ... decoupling capacitor with resistor, 26 ... capacitor, 27 ... resistance element, 31 ... external power supply, 32A, 32B ... resistance component of power supply line, 33A, 33B ... of power supply line Inductor component, 34... Capacitance between power supply wires, 35... Decoupling capacitor with resistor, 36. Resistance element 41... First resonance frequency calculation means 42. Second resonance frequency calculation means 43... Resonance frequency average value calculation means 44... Optimal resistance value calculation means 45. ... ROM, 53 ... RAM, 54 ... input device, 55 ... output device, 56 ... communication device, 57 ... hard disk device (HDD), 58 ... hard disk, 59 ... one embodiment of the semiconductor integrated circuit design program of the present invention , 60 ... circuit constant information, 61 ... first resonance frequency calculation program, 62 ... second resonance frequency calculation program, 63 ... resonance frequency average value calculation program, 64 ... optimum resistance value calculation program, 71 ... die, 72 ... Macro, 73 ... Bonding wire, 74 ... Interposer power supply wiring, 81 ... Die, 82 ... Macro, 83 ... Bonding wire, 84 ... Interposer power supply wiring, 85... Decoupling capacitor placement region, 91... Semiconductor integrated circuit layout information, 92... Package electrical characteristic information, 93... First resonance frequency / Q value calculation means, 94. ... optimal resistance value calculating means, 96 ... second resonance frequency and Q value calculating means, 101 ... first resonance frequency and Q value calculating program, 102 ... decoupling capacitor replacement program, 103 ... second resonance frequency and Q Value calculation program

Claims (4)

A method for designing a semiconductor integrated circuit in which a decoupling capacitor without resistance and a decoupling capacitor with resistance are connected between power supply wirings,
The first calculating means includes a first resonance frequency determined by a resistance component, an inductor component, and a parasitic capacitance of the power supply wiring, and a decoupling capacitor without resistance, and a resistance component, an inductor component, and a parasitic capacitance of the power supply wiring. Calculating a second resonance frequency determined by the non-resistive decoupling capacitor and a capacitor constituting the resistive decoupling capacitor;
The second calculating means calculates an average value of the first resonance frequency and the second resonance frequency, and sets a value equal to an impedance of a capacitor constituting the resistor decoupling capacitor at the average value to the resistance. A method for designing a semiconductor integrated circuit, comprising a step of calculating as an optimum resistance value of a resistance element constituting the attached decoupling capacitor. Before calculating the first resonance frequency and the second resonance frequency, the decoupling capacitor replacement means includes a step of replacing part or all of the resistance-free decoupling capacitor with a resistance decoupling capacitor. The method for designing a semiconductor integrated circuit according to claim 1. A program for designing a semiconductor integrated circuit in which a decoupling capacitor without resistance and a decoupling capacitor with resistance are connected between power supply wirings,
Computer
The first resonance frequency determined by the resistance component, inductor component and parasitic capacitance of the power supply wiring, and the decoupling capacitor without resistance, the resistance component, inductor component and parasitic capacitance of the power supply wiring, and the decoupling capacitor without resistance And a first calculating means for calculating a second resonance frequency determined by a capacitor constituting the decoupling capacitor with resistance, and
An average value of the first resonance frequency and the second resonance frequency is calculated, and a value equal to the impedance of the capacitor constituting the resistor decoupling capacitor in the average value is configured in the resistor decoupling capacitor. A program for designing a semiconductor integrated circuit, comprising: a program that functions as a second calculation unit that calculates the optimum resistance value of a resistance element. Before calculating the first resonance frequency and the second resonance frequency, a program that causes the computer to function as a decoupling capacitor replacement unit that replaces a part or all of a resistance-free decoupling capacitor with a resistance decoupling capacitor. The program for designing a semiconductor integrated circuit according to claim 3, comprising:

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