JP2008249632A - Evaluation method for wiring, and manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain knowledge regarding impurity concentration that closely approximates that in actual wiring structure, by measuring precisely the impurity concentration in a wiring conductive material, under a condition approximating the actual wiring structure, using a sample of relatively simple constitution, and to make the knowledge reflect on actual wiring formation. <P>SOLUTION: A wiring groove 1a is formed in a silicon substrate 1, the wiring groove 1a is embedded by the wiring conductive material 3 to form wiring-like structure 4, and the sample 11 is prepared. The wiring conductive material 3 of the wiring-like structure 4 is subjected to SIMS-analysis by a SIMS method, by using the sample 11. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for evaluating an impurity concentration in wiring in a semiconductor device, and a method for manufacturing a semiconductor device using the evaluation method.

  In recent years, copper (Cu) wiring having low wiring resistance, high electromigration (EM) resistance, and high stress migration (SIV) resistance has been adopted for a wiring structure used in a semiconductor device, for example, a CMOS-LSI.

  Unlike conventional Al wiring, Cu wiring is difficult to process by dry etching. Therefore, in order to form a Cu wiring, after forming a via portion for connecting to the wiring in the interlayer insulating film, a wiring groove for forming the wiring is formed in the interlayer insulating film, and Cu is embedded in the wiring groove. A (single) damascene method and a dual damascene method in which a via hole and a wiring groove for forming a via portion are simultaneously filled with Cu are applied. Here, an electrolytic copper plating method is generally employed for film formation of the wiring from the viewpoint of mass productivity and manufacturing cost.

Impurities such as O, C, S, Cl, and N are mixed in the electrolytic copper plating film of the damascene method, and the presence of impurities in these wirings is one of the main causes of reducing EM resistance, SIV resistance, and the like. (For example, see Non-Patent Documents 1 and 2).
In a copper wiring formation process in a general Cu / Ta (TaN) wiring structure (Ta (TaN) is a Cu base film), EM resistance and SIV resistance are in a trade-off relationship, but SIV is mainly generated. It has been reported that this is caused by the wide formation of wiring. Therefore, it is desired to grasp the impurity concentration in the wiring and further control the impurity concentration by adjusting the wiring width.

Japanese Patent Laid-Open No. 11-23497 Influence. Of. Copper Purity on Microstructure and Electromigration. B. Alers, et al. (IEEE 2004) Design of ECP Additive for 65 nm-node Technology Cu BEOL Reliability, H. Shih, et al., (ITC 2005)

  In general, the impurity concentration of a Cu wiring conductive material is evaluated by using a sample obtained by forming a Cu film on a flat portion of a substrate or a Cu substrate on a flat substrate as a sample. By the law (SIMS).

  This is due to the following reason. When using a sample that has wiring formed in the interlayer insulating film by the damascene method and is equivalent to the actual wiring structure and analyzed by the SIMS method, the measurement beam diameter is considerably larger than the wiring width. The insulating film material other than the wiring conductive material is mixed into the secondary ions by the SIMS method. Since the insulating film material contains the same element as the impurity to be analyzed, the influence of the element is reflected in the analysis result. Therefore, since it is extremely difficult to analyze the impurity concentration in the wiring with high accuracy, the above sample is used.

  However, when analyzed by the SIMS method using a sample in which Cu is formed as a Cu wiring as described above, the impurity concentration information indicates that the sample is different in film formation mode from the actual wiring structure. There is a problem that it is different from the actual impurity concentration of Cu wiring. At present, no method for analyzing the impurity concentration of the actual Cu wiring as accurately as possible has been reported, and the current search for darkness is in progress.

  The present invention has been made in view of the above-mentioned problems. Using a sample with a relatively simple configuration, the impurity concentration of the wiring conductive material is accurately measured in a situation that approximates the actual wiring structure, and the actual It is possible to obtain knowledge of the impurity concentration very close to the wiring structure, and further use this knowledge to reduce the impurity concentration in the wiring and manufacture a highly reliable semiconductor device having excellent EM resistance and SIV resistance. An object of the present invention is to provide a method for evaluating wiring and a method for manufacturing a semiconductor device, which makes it possible.

  The wiring evaluation method of the present invention includes a step of processing a surface of a silicon substrate to form a groove, a step of embedding a conductive material in the groove to form a wiring-like structure, and the wiring-like structure is formed. And analyzing the concentration of impurities present in the wiring conductive material of the wiring-like structure using the silicon substrate as a sample.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming a groove by processing the surface of a first silicon substrate, and a conductive material in the groove using a first copper sulfate plating solution containing a chlorine element. And using the first silicon substrate on which the wiring-like structure is formed as a sample, the concentration of impurities present in the conductive material of the wiring-like structure is determined. Analyzing the insulating film formed on the second silicon substrate to form a wiring groove, and using the second copper sulfate plating solution containing chlorine element in the wiring groove. A second electrolytic plating step of embedding the conductive material to form a wiring structure, and the chlorine concentration in the second copper sulfate plating solution is controlled based on the analysis result.

  According to the present invention, using a sample with a relatively simple configuration, the impurity concentration of the wiring conductive material is accurately measured in a situation that approximates the actual wiring structure, and knowledge of the impurity concentration very close to the actual wiring structure is obtained. Can be obtained. Furthermore, by using the knowledge, it is possible to reduce the impurity concentration in the wiring and manufacture a highly reliable semiconductor device having excellent EM resistance and SIV resistance.

-Basic outline of the present invention-
The inventor of the present invention has arrived at the present invention as a result of intensive studies to establish a technique for accurately measuring the impurity concentration of a wiring conductive material in a situation that approximates an actual wiring structure.
In the present invention, a single crystal silicon substrate generally used as a semiconductor substrate is used, and this silicon substrate is regarded as an interlayer insulating film for forming a wiring groove of an actual wiring structure, and the wiring groove is formed in the silicon substrate. For example, a wiring conductive material is embedded through a base conductive film to form a wiring-like structure close to the actual wiring structure.

  A silicon substrate is relatively easy to perform fine etching, and can be easily and accurately formed even with a fine width wiring groove. Moreover, unlike the interlayer insulating film, it does not contain the same element as the wiring impurities, and does not affect the measured impurity concentration when analyzing the wiring conductive material by the SIMS method.

  Therefore, using a sample in which a wiring trench and a wiring-like structure are formed on a silicon substrate, the wiring-like structure is sputtered, and the concentration of impurities present in the wiring conductive material of the wiring-like structure due to the elements scattered from the wiring-like structure. Analyze. For example, by analyzing the wiring conductive material using the SIMS method, the impurity concentration of the wiring conductive material is accurately measured in a situation that approximates the actual wiring structure, and knowledge of the impurity concentration extremely close to the actual wiring structure is obtained. be able to.

  Here, in an actual wiring structure, after the wiring is formed in the wiring groove of the interlayer insulating film, the wiring structure is often annealed in order to increase the grain size and further reduce the resistance. However, as with the actual wiring structure, if a sample having the above wiring-like structure is annealed to obtain information on the impurities thermally diffused in the wiring conductive material by annealing, the silicon substrate and the underlying conductive film react. There is a concern that the wiring-like structure will collapse.

Therefore, in the present invention, annealing is performed under a predetermined annealing condition, for example, a temperature within a range of 150 ° C. or higher and 350 ° C. or lower, and a relatively high temperature annealing condition such as a processing time of 90 seconds or longer and 180 seconds or shorter. In this case, a protective film for preventing the thermal reaction, for example, a SiN film or a SiC film is formed between the surface of the wiring groove of the silicon substrate and the underlying conductive film.
However, in this case, it is necessary to exclude the same element as the impurity to be analyzed in the protective film, for example, N when the SiN film is used, and C when the SiC film is used, from the impurity to be analyzed. .

Furthermore, in the present invention, knowledge of various impurity concentrations obtained by the analysis using the above sample is applied to the formation of an actual wiring structure. That is, based on the results of the above analysis, the wiring conductive material is adjusted, specifically, the wiring conductive material is adjusted to the component condition that reduces the ratio of the impurities in the wiring conductive material, thereby forming an actual wiring structure. To do.
By adopting this configuration, a highly reliable semiconductor device in which the impurity concentration in the wiring is reduced is realized.

  In Patent Document 1, a recess formed in a silicon substrate is formed, and a measurement object is provided in the recess so as to be concave with respect to the surroundings (that is, clearly shown in FIG. 1 of Patent Document 1). As shown, the surface of the object to be measured is made lower than the surface of the silicon substrate so as not to embed the depression.), The SIMS measurement is performed by irradiating the object with primary ions from an oblique direction. Techniques to perform are disclosed. However, the invention of Patent Document 1 is intended to perform SIMS measurement with excellent resolution when the measurement target region is concave compared to the surroundings, and there is no specification of the measurement target. In addition, the hollow shape is naturally shown in a rectangular shape larger than the primary ion beam diameter. The object of the present invention is to accurately identify the impurities of the damascene wiring, and the size of the sputter region, for example, a wiring-like structure whose width is significantly smaller than the beam diameter of the primary ions in the SIMS method is an object of analysis. Moreover, the wiring-like structure is formed so as to fill the wiring groove of the silicon substrate, and is not recessed compared to the surroundings. As described above, the present invention is a completely different invention that is significantly different in object and configuration from the invention of Patent Document 1.

-Specific embodiments to which the present invention is applied-
Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

(First embodiment)
In the present embodiment, a wiring evaluation method is disclosed. Hereinafter, a method for manufacturing a sample and an evaluation method using the sample will be sequentially described.

[Sample preparation method]
FIG. 1 is a schematic cross-sectional view illustrating a sample manufacturing method used in the wiring evaluation method according to the first embodiment in the order of steps.
First, as shown in FIGS. 1A and 1B, a wiring groove 1 a is formed in the silicon substrate 1.
More specifically, the surface of the single crystal silicon substrate 1 is patterned to form wiring-shaped wiring grooves 1a.

Subsequently, as shown in FIG. 1C, a barrier metal layer 2a and a seed layer 2b are sequentially formed.
Specifically, a barrier metal layer 2a made of Ta as a base conductive film and a seed layer 2b are sequentially deposited on the silicon substrate 1 by, for example, sputtering so as to cover the inner wall surface of the wiring groove 1a. Here, the barrier metal layer 2a is formed to a thickness of about 20 nm to 30 nm, and the seed layer 2b is formed to a thickness of about 40 nm to 80 nm.

Subsequently, as shown in FIG. 1 (d), a wiring-like structure 4 in which the wiring groove 1 a is embedded with the wiring conductive material 3 is formed.
Specifically, the wiring conductive material 3 is deposited on the seed layer 2b so as to fill the wiring groove 1a. The wiring conductive material 3 is selected from the group consisting of gold (Au), silver (Ag), copper (Cu), aluminum (Al), platinum (Pt), and manganese (Mn), or the group In this example, Cu is used. In this case, the seed layer 2b is similarly formed using Cu as a material, and the seed layer 2b and the wiring conductive material 3 are integrated by the deposition of Cu. The wiring conductive material 3 is deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), supercritical deposition, electrolytic plating, electroless plating. This is done by at least one of the methods.

  Then, the surface layer of the wiring conductive material 3 is polished by, for example, a chemical mechanical polishing (CMP) method to flatten the surface. As a result, a wiring-like structure 4 is formed by filling the wiring trench 1a with the wiring conductive material 3 via the barrier metal layer 2a, and the sample 11 is completed.

Here, another example of a method for preparing a sample used in the wiring evaluation method according to the present embodiment will be described.
In an actual wiring structure, after the wiring is formed in the wiring groove of the interlayer insulating film, the wiring structure is often annealed in order to increase the grain size and further reduce the resistance. In this example, a protective film is formed in order to perform this annealing without destroying the wiring-like structure.

FIG. 2 is a schematic cross-sectional view showing main steps in another example of a method for preparing a sample used in the wiring evaluation method according to the present embodiment.
First, as in FIGS. 1A and 1B, a wiring groove 1a is formed in the silicon substrate 1. FIG.
More specifically, the surface of the single crystal silicon substrate 1 is patterned to form wiring-shaped wiring grooves 1a.

Subsequently, as shown in FIG. 2A, a protective film 5 is formed.
Specifically, a SiN film or a SiC film is formed as a protective film 5 to a thickness of about 10 nm to 30 nm, for example, by sputtering, for example, so as to cover the inner wall surface of the wiring groove 1a on the silicon substrate 1.
The same element as the impurity to be analyzed in the protective film 5, for example, N is used when a SiN film is used, and C is used when a SiC film is used. It is necessary to exclude from.

  Subsequently, as shown in FIG. 2B, as in FIG. 1C, the base conductive film is made of Ta, for example, by sputtering so as to cover the inner wall surface of the wiring groove 1a on the protective film 5. A barrier metal layer 2a and a seed layer 2b made of the same metal as the wiring conductive material 3 are sequentially deposited.

  Subsequently, as shown in FIG. 2C, after the wiring conductive material 3 is deposited on the seed layer 2b so as to fill the wiring groove 1a, the surface layer of the wiring conductive material 3 is formed, as in FIG. Is polished by CMP to flatten the surface. As a result, a wiring-like structure 4 is formed by filling the wiring trench 1a with the wiring conductive material 3 via the protective film 5 and the barrier metal layer 2a, and the sample 12 is completed.

[Evaluation method using sample]
Hereinafter, using the sample 11 (12) manufactured as described above, here, the impurities contained in the wiring conductive material 3 are analyzed by the SIMS method.
The SIMS method uses a metal ion such as cesium ion (Cs ⁺ ) or lithium ion (Li ⁺ ) as a primary ion, irradiates the sample with a beam in the form of a beam, sputters, and scatters from the irradiated part of the sample. In this method, secondary ions are detected and analyzed with a high-resolution mass spectrometer.

  Note that a so-called GDMS method may be used instead of the SIMS method. In the GDMS method, a positively charged Ar plasma is generated when a conductive solid sample is used as a cathode and a voltage is applied in an argon atmosphere. The surface of the sample is sputtered by this Ar plasma, and the emitted atoms are ionized in the discharge plasma, and the ions are detected by a high resolution mass spectrometer.

(1) SIMS analysis on the sample surface As shown in FIG. 3, the surface of the sample 11 is irradiated in the form of a beam using Cs ⁺ as a primary ion, secondary ions scattered from the surface are detected, and wiring is performed. Impurities in the conductive material 3 are analyzed.

(2) SIMS (backside SIMS) analysis on the back surface of the sample In this case, unlike the sample 11, it is not necessary to flatten the surface of the wiring conductive material 3. Therefore, as shown in FIG. 4A, a sample 13 is obtained in a state where the surface of the wiring conductive material 3 is not polished in FIG.
Then, as shown in FIG. 4B, Cs ⁺ is used as a primary ion, which is irradiated in a beam shape on the back surface of the sample 11 until the bottom of the wiring conductive material 3 is scraped off, and scattered from the surface. Next ions are detected, and impurities in the wiring conductive material 3 are analyzed.

The analysis result of the sample 13 by the backside SIMS method is shown in FIG. 5 together with the comparison with the sample manufactured by the conventional method.
Here, the following three types of samples were prepared.
Sample 1: Cu film formed on a flat substrate as Cu wiring Sample 2: Actual wiring structure substrate with wiring groove formed in wiring groove of interlayer insulating film Sample 3: Sample 13 (width 70 nm / 70nm 1: 1 L & S wiring)

In each of samples 1 to 3, Cu, which is currently the mainstream as a semiconductor wiring conductive material, was formed by electrolytic plating. A general plating solution containing a predetermined amount of an additive was used, and a film was formed under a predetermined current density and rotation conditions.
As shown in FIG. 5, oxygen (O), carbon (C), chlorine (Cl), and sulfur (S) as impurities were analyzed for samples 1 to 3. In sample 2, oxygen contained in the interlayer insulating film was analyzed. It can be seen that (O) and C (C) affect the measurement and an accurate analysis result cannot be obtained. In Sample 1, the form is different from the actual wiring structure, so it cannot be said that the result is sufficient. On the other hand, in the sample 3, the form is as close as possible to the actual wiring structure as compared with the sample 1, and there is no adverse effect on each impurity concentration, and the impurity concentration in the actual wiring structure is not observed. It is thought that the result which can be considered very close was obtained.

(3) Limitation of annealing treatment in the case of using the sample 11 that does not have the protective film 5 As described above, when the sample 11 is annealed, the silicon substrate 1 and the barrier metal layer 2a are thermally reacted depending on the processing conditions. The wiring-like structure 4 may collapse and SIMS analysis may be difficult.
Whether or not the SIMS analysis is possible depends on the film formation conditions of the barrier metal layer 2a, the annealing temperature conditions after the formation of the wiring-like structure 4, and the wiring width to be analyzed. Here, the barrier metal layer 2a was a Ta film having a thickness of 30 nm, Cu was used as the wiring conductive material 3, and the possibility of SIMS analysis for each annealing condition was examined for three types of samples 11 having different wiring widths. For the three types of wiring-like structures 4, a 1: 1 L & S wiring with a width of 70 nm / 70 nm, a 1: 1 L & S wiring with a width of 100 nm / 100 nm, and a 1: 1 L & S wiring with a width of 500 nm / 500 nm were used.

The experimental results are shown in FIG.
At the narrowest width of 70 nm / 70 nm, a result that can be regarded as an acceptable range was obtained up to the annealing treatment under the treatment conditions at 250 ° C. for 90 seconds. At 100 nm / 100 nm, sufficient analysis was possible up to annealing treatment under the treatment conditions at 250 ° C. for 90 seconds, but sufficient analysis was difficult under the treatment conditions at 275 ° C. for 90 seconds. At the widest 500 nm / 500 nm, it was possible to analyze sufficiently up to annealing treatment at 300 ° C. for 90 seconds, but the wiring-like structure 4 collapsed at 350 ° C. for 90 seconds, and analysis was impossible. became.
As described above, even in the sample 11 that does not have the protective film 5, if the annealing process conditions are limited, accurate information can be obtained regarding the thermal diffusion of impurities by the annealing process when forming the actual wiring structure. Was confirmed.

(4) Restriction of annealing treatment in the case of using the sample 12 having the protective film 5 Subsequently, the barrier metal layer 2a is formed on the sample 12 having the SiN film having a thickness of about 20 nm as the protective film 5 in the same manner as described above. Using a Ta film with a thickness of 30 nm, Cu as the wiring conductive material 3, and three types of samples 11 having different wiring widths, the possibility of SIMS analysis for annealing treatment was examined. For the three types of wiring-like structures 4, a 1: 1 L & S wiring with a width of 70 nm / 70 nm, a 1: 1 L & S wiring with a width of 100 nm / 100 nm, and a 1: 1 L & S wiring with a width of 500 nm / 500 nm were used.

The experimental results are shown in FIG.
In this sample 12, even when annealing was performed for all three types of L & S wiring under high-temperature and long-time processing conditions at 350 ° C. for 180 seconds, the wiring-like structure 4 was not completely disintegrated, and sufficient The result is that it can be analyzed.
From the above, it has been found that the formation of the protective film 5 can sufficiently withstand high-temperature and long-time annealing. By using the sample 12, it was confirmed that accurate information can be obtained about the thermal diffusion of impurities by annealing in a wide temperature range when forming an actual wiring structure.

  As described above, according to the present embodiment, the samples 11 to 13 having a relatively simple configuration are used to accurately measure the impurity concentration of the wiring conductive material 3 in a situation that approximates the actual wiring structure. It is possible to obtain knowledge of the impurity concentration extremely close to the wiring structure.

(Second Embodiment)
In the present embodiment, a semiconductor device manufacturing method to which the wiring evaluation method described in the first embodiment is applied is disclosed.
In the present embodiment, when manufacturing a semiconductor device, the wiring structure is formed by controlling the impurity concentration of the wiring conductive material based on the knowledge obtained by the wiring evaluation method according to the first embodiment.

In describing the manufacturing method of the semiconductor device in the present embodiment, an example of a wiring conductive material applied to the manufacturing method will be described.
First, the knowledge for each film forming method of the wiring conductive material obtained by the wiring evaluation method will be described.

(1) In the case where a wiring conductive material (Cu) is formed by an electrolytic plating method Here, for each impurity concentration value of the wiring conductive material 3 in the sample 11 manufactured by the manufacturing method described in the first embodiment, wiring is performed. In the case where the conductive material 3 is formed by the electrolytic plating method, the improvement conditions of each component in the copper sulfate plating solution used for the electrolytic plating were searched.

  As the sample 11, one prepared as a 1: 1 L & S wiring having a width of 70 nm / 70 nm was used. Impurities to be measured are oxygen (O), carbon (C), chlorine (Cl), and sulfur (S).

The experimental results are shown in FIG.
Here, first, a sample 11 (indicated by REF in FIG. 8) to be referred to was manufactured by the manufacturing method described in the first embodiment, and each impurity concentration was analyzed by SIMS method using the sample 11. Based on this result, among the components in the copper sulfate plating solution, the concentration of chlorine, which is an inorganic component, was increased (50 mg / l → 75 mg / l), and the Cu plating solution was adjusted without changing other component conditions. Similarly, a sample 11 (shown in FIG. 8 under improvement conditions) was produced. When this sample 11 was used to analyze the concentration of each impurity by SIMS, the concentration of carbon in the impurity decreased (3.0 × 10 ¹⁹ atoms / cm ³ → 2.3 × 10 ¹⁹ atoms / cm ³ ). It was confirmed. It was also found that the concentration of sulfur (S) also decreased (3.4 × 10 ¹⁹ atoms / cm ³ → 2.3 × 10 ¹⁹ atoms / cm ³ ).

(2) When wiring conductive material (Cu) is formed by chemical vapor deposition (CVD) method Here, here, wiring conductive material 3 in sample 11 manufactured by the manufacturing method described in the first embodiment is used. With respect to the value of each impurity concentration, the conditions for improving the film formation were searched when the wiring conductive material 3 was formed by the CVD method.

  As the sample 11, one prepared as a 1: 1 L & S wiring having a width of 70 nm / 70 nm was used. Here, a barrier metal layer 2a made of Ta and TaN is formed to a thickness of about 5 nm in the wiring groove 1a of the silicon substrate 1 by sputtering, and subsequently a seed layer 2b made of Cu is formed by sputtering in the same sputtering apparatus. The film was formed to a thickness of about 50 nm. Thereafter, the wiring conductive material 3 was made Cu, the silicon substrate 1 was introduced into a Cu-CVD apparatus, and the wiring trench 1a was filled with Cu via the barrier metal layer 2a and the seed layer 2b by Cu-CVD.

The deposition conditions for Cu-CVD are Cu (hfac) tmvs (Trimethylvinylsilyl hexafluoroacetylacetonate Cu (I) as the main raw material, a flow rate of 0.3 g / min, a substrate temperature of 180 ° C., a deposition pressure of 100 Pa, and a carrier gas. Using a mixed gas of H ₂ / He, it was supplied to the Cu-CVD apparatus at a flow rate of 600 sccm.

Each impurity concentration was analyzed by the SIMS method using the sample 11 produced as described above. Impurities to be measured are carbon (C) and oxygen (O). As a result, each impurity concentration was smaller than 1 × 10 ¹⁸ atoms / cm ³ (DL) for carbon, and 3 × 10 ¹⁸ atoms / cm ³ for oxygen. Based on this knowledge, it was possible to form a high-purity fine wiring by a manufacturing method described later by setting the raw material purity of Cu-CVD high and using a mixed gas of H ₂ / He as a carrier gas at a low pressure. In the case of Cu-CVD, unlike electrolytic plating, the impurities in the wiring conductive material were constant regardless of the wiring width.

  Although a Ta / TaN laminated film is used here as the barrier metal layer, Ti or Zr, or a nitrogen compound thereof may be used. In addition, although pure Cu is used for the seed layer, an alloy layer added with a small amount of impurities such as Al, Mn, Sn, Ti, etc. may be used in order to suppress aggregation of the wiring conductive material during CVD film formation. By adopting this configuration, it is possible to improve Cu embedding by Cu-CVD.

(3) In the case where a wiring conductive material (Cu) is formed by physical vapor deposition (PVD) method Here, each impurity of the wiring conductive material 3 in the sample 11 manufactured by the manufacturing method described in the first embodiment. With respect to the concentration value, when the wiring conductive material 3 was formed by the PVD method, the conditions for improving the film formation were searched.

  As the sample 11, one prepared as a 1: 1 L & S wiring having a width of 70 nm / 70 nm was used. Here, a barrier metal layer 2a made of Ta and TaN is formed to a thickness of about 10 nm in the wiring groove 1a of the silicon substrate 1 by sputtering, and a Cu layer is subsequently formed to a thickness of about 30 nm by sputtering in the same sputtering apparatus. And annealed at 250 ° C. for 30 seconds in the same apparatus. A series of steps including film formation and annealing treatment of this Cu layer was repeated five times, and the inside of the wiring groove 1a was filled with Cu via the barrier metal layer 2a.

As the Cu-PVD film forming conditions, low-pressure long-throw magnetron sputtering with a silicon substrate-target distance of 450 mm and a film forming pressure of 1 × 10 ⁻³ Pa was performed, the target voltage was 15 kW, and the substrate bias was 60 W. Thus, the directivity of Cu ions reaching the wiring trench 1a was sufficiently high. By the annealing treatment after the film formation, the formed Cu surface is smoothed. By repeating this series of steps, Cu embedding can be improved.

Each impurity concentration was analyzed by the SIMS method using the sample 11 produced as described above. Impurities to be measured are carbon (C) and oxygen (O). As a result, each impurity concentration is smaller than 1.1 × 10 ¹⁸ atoms / cm ³ (DL) for carbon, and 2.2 × 10 ¹⁸ atoms / cm ³ (for oxygen). (DL)). Based on this knowledge, high purity fine wiring could be formed by executing the manufacturing method described later. Also in the case of Cu-PVD, unlike electrolytic plating, the impurities in the wiring conductive material were constant regardless of the wiring width.

Normally, it is difficult to embed the fine wiring by the PVD method, but using ions with improved directivity as in this case, or heating the silicon substrate to 150 ° C. to 300 ° C. during Cu film formation By using the momentum of ion bombardment to proliferate Cu diffusion on the surface during film formation, or by adopting a technique such as alternately repeating film formation and etching, it is possible to achieve good embedding.
Although a Ta / TaN laminated film is used here as the barrier metal layer, Ti or Zr, or a nitrogen compound thereof may be used.

Hereinafter, a method for manufacturing the semiconductor device according to the present embodiment will be described. Here, for example, a case where the wiring conductive material (Cu) is formed by the electrolytic plating method described in the above (1) is illustrated.
9 to 11 are schematic cross-sectional views illustrating the semiconductor device manufacturing method according to the second embodiment in the order of steps. For convenience of illustration, in FIGS. 9 to 11, the silicon substrate and the semiconductor element are omitted, and only the upper layer portion from the interlayer insulating film covering the semiconductor element is shown.

  First, a predetermined semiconductor element is formed on an active region defined by an element isolation structure such as STI on a silicon substrate. As a semiconductor element, for example, a MOS transistor including a gate electrode formed on a silicon substrate through a gate insulating film, and a source / drain formed by introducing impurities into the surface layer portion of the active region on both sides of the gate electrode Etc.

Subsequently, as shown in FIG. 9A, an interlayer insulating film 101 and a silicon nitride film 102 are sequentially formed.
Specifically, an interlayer insulating film 101 made of, for example, a silicon oxide film is deposited to a thickness of about 200 nm to 300 nm by a CVD method or the like so as to cover the semiconductor element.
Next, a silicon nitride film 102 is deposited to a thickness of about 50 nm to 100 nm on the interlayer insulating film 101 by CVD or the like.

Subsequently, as shown in FIG. 9B, a resist pattern 103 is formed.
Specifically, a resist is applied on the silicon nitride film 102, and the resist is processed by lithography to form a wiring-shaped opening 103a, thereby forming a resist pattern 103.

Subsequently, as shown in FIG. 9C, the silicon nitride film 102 is processed.
Specifically, the silicon nitride film 102 is processed by dry etching using the resist pattern 103 as a mask. As a result, an opening 102 a having a wiring shape following the opening 103 a of the resist pattern 103 is formed in the silicon nitride film 102.

Subsequently, as shown in FIG. 9D, a wiring groove 101 a is formed in the interlayer insulating film 101.
Specifically, the interlayer insulating film 101 is processed by dry etching using the resist pattern 103 and the silicon nitride film 102 as a mask. As a result, a wiring trench 101 a having a shape following the opening 102 a of the silicon nitride film 102 is formed in the interlayer insulating film 101.
The resist pattern 103 is removed by, for example, an ashing process.

Subsequently, as shown in FIG. 9E, a barrier metal layer 104 and a seed layer 105 are sequentially formed.
A barrier metal layer 104 made of Ta as a base conductive film and a seed layer 105 for Cu plating are sequentially deposited on the interlayer insulating film 101 by sputtering, for example, so as to cover the inner wall surface of the wiring trench 101a. Here, the barrier metal layer 104 is formed to a thickness of about 10 nm to 30 nm, and the seed layer 105 is formed to a thickness of about 40 nm to 80 nm.

Subsequently, as shown in FIG. 10A, the wiring groove 101a is filled with Cu.
In this embodiment, when Cu, which is a wiring conductive material, is formed by electrolytic plating, sample 11 or sample 12 is prepared as described above in order to adjust each component of the copper sulfate plating solution used for electrolytic plating. For example, the impurity concentration is measured by the SIMS method. As a result, for example, the knowledge that the impurity concentration (carbon concentration in this case) of Cu that is the wiring conductive material can be decreased by increasing the concentration of chlorine as described above. In this embodiment, using this knowledge, the copper sulfate plating solution for forming the electrolytic plating of Cu 106 is controlled and controlled (for example, the chlorine concentration is increased), and the electrolytic plating is performed using the copper sulfate plating solution.

  In addition, when forming a Cu film using a CVD method or a PVD method instead of the electrolytic plating method, for example, as described in the above (1), SIMS analysis is performed using the sample 11 or the sample 12, and the result (Film formation conditions) may be reflected in Cu film formation.

  Specifically, Cu 106 is formed on seed layer 105 so as to embed wiring trench 101a of interlayer insulating film 101 by an electrolytic plating method using a copper sulfate plating solution whose components are adjusted as described above. At this time, the seed layer 105 and the Cu 106 are integrated by the deposition of the Cu 106.

  Next, Cu 106 is annealed as necessary. This annealing process is intended to further reduce the resistance by increasing the grain size of Cu, and is executed, for example, at a temperature in the range of 150 ° C. to 350 ° C. and a processing time of 90 seconds to 180 seconds. . When this annealing treatment is performed, the same annealing treatment is performed by SIMS analysis according to the above temperature and treatment time, for example, when annealing treatment is performed at a temperature close to 350 ° C. for a treatment time of 180 seconds. It is preferable to use the sample 12 provided with the protective film 5 of SiC or SiN as a sample to be applied to the sample for use.

Subsequently, as shown in FIG. 10B, the surface layer of Cu 106 is flattened to form the lower wiring 107.
Specifically, the surface layer of Cu 106 is polished by CMP using the silicon nitride film 102 as a polishing stopper, and the surface is flattened. As a result, a lower wiring 107 is formed by filling the wiring trench 101a with Cu 106 via the barrier metal layer 104.

Subsequently, as shown in FIG. 10C, a cap layer 108 is formed.
Specifically, an insulating film, for example, a SiC film is deposited on the silicon nitride film 102 so as to cover the lower wiring 107 to a film thickness of about 30 nm to 100 nm by a plasma CVD method or the like, thereby forming the cap layer 108. The cap layer 108 is formed to prevent Cu diffusion at the interface of the lower wiring 107.

Subsequently, as shown in FIG. 10D, an interlayer insulating film 109 having a silicon nitride film 118 therein is formed.
Specifically, for example, a silicon oxide film is deposited on the cap layer 108 by a CVD method or the like.
Next, a material having an etching rate lower than that of the silicon oxide film, for example, a silicon nitride film 118 is deposited on the silicon oxide film. Then, the silicon nitride film 118 is processed to form a via hole-shaped opening 118a at a position aligned with the lower wiring 107 existing in the lower layer.

Next, a silicon oxide film is deposited so as to cover the silicon nitride film 118.
Thus, the interlayer insulating film 109 made of the silicon oxide film having the silicon nitride film 118 having the opening 118a formed therein is formed.

Subsequently, as shown in FIG. 11A, a silicon nitride film 110 is formed, and the silicon nitride film 110 is processed using the resist pattern 111.
Specifically, the silicon nitride film 110 is deposited on the interlayer insulating film 109 to a thickness of about 50 nm to 100 nm by the CVD method or the like.
Next, a resist is applied on the silicon nitride film 109, and the resist is processed by lithography to form a wiring-shaped opening 111a, thereby forming a resist pattern 111.
Next, the silicon nitride film 110 is processed by dry etching using the dies pattern 111 as a mask. As a result, an opening 110 a having a wiring shape following the opening 111 a of the resist pattern 111 is formed in the silicon nitride film 110.

Subsequently, as shown in FIG. 11B, a groove 112 including a wiring groove 112 a and a via hole 112 b is formed in the interlayer insulating film 109.
Specifically, using the resist pattern 111 and the silicon nitride film 110 as a mask, the interlayer insulating film 109 is processed by dry etching until a part of the surface of the lower wiring 107 is exposed. That is, in this case, the silicon nitride film 118 serves as an etching stopper above the interlayer insulating film 109, and a wiring groove 112a having a shape following the opening 110a of the silicon nitride film 110 is formed. Subsequently, by performing the above-described dry etching until a part of the surface of the lower wiring 107 is exposed, a via hole 112b having a shape following the opening 118a of the silicon nitride film 118 is formed below the interlayer insulating film 109. The As described above, the trench 112 in which the wiring trench 112 a and the via hole 112 b are integrated is formed in the interlayer insulating film 109 by one continuous dry etching.

Subsequently, as shown in FIG. 11C, an upper wiring 116 electrically connected to the lower wiring 107 is formed.
Specifically, first, a barrier metal layer 121 made of Ta as a base conductive film and a seed layer for Cu plating (not shown) are formed by sputtering, for example, so as to cover the inner wall surface of the groove 112 on the interlayer insulating film 109. And the like are sequentially deposited. Here, the barrier metal layer 121 is formed to a thickness of about 10 nm to 30 nm, and the seed layer is formed to a thickness of about 40 nm to 80 nm.

Next, the wiring 112 is embedded with Cu106.
Here too, as in the formation of the lower wiring 107, the knowledge obtained by SIMS analysis using the sample 11 or 12 is used to adjust and control the copper sulfate plating solution for forming the electrolytic plating of Cu 106 (for example, chlorine The concentration is increased) and electrolytic plating is performed using the copper sulfate plating solution. Cu 106 is formed on the seed layer so as to fill the groove 112 of the interlayer insulating film 109 by the electrolytic plating method using the copper sulfate plating solution whose components are adjusted as described above. At this time, the seed layer and Cu 106 are integrated by the deposition of Cu 106.

  Next, Cu 106 is annealed as necessary. This annealing process is intended to further reduce the resistance by increasing the grain size of Cu, and is executed, for example, at a temperature in the range of 150 ° C. to 350 ° C. and a processing time of 90 seconds to 180 seconds. . Also in this case, the sample 12 may be used in the SIMS analysis in consideration of the annealing treatment.

Next, the surface layer of Cu 106 is polished by CMP using the silicon nitride film 110 as a polishing stopper, and the surface is flattened. As a result, the trench 112 is filled with the Cu 106 via the barrier metal layer 121, and the upper wiring 116 electrically connected to the lower wiring 107 is formed.
Then, an insulating film, for example, a SiC film is deposited on the silicon nitride film 110 so as to cover the upper wiring 116 to a film thickness of about 30 nm to 100 nm by a plasma CVD method or the like, thereby forming a cap layer 117.

  A wiring structure in which a lower wiring and an upper wiring are formed in an interlayer insulating film as described above is formed in a plurality of layers as necessary, thereby completing a semiconductor device having a multilayer wiring structure.

  As described above, according to the present embodiment, the samples 11 to 13 having a relatively simple configuration are used to accurately measure the impurity concentration of the wiring conductive material 3 in a situation that approximates the actual wiring structure. After obtaining knowledge of the impurity concentration very close to the wiring structure of the semiconductor device, using the knowledge, the impurity concentration in the lower wiring 107 and the upper wiring 116 is reduced, and a highly reliable semiconductor device having excellent EM resistance and SIV resistance. Can be manufactured.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1) A step of processing the surface of the silicon substrate to form a groove;
Embedding a conductive material in the groove to form a wiring-like structure;
And analyzing the concentration of impurities present in the wiring conductive material of the wiring-like structure using the silicon substrate on which the wiring-like structure is formed as a sample.

(Appendix 2) The step of embedding the conductive material in the groove includes
Forming a base conductive film in the groove;
The method of evaluating a wiring according to appendix 1, further comprising: forming the conductive material on the base conductive film.

  (Supplementary note 3) The wiring evaluation method according to supplementary note 2, wherein the underlying conductive film is one selected from Ta, TaN and TiN.

  (Supplementary note 4) The wiring evaluation method according to supplementary note 2, wherein a SiN film or a SiC film is formed between the surface of the groove and the underlying conductive film.

  (Appendix 5) The wiring according to any one of appendices 1 to 4, further comprising a step of annealing the silicon substrate after forming the wiring-like structure and before performing the analysis. Evaluation methods.

  (Supplementary note 6) The wiring evaluation method according to supplementary note 4, wherein the annealing treatment is performed at a temperature in a range of 150 ° C. to 350 ° C. and a treatment time of 90 seconds to 180 seconds.

  (Additional remark 7) The said wiring conductive material contains 1 type chosen from the group which consists of gold, silver, copper, aluminum, platinum, and manganese, or at least 2 sorts chosen from the said group The wiring evaluation method according to any one of 1 to 6.

  (Supplementary note 8) The wiring evaluation method according to any one of supplementary notes 1 to 7, wherein the impurity is at least one selected from S, Cl, O, C, and N.

  (Supplementary Note 9) When the wiring conductive material is embedded in the wiring groove, physical vapor deposition (PVD) method, chemical vapor deposition (CVD) method, atomic layer deposition (ALD) method, supercritical deposition method, electrolytic plating 9. The wiring evaluation method according to any one of appendices 1 to 8, wherein at least one film forming method selected from a method and an electroless plating method is used.

  (Supplementary note 10) The wiring according to any one of supplementary notes 1 to 9, wherein the analysis is performed by sputtering the wiring-like structure and detecting an element scattered from the wiring-like structure. Evaluation methods.

  (Additional remark 11) The width | variety of the said wiring-like structure is smaller than the size of the said sputtering area | region, The evaluation method of the wiring of Additional remark 10 characterized by the above-mentioned.

  (Supplementary note 12) The wiring evaluation method according to supplementary note 10 or 11, wherein the analysis is performed by secondary ion mass spectrometry.

  (Supplementary note 13) The wiring evaluation according to any one of supplementary notes 1 to 12, further comprising a step of polishing and flattening a surface of the wiring-like structure after forming the wiring-like structure. Method.

  (Supplementary note 14) The wiring evaluation method according to supplementary note 12, wherein the beam is irradiated from the back surface of the silicon substrate during the analysis.

(Additional remark 15) The process of processing the surface of a 1st silicon substrate, and forming a groove | channel,
A first electrolytic plating step of forming a wiring-like structure by embedding a conductive material in the groove using a first copper sulfate plating solution containing a chlorine element;
Analyzing the concentration of impurities present in the conductive material of the wiring-like structure using the first silicon substrate on which the wiring-like structure is formed as a sample;
Processing the insulating film formed on the second silicon substrate to form a wiring groove;
A second electrolytic plating step of forming a wiring structure by embedding the conductive material in the wiring groove using a second copper sulfate plating solution containing chlorine element,
The method for manufacturing a semiconductor device, wherein a chlorine concentration in the second copper sulfate plating solution is controlled based on the analysis result.

  (Additional remark 16) The said impurity is carbon or sulfur, and when the said carbon or sulfur more than predetermined amount is detected in the said analysis, the chlorine concentration of a said 2nd copper sulfate plating solution is set to the said 1st copper sulfate plating. The method for manufacturing a semiconductor device according to appendix 15, wherein the concentration of chlorine is higher than a chlorine concentration of the liquid.

  (Additional remark 17) The manufacturing method of the semiconductor device of Additional remark 15 or 16 which forms a SiN film or a SiC film in the surface of the said groove | channel.

  (Supplementary note 18) The method for manufacturing a semiconductor device according to supplementary note 17, further comprising a step of annealing the silicon substrate after forming the wiring-like structure and before performing the analysis.

  (Supplementary note 19) The method for manufacturing a semiconductor device according to supplementary note 18, wherein the annealing treatment is performed at a temperature in a range of 150 ° C. to 350 ° C. and a treatment time of 90 seconds to 180 seconds.

  (Additional remark 20) The said analysis is performed by secondary ion mass spectrometry, The manufacturing method of the semiconductor device of any one of Additional remarks 15-19 characterized by the above-mentioned.

It is a schematic sectional drawing shown in order of a process about the preparation method of the sample used for the evaluation method of wiring by a 1st embodiment. It is a schematic sectional drawing which shows the main processes about the other example of the preparation methods of the sample used for the wiring evaluation method by this embodiment. It is a schematic sectional drawing which shows the SIMS analysis using the sample used for the wiring evaluation method by 1st Embodiment. It is a schematic sectional drawing which shows the backside SIMS analysis using the sample used for the wiring evaluation method by 1st Embodiment. It is a figure which shows the analysis result of the sample by backside SIMS method with the comparison with the sample produced by the conventional method. It is a figure which shows whether the SIMS analysis of the sample with respect to each annealing condition is possible. It is a figure which shows whether the SIMS analysis of the sample which has a protective film with respect to each annealing condition is possible. It is a figure shown by comparison with a reference object about improvement conditions of each ingredient in a copper sulfate plating solution used for electroplating. It is a schematic sectional drawing shown in order of a process about the manufacturing method of the semiconductor device by 2nd Embodiment. FIG. 10 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the second embodiment in order of processes subsequent to FIG. 9. FIG. 11 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the second embodiment in order of processes subsequent to FIG. 10.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 1a, 101a, 112a Wiring groove | channel 2a, 104, 121 Barrier metal layer 2b, 105 Seed layer 3 Wiring conductive material 4 Wiring-like structure 5 Protective film 11, 12, 13 Sample 101, 109 Interlayer insulation film 101a, 102a, 103a, 110a, 111a Opening 102, 110, 118 Silicon nitride film 103, 111 Resist pattern 107 Lower wiring 108, 117 Cap layer 112b Via hole 112 Groove 116 Upper wiring

Claims (5)

Processing the surface of the silicon substrate to form grooves,
Embedding a conductive material in the groove to form a wiring-like structure;
And analyzing the concentration of impurities present in the wiring conductive material of the wiring-like structure using the silicon substrate on which the wiring-like structure is formed as a sample. The step of embedding the conductive material in the groove includes
Forming a base conductive film in the groove;
The wiring evaluation method according to claim 1, further comprising: forming the conductive material on the base conductive film.   The wiring evaluation method according to claim 2, wherein a SiN film or a SiC film is formed between the surface of the groove and the base conductive film.   The wiring analysis method according to claim 1, wherein the analysis is performed by secondary ion mass spectrometry. Processing the surface of the first silicon substrate to form a groove;
A first electrolytic plating step of forming a wiring-like structure by embedding a conductive material in the groove using a first copper sulfate plating solution containing a chlorine element;
Analyzing the concentration of impurities present in the conductive material of the wiring-like structure using the first silicon substrate on which the wiring-like structure is formed as a sample;
Processing the insulating film formed on the second silicon substrate to form a wiring groove;
A second electrolytic plating step of forming a wiring structure by embedding the conductive material in the wiring groove using a second copper sulfate plating solution containing chlorine element,
The method for manufacturing a semiconductor device, wherein a chlorine concentration in the second copper sulfate plating solution is controlled based on the analysis result.

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