JP2008244599A - Decoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a decoder capable of completing decoding processing in a short time without increasing the scaling of a circuit too high, even when packets of code data are inputted continuously by configuring two decoding circuits in parallel. <P>SOLUTION: While first decoding circuits (first code register 1, first syndrome resistor 11) execute input processing of code data of one packet, second decoding circuits (second code register 2, second syndrome resistor 12, third syndrome register 13) execute decoding processing two times based on majority rule. Then, while the second decoding circuits (second code register 2, second syndrome resistor 12) execute input processing of code data of one packet, the first decoding circuits (first code register 1, first syndrome resistor 11, third syndrome register 13) execute decoding processing two times, based on the majority logic. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a decoding device that decodes code data, and more particularly, to a decoding device that decodes a cyclic code using a majority logic method.

  A cyclic code is known as an encoding method that is easy to configure in hardware and has high error correction capability, and is particularly applied to high-speed data transmission between devices. The cyclic code is conventionally applied to television teletext, and specifically, a (272, 190) code composed of 190 information bits and 82 parity bits is employed ( Patent Documents 1 and 2).

  In this cyclic coding method, a syndrome is added to the input data for coding, and the coding device includes a shift register for the code length, and the decoding device includes a shift register for (code length + syndrome length) and And a circuit for parity check.

In the decoding process, first, information bits are stored in a code register and a syndrome register. A syndrome is generated while circulating the data in the syndrome register, and the syndrome is corrected by a majority circuit. The corrected output from the majority circuit is input to the syndrome register, and this corrected output is added to the output from the code register to correct the code data.
JP-A-62-235823 JP-A-7-321669

  If the error correction code that can be decoded by majority voting theory has a code length that is more than a certain level that can correct a multi-bit error, an error exceeding the correction capability can be determined by determining the majority decision criterion from the highest value. It is known that the probability of correction can be increased. However, in order to achieve such a purpose, it is necessary to repeat the cycle of the syndrome generation process and the code data correction process as described above by the number of reference values for majority decision.

  In television teletext broadcasting, code data packets are input only in a discrete manner, so that such repeated processing is not a problem.

  However, when the present invention is applied to a high-speed data transfer system between devices in which code data packets are continuously input, it is necessary to cascade a plurality of decoding circuits, and the circuit scale becomes very large. There is a problem that it takes a long time depending on the number of stages of the decoding circuit until the decoding process is completed.

  The present invention has been made in view of such circumstances, and by configuring two decoding circuits in parallel, the circuit scale can be made very large even when packets of code data are continuously input. An object of the present invention is to provide a decoding device that can finish the decoding process in a short time.

  The decoding device according to the present invention is a decoding device that decodes code data input in units of packets using a majority logic method, two code registers in which packets of the code data are alternately input over time, And three syndrome registers that generate syndromes necessary for the majority logic while circulating the input code data.

  In the decoding apparatus of the present invention, code data packets are alternately input to two code registers over time, and decoding processing is performed using syndrome registers corresponding to the code registers. Therefore, even if code data packets are continuously input, the code data input process / code data decoding process are performed in parallel in two systems, so that it is possible to cope with them.

  In the decoding device according to the present invention, the first code register of the two code registers and the first syndrome register of the three syndrome registers constitute a first decoding circuit, and the two The second code register in the code register and the second syndrome register in the three syndrome registers constitute a second decoding circuit, and the third syndrome in the three syndrome registers The register is shared by the first decoding circuit and the second decoding circuit.

  In the decoding apparatus of the present invention, the first code register, the first syndrome register, and the third syndrome register constitute a first decoding circuit, and the second code register, the second syndrome register, and the third syndrome register In the second decoding circuit, the two decoding circuits are not connected in cascade, but are connected in parallel, and the input code data packet is divided into two decoding circuits (the first decoding circuit and the second decoding circuit). The decoding process is performed alternately on the decoding circuit. That is, while a packet is being input by one decoding circuit (first decoding circuit or second decoding circuit), the other decoding circuit (second decoding circuit or first decoding circuit) performs decoding processing. . Therefore, even if code data packets are continuously input, the decoding process can be performed in a short time. In addition, since the third syndrome register is shared by the first decoding circuit and the second decoding circuit, expansion of the circuit scale can be suppressed.

  The decoding apparatus according to the present invention is characterized in that decoding processing by majority logic is performed a plurality of times within a time when one packet of the code data is input to the code register.

  In the decoding apparatus of the present invention, the operation clock in the decoding process is made faster than the operation clock in the code data input process, and the decoding process is performed a plurality of times within the time for inputting the code data of one packet. Therefore, since the majority decision can be made a plurality of times based on a plurality of reference values, the possibility of improving the correction capability is increased.

  Since the decoding device of the present invention includes two code registers and three syndrome registers, and the code data packets are alternately input to each code register over time, the decoding process is performed. Even when the packets are continuously input, the decoding process can be completed in a short time without significantly increasing the circuit scale.

  In the decoding apparatus of the present invention, the first code register and the first syndrome register constitute a first decoding circuit, the second code register and the second syndrome register constitute a second decoding circuit, and the third syndrome Since the register is shared by the first decoding circuit and the second decoding circuit, the input process of the code data packet and the decoding process of the code data are performed by the first decoding circuit and the second decoding circuit. The decoding process can be performed alternately over time, and even when the code data packets are continuously input, the decoding process can be completed in a short time without significantly increasing the circuit scale. Further, since the third syndrome register is shared by the two decoding circuits, it is not necessary to provide the third syndrome register for each decoding circuit, and in this respect as well, expansion of the circuit scale can be suppressed.

  In the decoding apparatus according to the present invention, since the decoding process by the majority logic method is performed a plurality of times within the time for inputting the code data of one packet, the possibility of improving the correction capability can be increased.

  Hereinafter, the present invention will be described in detail with reference to the drawings showing embodiments thereof. Note that the present invention is not limited to the following embodiments.

  FIG. 1 is a circuit configuration diagram of a decoding apparatus according to the present invention. The decoding apparatus includes a first code register 1 and a second code register 2 in which code data is alternately input in units of one packet, a first syndrome register 11 and a second syndrome register 12 that generate a syndrome while circulating the data, Controls the operation timing of the third syndrome register 13, the majority circuit 20 that takes the majority of the outputs of the syndrome registers 11, 12, 13, the sign registers 1, 2, the syndrome registers 11, 12, 13, and the majority circuit 20. And a clock generation circuit 30 for generating an operation clock for this purpose.

  Adders 21, 22 and 23 for adding the outputs of the majority circuit 20 to the outputs of the syndrome registers 11, 12 and 13 are provided on the input side of the syndrome registers 11, 12 and 13. The syndromes are supplied to the syndrome registers 11, 12, and 13 to correct the syndrome. Further, adders 31 and 32 for adding the output of the majority circuit 20 to the outputs of the code registers 1 and 2 are provided on the output side of the code registers 1 and 2, and error correction is performed from the adders 31 and 32. The decryption data is extracted.

  The first code register 1, the first syndrome register 11 and the adders 21 and 31 constitute a first decoding circuit, and the second code register 2, the second syndrome register 12 and the adders 22 and 32 constitute a second The decoding circuit is configured, and the third syndrome register 13, the adder 23, and the majority decision circuit 20 are shared by the first decoding circuit and the second decoding circuit.

  The switches 41 and 42 are switches for switching the input of code data between the first decoding circuit and the second decoding circuit. The switch 51 is a switch for switching between the external connection of the first syndrome register 11 and the majority circuit 20 connection in the first decoding circuit, and the switch 52 is an external connection of the second syndrome register 12 in the second decoding circuit. And a switch for switching the majority circuit 20 connection. The switch 61 is a switch for switching the connection of the first sign register 1 and the majority circuit 20 of the third syndrome register 13 when used as a member for the first decoding circuit. This is a switch for switching between the second code register 2 connection and the majority circuit 20 connection of the third syndrome register 13 when used as a member for the decoding circuit. The switch 70 is a switch for switching the third syndrome register 13 between use for the first decoding circuit and use for the second decoding circuit. The switch 80 is a switch for switching the output of the decoded data between the first decoding circuit and the second decoding circuit.

  In the decoding apparatus of the present invention, as described above, two decoding circuits are configured in parallel so that packets of input code data are distributed alternately. And while the other decoding circuit is inputting the next packet, one decoding circuit performs a decoding process. At this time, the operation clock for the decoding process is set to double the operation clock for the input process. As a result, the decoding process is performed twice within the time for inputting the code data of one packet. These operation clocks are supplied from the clock generation circuit 30 to each member.

  A third syndrome register 13 is provided to perform the majority decision and the generation of the syndrome at the next stage simultaneously. However, since the third syndrome register 13 can be shared by the first decoding circuit and the second decoding circuit, it is not necessary to provide the third syndrome register 13 for each decoding circuit.

  Next, the operation will be described. FIG. 2 is a timing chart showing an operation example of the decoding device of the present invention. 3 to 5 are diagrams showing the switching state of each switch in the decoding device.

  The switching state of each switch in the period 1 of FIG. 2 is as shown in FIG. 1, and the switching state of each switch in the period 2, period 3, and period 4 of FIG. This is as shown in FIG.

  Period 1 + period 2 is a period during which the third syndrome register 13 is used for the second decoding circuit, and period 3 + period 4 is a period during which the third syndrome register 13 is used for the first decoding circuit. is there. During the period 1 + period 2, while the code data of one packet is input from the outside to the first decoding circuit, the second syndrome register 12 and the third syndrome register 13 are used to perform the decoding process based on the majority rule 2 I'm going to go. Similarly, during the period of period 3 + period 4, while code data of one packet is input from the outside to the second decoding circuit, the first syndrome register 11 and the third syndrome register 13 are used to perform decoding based on majority voting theory. The process is performed twice.

  As described above, in the decoding apparatus of the present invention, even if code data packets are continuously input, code data input processing / code data decoding processing is performed in parallel in two systems, so that a relatively small size is achieved. With the circuit configuration, the decoding process can be completed in a short time. In addition, since the operation clock of the decoding process is twice that of the input process, the decoding process based on the majority rule can be performed twice, so that the correction capability can be improved.

  In the above-described embodiment, a case has been described in which the operation clock of the decoding process is set to twice the operation clock of the input process, but may be three times, four times,. 1 can perform decoding processing based on the majority rule of n times without changing the configuration shown in FIG. 1 (two code registers + three syndrome registers), so that the correction capability can be further improved. It is.

It is a circuit block diagram of the decoding apparatus which concerns on this invention. It is a timing chart which shows the operation example of a decoding apparatus. It is a figure which shows the switching state of each switch in a decoding apparatus. It is a figure which shows the switching state of each switch in a decoding apparatus. It is a figure which shows the switching state of each switch in a decoding apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st code register 2 2nd code register 11 1st syndrome register 12 2nd syndrome register 13 3rd syndrome register 20 Majority circuit 30 Clock generation circuit

Claims (3)

In a decoding device that decodes code data input in units of packets using a majority logic method,
And two code registers in which the code data packets are alternately input over time, and three syndrome registers that generate the syndrome necessary for the majority logic method while circulating the input code data. A characteristic decoding apparatus.   The first code register in the two code registers and the first syndrome register in the three syndrome registers form a first decoding circuit, and the second code register in the two code registers. The sign register and the second syndrome register in the three syndrome registers constitute a second decoding circuit, and the third syndrome register in the three syndrome registers is the first decoding circuit. 2. The decoding apparatus according to claim 1, wherein the decoding apparatus is shared by the second decoding circuit.   3. A decoding apparatus according to claim 1, wherein decoding processing by majority logic is performed a plurality of times within a time when one packet of the code data is input to the code register.

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