JP2008244486A - Non-volatile memory element, manufacturing method thereof and semiconductor chip - Google Patents

Non-volatile memory element, manufacturing method thereof and semiconductor chip Download PDF

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Publication number
JP2008244486A
JP2008244486A JP2008084147A JP2008084147A JP2008244486A JP 2008244486 A JP2008244486 A JP 2008244486A JP 2008084147 A JP2008084147 A JP 2008084147A JP 2008084147 A JP2008084147 A JP 2008084147A JP 2008244486 A JP2008244486 A JP 2008244486A
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Prior art keywords
semiconductor pillar
layer
doping layer
memory device
substrate
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JP2008084147A
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Japanese (ja)
Inventor
Jeong-Hee Han
禎 希 韓
Ji-Young Kim
志 永 金
Chung-Woo Kim
▲てい▼ 雨 金
Kang Long Wang
ロン ワン カン
Siguang Ma
マ シグァン
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of JP2008244486A publication Critical patent/JP2008244486A/en
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  • Non-Volatile Memory (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non-volatile memory element which can be easily and highly integrated and has high reliability, and to provide a manufacturing method thereof. <P>SOLUTION: The non-volatile memory element has a first conductivity-type first doping layer 115 formed on a substrate 105; a second conductivity-type semiconductor column 120 extending upward to one surface of the substrate 105 from the first doping layer 115 and having a conductivity type reverse to the first conductivity type; a control gate electrode 150a surrounding the side wall of the semiconductor column 120; an electric charge storage layer 140a interposed between the semiconductor column 120 and the control gate electrode 150a; a first conductivity-type second doping layer 130 disposed on the semiconductor column 120 so as to be electrically coupled to the semiconductor column 120. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は半導体素子に係り、特に、データを保存して読み取りできる不揮発性メモリ素子及びその製造方法に関する。   The present invention relates to a semiconductor device, and more particularly, to a nonvolatile memory device that can store and read data and a method for manufacturing the same.

最近、大容量の携帯用電子装置として、例えば、デジタルカメラ、ＭＰ３プレーヤーなどの電子装置が注目されている。このような電子装置は、小型化及び高容量化がさらに要求されている。電子装置の小型化及び高容量化は、これらの電子装置に利用される不揮発性メモリ素子の高集積化及び高容量化によって達成することができる。   Recently, electronic devices such as digital cameras and MP3 players have attracted attention as large-capacity portable electronic devices. Such electronic devices are further required to be smaller and have higher capacity. Miniaturization and high capacity of electronic devices can be achieved by high integration and high capacity of nonvolatile memory elements used in these electronic devices.

しかし、高集積パターンの形成を通じての不揮発性メモリ素子の高集積化は、工程技術の限界によってその限界に到達してしまった。また、通例的な平面型の不揮発性メモリ素子は、その集積度の上昇につれて、短チャンネル効果による性能低下が問題になりうる。したがって、平面型の不揮発性メモリ素子の高集積化には、信頼性低下を招く恐れがある。   However, the high integration of nonvolatile memory devices through the formation of highly integrated patterns has reached its limit due to the limitations of process technology. In addition, in a typical planar nonvolatile memory device, performance degradation due to the short channel effect may become a problem as the degree of integration increases. Therefore, high integration of the planar nonvolatile memory element may cause a decrease in reliability.

本発明が解決しようとする技術的課題は、高集積化が容易であり、かつ、高い信頼性を有する不揮発性メモリ素子を提供するところにある。   The technical problem to be solved by the present invention is to provide a non-volatile memory element that can be easily integrated and has high reliability.

本発明が解決しようとする他の技術的課題は、前記不揮発性メモリ素子の製造方法を提供するところにある。   Another technical problem to be solved by the present invention is to provide a method for manufacturing the nonvolatile memory device.

前記技術的課題を達成するための本発明の一形態による不揮発性メモリ素子が提供される。第１ドーピング層は、基板上に提供され、第１導電型である。半導体柱は、前記第１ドーピング層から前記基板の一面に対して上向き伸長し、前記第１導電型と逆の導電性を有する第２導電型である。制御ゲート電極は、前記半導体柱の側壁を一回り取り囲む。電荷保存層は、前記半導体柱と前記制御ゲート電極との間に介在される。第２ドーピング層は、前記半導体柱と電気的に連結されるように前記半導体柱上に配置され、前記第１導電型である。   In order to achieve the above technical problem, a nonvolatile memory device according to an aspect of the present invention is provided. The first doping layer is provided on the substrate and is of the first conductivity type. The semiconductor pillar is a second conductivity type extending upward from the first doping layer with respect to one surface of the substrate and having a conductivity opposite to the first conductivity type. The control gate electrode surrounds the side wall of the semiconductor pillar. The charge storage layer is interposed between the semiconductor pillar and the control gate electrode. The second doping layer is disposed on the semiconductor pillar so as to be electrically connected to the semiconductor pillar, and is of the first conductivity type.

前記不揮発性メモリ素子の一例において、前記第１ドーピング層は、前記半導体柱の底面の中心部を覆う。さらに、前記第１ドーピング層は、前記半導体柱の底面全体を覆う。
前記不揮発性メモリ素子の他の例において、トンネリング絶縁層は、前記電荷保存層と前記半導体柱との間に介在され、ブロッキング絶縁層は、前記電荷保存層と前記制御ゲート電極との間に介在される。 In one example of the nonvolatile memory device, the first doping layer covers a central portion of the bottom surface of the semiconductor pillar. Further, the first doping layer covers the entire bottom surface of the semiconductor pillar.
In another example of the nonvolatile memory element, a tunneling insulating layer is interposed between the charge storage layer and the semiconductor pillar, and a blocking insulating layer is interposed between the charge storage layer and the control gate electrode. Is done.

前記技術的課題を達成するための本発明の他の形態による不揮発性メモリ素子が提供される。第１ドーピング層は、基板上に提供され、第１導電型である。半導体柱は、前記第１ドーピング層から前記基板の一面に対して上向きに伸長し、前記第１導電型と逆の導電性を有する第２導電型である。制御ゲート電極は、前記半導体柱の側壁を一回り取り囲む。電荷保存層は、前記半導体柱と前記制御ゲート電極との間に介在され、前記制御ゲート電極の上面及び底面を覆う。そして、第２ドーピング層は、前記半導体柱と電気的に連結されるように前記半導体柱上に配置され、前記第１導電型である。   A non-volatile memory device according to another aspect of the present invention for achieving the above technical problem is provided. The first doping layer is provided on the substrate and is of the first conductivity type. The semiconductor pillar is a second conductivity type that extends upward from the first doping layer with respect to one surface of the substrate and has a conductivity opposite to that of the first conductivity type. The control gate electrode surrounds the side wall of the semiconductor pillar. The charge storage layer is interposed between the semiconductor pillar and the control gate electrode, and covers an upper surface and a bottom surface of the control gate electrode. The second doping layer is disposed on the semiconductor pillar so as to be electrically connected to the semiconductor pillar, and is of the first conductivity type.

前記他の技術的課題を達成するための本発明の一形態による不揮発性メモリ素子の製造方法が提供される。基板上に第１導電型の第１ドーピング層を形成する。前記第１ドーピング層から前記基板の一面に対して上向きに伸長するように、前記第１導電型と逆の導電性を有する第２導電型の半導体柱を形成する。前記半導体柱と電気的に連結されるように前記半導体柱上に、前記第１導電型の第２ドーピング層を形成する。前記半導体柱の側壁を一回り取り囲む電荷保存層を形成する。前記半導体柱の反対側の前記電荷保存層上に制御ゲート電極を形成する。   A method for manufacturing a non-volatile memory device according to an aspect of the present invention for achieving the other technical problem is provided. A first doping layer of the first conductivity type is formed on the substrate. A semiconductor column of a second conductivity type having conductivity opposite to that of the first conductivity type is formed so as to extend upward from the first doping layer with respect to one surface of the substrate. A second doping layer of the first conductivity type is formed on the semiconductor pillar so as to be electrically connected to the semiconductor pillar. A charge storage layer surrounding the side wall of the semiconductor pillar is formed. A control gate electrode is formed on the charge storage layer on the opposite side of the semiconductor pillar.

前記不揮発性メモリ素子の製造方法の一例において、前記半導体柱は、ナノワイヤー構造で形成する。   In one example of a method for manufacturing the nonvolatile memory element, the semiconductor pillar is formed with a nanowire structure.

前記不揮発性メモリ素子の製造方法の他の例において、前記第２ドーピング層を形成する前に、前記半導体柱の側壁を取り囲むスペーサ絶縁膜を形成し、前記第２ドーピング層を形成する工程後、前記スペーサ絶縁膜を除去する。前記スペーサ絶縁膜は、前記半導体柱の側壁を熱酸化させて形成する。   In another example of the method for manufacturing the non-volatile memory device, before forming the second doping layer, a spacer insulating film surrounding a side wall of the semiconductor pillar is formed, and after the step of forming the second doping layer, The spacer insulating film is removed. The spacer insulating film is formed by thermally oxidizing the side wall of the semiconductor pillar.

本発明による不揮発性メモリ素子は、半導体柱の高さを調節することによってチャンネル長を容易に延長できる。さらに、半導体柱の直径または幅を縮めることによって、基板上の集積度を高めることができる。したがって、不揮発性メモリ素子は集積度を高めつつ、短チャンネル効果を抑制できる。   The nonvolatile memory device according to the present invention can easily extend the channel length by adjusting the height of the semiconductor pillar. Furthermore, the degree of integration on the substrate can be increased by reducing the diameter or width of the semiconductor pillar. Therefore, the nonvolatile memory device can suppress the short channel effect while increasing the degree of integration.

また、本発明による不揮発性メモリ素子は、半導体柱の高さを調節することによって、これを取り囲んでいる電荷保存層の面積を広げることができる。これにより、データプログラム及びリテンション特性が改善されることで、不揮発性メモリ素子の動作信頼性が高くなる。さらに、電荷保存層を局部に分けてデータプログラムを行うマルチビット動作の信頼性が高くなる。   In the nonvolatile memory device according to the present invention, the area of the charge storage layer surrounding the nonvolatile semiconductor memory device can be increased by adjusting the height of the semiconductor pillar. As a result, the data program and the retention characteristics are improved, and the operation reliability of the nonvolatile memory element is increased. Furthermore, the reliability of the multi-bit operation in which the charge storage layer is locally divided to perform the data program is increased.

以下、添付した図面を参照して本発明の望ましい実施形態を説明することによって本発明を詳細に説明する。しかし、本発明は、以下で開示される実施形態に限定されるものではなく、相異なる多様な形態で具現され、本実施形態は、単に、本発明の開示を完全にし、当業者に発明の範ちゅうを完全に知らせるために提供されるものである。図面において、各構成要素は、説明の便宜のためにその大きさが誇張されている。   Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are merely a complete disclosure of the present invention and are disclosed to those skilled in the art. It is provided to fully inform the category. In the drawings, the size of each component is exaggerated for convenience of explanation.

図１は、本発明の一実施形態による不揮発性メモリ素子１００を示す部分切断された斜視図である。図２は、図１の不揮発性メモリ素子１００のＩＩ−ＩＩ’線の断面図であり、図３は、図１の不揮発性メモリ素子１００のＩＩＩ−ＩＩＩ’線の断面図である。   FIG. 1 is a partially cut perspective view illustrating a nonvolatile memory device 100 according to an embodiment of the present invention. 2 is a cross-sectional view taken along the line II-II ′ of the nonvolatile memory element 100 of FIG. 1, and FIG. 3 is a cross-sectional view taken along the line III-III ′ of the nonvolatile memory element 100 of FIG.

図１ないし図３を参照すれば、本実施形態の不揮発性メモリ素子１００は、第１ドーピング層１１５と第２ドーピング層１３０との間に介在された半導体柱１２０が提供される。第１ドーピング層１１５及び第２ドーピング層１３０は第１導電型であって、半導体柱１２０は第１導電型と逆の導電性を有する第２導電型である。第１導電型及び第２導電型は、ｎ型及びｐ型でそれぞれ選択された相異なる一つでありうる。例えば、第１ドーピング層１１５及び第２ドーピング層１３０は、第１導電型の不純物で高濃度ドーピングされ、半導体柱１２０は、第２導電型の不純物で低濃度ドーピングされうる。   1 to 3, the nonvolatile memory device 100 of the present embodiment is provided with a semiconductor pillar 120 interposed between a first doping layer 115 and a second doping layer 130. The first doping layer 115 and the second doping layer 130 are of a first conductivity type, and the semiconductor pillar 120 is of a second conductivity type having conductivity opposite to that of the first conductivity type. The first conductivity type and the second conductivity type may be different ones selected for n-type and p-type, respectively. For example, the first doping layer 115 and the second doping layer 130 may be highly doped with a first conductivity type impurity, and the semiconductor pillar 120 may be lightly doped with a second conductivity type impurity.

第１ドーピング層１１５及び第２ドーピング層１３０は、不揮発性メモリ素子でソース領域及びドレーン領域として機能する。ソース領域及びドレーン領域は、その機能によって互いに入れ替わって呼ばれるか、混用されてもよい。半導体柱１２０は、チャンネル領域（図示せず）を限定できる。したがって、半導体柱１２０は、不揮発性メモリ素子１００のオン・オフ動作によって、第１ドーピング層１１５及び第２ドーピング層１３０を電気的に連結または開放させる役割を担う。   The first doping layer 115 and the second doping layer 130 function as a source region and a drain region in the nonvolatile memory device. The source region and the drain region may be referred to interchangeably depending on their functions, or may be mixed. The semiconductor pillar 120 may define a channel region (not shown). Accordingly, the semiconductor pillar 120 plays a role of electrically connecting or opening the first doping layer 115 and the second doping layer 130 by the on / off operation of the nonvolatile memory device 100.

第１ドーピング層１１５は、例えば、基板１０５の一部分に第１導電型の不純物を高濃度ドーピングして限定される。基板１０５は半導体物質からなり、単結晶構造からなる。他の例として、第１ドーピング層１１５は基板１０５上にエピタキシャル層として提供されうる。この場合、第１ドーピング層１１５は基板１０５の格子に合せて形成され、したがって、基板１０５のような結晶構造を有する。   For example, the first doping layer 115 is limited by doping a part of the substrate 105 with a first conductivity type impurity at a high concentration. The substrate 105 is made of a semiconductor material and has a single crystal structure. As another example, the first doping layer 115 may be provided as an epitaxial layer on the substrate 105. In this case, the first doping layer 115 is formed in conformity with the lattice of the substrate 105, and thus has a crystal structure like the substrate 105.

第１ドーピング層１１５の側壁は、素子分離膜１１０で取り囲まれうる。素子分離膜は、例えば、酸化膜、窒化膜または低誘電率膜を用いられる。なお、低誘電率膜とは、酸化膜よりその誘電定数の低い絶縁膜を称する。   A sidewall of the first doping layer 115 may be surrounded by the device isolation layer 110. For example, an oxide film, a nitride film, or a low dielectric constant film is used as the element isolation film. The low dielectric constant film refers to an insulating film whose dielectric constant is lower than that of an oxide film.

半導体柱１２０は、第１ドーピング層１１５上から基板１０５の一面（上面）に対して上向きに伸長して形成される。半導体柱１２０は、半導体物質が柱状に配置されたものを称する。半導体物質は、例えば、シリコン、シリコンゲルマニウム、またはゲルマニウムを含む。なお、本実施形態では、半導体柱１２０は、基板１０５の一面に対して垂直方向に伸長する垂直構造を有するが、本発明の範囲がこれに制限されるものではない。例えば、半導体柱１２０は、基板１０５の一面に対して垂直方向から所定の角度を有した方向に傾いて上向きに伸長されてもよい。   The semiconductor pillar 120 is formed to extend upward from the first doping layer 115 to one surface (upper surface) of the substrate 105. The semiconductor pillar 120 refers to a semiconductor substance arranged in a pillar shape. The semiconductor material includes, for example, silicon, silicon germanium, or germanium. In this embodiment, the semiconductor pillar 120 has a vertical structure extending in a direction perpendicular to one surface of the substrate 105, but the scope of the present invention is not limited to this. For example, the semiconductor pillar 120 may be extended upward while being inclined in a direction having a predetermined angle from the vertical direction with respect to one surface of the substrate 105.

半導体柱１２０は、多様な形態からなることができ、望ましくは、半導体物質のナノワイヤー構造からなることができる。なお、ナノワイヤーとは、ナノメートルスケールの直径を持つ線形態を称する。ナノワイヤーは、ナノテクノロジー分野で通称的に使われ、その断面は円柱以外にも多角形状であってもよい。図１では、半導体柱１２０は、便宜のために円柱の半分のみ図示されたが、図３は、元来の円形断面を図示した。さらに、半導体柱１２０の直径または幅は一定なものが望ましいが、本発明の範囲はこれに制限されるものではない。例えば、半導体柱１２０は、基板１０５の上面から上へ行くほど直径または幅が大きくなる放射形構造であってもよい。   The semiconductor pillar 120 may have various forms, and preferably may have a nanowire structure of a semiconductor material. Nanowire refers to a line form having a nanometer-scale diameter. Nanowire is commonly used in the field of nanotechnology, and its cross section may be polygonal in addition to a cylinder. In FIG. 1, the semiconductor pillar 120 is shown only half of the cylinder for convenience, but FIG. 3 shows the original circular cross section. Further, it is desirable that the semiconductor pillar 120 has a constant diameter or width, but the scope of the present invention is not limited thereto. For example, the semiconductor pillar 120 may have a radial structure whose diameter or width increases from the upper surface of the substrate 105 upward.

半導体柱１２０は、第１ドーピング層１１５上にエピタキシャル層として提供され、底面１２０１、側壁１２０２及び上面１２０３を備える。第１ドーピング層１１５は、例えば、半導体柱１２０の底面１２０１の少なくとも中心付近（中心部）を覆うことができる。望ましくは、第１ドーピング層１１５は、半導体柱１２０の底面１２０１全体を覆うことができる。   The semiconductor pillar 120 is provided as an epitaxial layer on the first doping layer 115 and includes a bottom surface 1201, a sidewall 1202, and a top surface 1203. For example, the first doping layer 115 can cover at least the vicinity (center portion) of the bottom surface 1201 of the semiconductor pillar 120. For example, the first doping layer 115 may cover the entire bottom surface 1201 of the semiconductor pillar 120.

第２ドーピング層１３０は、半導体柱１２０上にエピタキシャル層として提供されうる。これにより、第２ドーピング層１３０、半導体柱１２０及び第１ドーピング層１１５は同じ結晶構造からなり、例えば、単結晶構造である。第２ドーピング層１３０は、半導体柱１２０の上面１２０３を覆う。   The second doping layer 130 may be provided as an epitaxial layer on the semiconductor pillar 120. Accordingly, the second doping layer 130, the semiconductor pillar 120, and the first doping layer 115 have the same crystal structure, for example, a single crystal structure. The second doping layer 130 covers the upper surface 1203 of the semiconductor pillar 120.

第２ドーピング層１３０は、半導体柱１２０及び第１ドーピング層１１５より大きい直径または幅を有する。本発明の実施形態において、幅とは、基板１０５と平行な方向の長さを称する。なお、第２ドーピング層１３０は、直径または幅が一定なものに限られず、例えば、半導体柱１２０の上面１２０３から上に行くほどその半径または幅の大きい放射形構造であってもよい。   The second doping layer 130 has a larger diameter or width than the semiconductor pillar 120 and the first doping layer 115. In the embodiment of the present invention, the width refers to a length in a direction parallel to the substrate 105. The second doping layer 130 is not limited to one having a constant diameter or width, and may be a radial structure whose radius or width increases from the upper surface 1203 of the semiconductor pillar 120 upward, for example.

制御ゲート電極１５０ａは、半導体柱１２０の側壁１２０２を少なくとも一回り取り囲んで形成される。制御ゲート電極１５０ａは、基板１０５の一面に対して上向きに伸長した形状で配置され、底面１５０１及び上面１５０３を備える。また、制御ゲート電極１５０ａは、ワードラインの一部として利用されうる。   The control gate electrode 150a is formed so as to surround the side wall 1202 of the semiconductor pillar 120 at least once. The control gate electrode 150a is arranged in a shape extending upward with respect to one surface of the substrate 105, and includes a bottom surface 1501 and a top surface 1503. The control gate electrode 150a can be used as a part of the word line.

電荷保存層１４０ａは、制御ゲート電極１５０ａと半導体柱１２０との間に介在されうる。トンネリング絶縁層１３５ａは、半導体柱１２０と電荷保存層１４０ａとの間に介在されうる。ブロッキング絶縁層１４５ａは、電荷保存層１４０ａと制御ゲート電極１５０ａとの間に介在されうる。   The charge storage layer 140a may be interposed between the control gate electrode 150a and the semiconductor pillar 120. The tunneling insulating layer 135a may be interposed between the semiconductor pillar 120 and the charge storage layer 140a. The blocking insulating layer 145a may be interposed between the charge storage layer 140a and the control gate electrode 150a.

トンネリング絶縁層１３５ａ、電荷保存層１４０ａ及び／またはブロッキング絶縁層１４５ａは、半導体柱１２０の側壁１２０２を取り囲むように形成される。さらに、トンネリング絶縁層１３５ａ、電荷保存層１４０ａ及び／またはブロッキング絶縁層１４５ａは、制御ゲート電極１５０ａの底面１５０１及び上面１５０３を覆うようにさらに伸長される。なお、本発明の範囲は、上述した積層構造に制限されず、トンネリング絶縁層１３５ａ、電荷保存層１４０ａ及びブロッキング絶縁層１４５ａの積層構造は多様に変形されうる。   The tunneling insulating layer 135a, the charge storage layer 140a, and / or the blocking insulating layer 145a are formed so as to surround the sidewall 1202 of the semiconductor pillar 120. Further, the tunneling insulating layer 135a, the charge storage layer 140a, and / or the blocking insulating layer 145a are further extended to cover the bottom surface 1501 and the top surface 1503 of the control gate electrode 150a. Note that the scope of the present invention is not limited to the above-described stacked structure, and the stacked structure of the tunneling insulating layer 135a, the charge storage layer 140a, and the blocking insulating layer 145a can be variously modified.

トンネリング絶縁層１３５ａ及びブロッキング絶縁層１４５ａは、例えば、酸化膜、窒化膜または高誘電率膜を備える。高誘電率膜とは、酸化膜及び窒化膜より誘電定数の大きい絶縁膜を称する。電荷保存層１４０ａは、電荷トラップの可能な物質を含む。電荷保存層１４０ａは、例えば、窒化膜、ドット構造及びナノクリスタル構造を備える。ドット構造及びナノクリスタル構造は、導電層、例えば、金属またはシリコンの微細構造を備える。   The tunneling insulating layer 135a and the blocking insulating layer 145a include, for example, an oxide film, a nitride film, or a high dielectric constant film. A high dielectric constant film refers to an insulating film having a larger dielectric constant than oxide and nitride films. The charge storage layer 140a includes a substance capable of charge trapping. The charge storage layer 140a includes, for example, a nitride film, a dot structure, and a nanocrystal structure. The dot structure and the nanocrystal structure comprise a conductive layer, for example a metal or silicon microstructure.

ビットライン電極１６０は、コンタクトプラグ１５５を利用して第２ドーピング層１３０に電気的に連結されうる。例えば、コンタクトプラグ１５５は第２ドーピング層１３０上に配置され、ビットライン電極１６０はコンタクトプラグ１５５上に配置されうる。   The bit line electrode 160 may be electrically connected to the second doping layer 130 using the contact plug 155. For example, the contact plug 155 may be disposed on the second doping layer 130 and the bit line electrode 160 may be disposed on the contact plug 155.

前述した不揮発性メモリ素子１００は、データ記録媒体に利用されうる。データプログラムは、トンネリングまたはチャンネル熱電子注入（Ｃｈａｎｎｅｌ Ｈｏｔ Ｅｌｅｃｔｒｏｎ Ｉｎｊｅｃｔｉｏｎ；ＣＨＥＩ）を利用して電荷保存層１４０ａに電荷を保存させて行えうる。消去動作は、トンネリングを利用して電荷保存層１４０ａの電荷を除去するように行われうる。   The non-volatile memory device 100 described above can be used as a data recording medium. The data program can be performed by storing charges in the charge storage layer 140a using tunneling or channel hot electron injection (CHEI). The erase operation may be performed so as to remove charges from the charge storage layer 140a using tunneling.

本実施形態の不揮発性メモリ素子１００において、電荷の導電通路であるチャンネルは、半導体柱１２０に沿って垂直に形成されうる。したがって、半導体柱１２０の高さを調節することによってチャンネル長を容易に長くすることができる。その結果、いわゆる短チャンネル効果が抑制されうる。また、半導体柱１２０の底面１２０１の直径または幅を縮めることによって、基板１０５上の集積度を高めることができる。したがって、不揮発性メモリ素子１００は、集積度が高くなれば短チャンネル効果を抑制できる。したがって、本実施形態の不揮発性メモリ素子１００は、集積度が高くなれば短チャンネル効果が顕著になる通例的な平面型構造と比較されうる。   In the nonvolatile memory device 100 according to the present embodiment, a channel that is a conductive path for electric charge may be formed vertically along the semiconductor pillar 120. Therefore, the channel length can be easily increased by adjusting the height of the semiconductor pillar 120. As a result, the so-called short channel effect can be suppressed. In addition, the degree of integration on the substrate 105 can be increased by reducing the diameter or width of the bottom surface 1201 of the semiconductor pillar 120. Therefore, the non-volatile memory device 100 can suppress the short channel effect as the integration degree increases. Therefore, the non-volatile memory device 100 of the present embodiment can be compared with a conventional planar structure in which the short channel effect becomes more significant as the degree of integration increases.

さらに、半導体柱１２０の高さを調節することによって、これを取り囲んでいる電荷保存層１４０ａの面積を大きくすることができる。電荷保存層１４０ａの面積が大きくなるにつれて、保存できる電荷の量が増大する。これにより、データプログラム及びリテンション特性が改善されて、不揮発性メモリ素子１００の動作信頼性を高めることができる。さらに、電荷保存層１４０ａを局部に分けてデータプログラムを行うマルチビット動作の信頼性が高まりうる。   Further, by adjusting the height of the semiconductor pillar 120, the area of the charge storage layer 140a surrounding the semiconductor pillar 120 can be increased. As the area of the charge storage layer 140a increases, the amount of charge that can be stored increases. As a result, the data program and the retention characteristics are improved, and the operation reliability of the nonvolatile memory device 100 can be enhanced. Furthermore, the reliability of the multi-bit operation in which the charge storage layer 140a is locally divided to perform data programming can be improved.

図４ないし図９は、本発明の一実施形態による不揮発性メモリ素子の製造方法を示す断面図である。   4 to 9 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

図４を参照すれば、まず、基板１０５上に第１導電型の第１ドーピング層１１５を形成する。例えば、基板１０５に浅いトレンチ構造の素子分離膜１１０を形成して第１ドーピング層１１５を限定する。素子分離膜１１０の形成前または形成後に、第１ドーピング層１１５は、高濃度の第１導電型の不純物でドーピングされうる。   Referring to FIG. 4, first, a first conductivity type first doping layer 115 is formed on a substrate 105. For example, the first doping layer 115 is limited by forming a shallow trench isolation device isolation layer 110 on the substrate 105. The first doping layer 115 may be doped with a high-concentration first conductivity type impurity before or after the isolation layer 110 is formed.

本発明の他の実施形態で、第１ドーピング層１１５は、エピタキシャル蒸着法を利用して形成してもよい。例えば、基板１０５上に素子分離膜１１０を形成し、次いで、素子分離膜１１０から露出された基板１０５の表面から第１ドーピング層１１５を成長させうる。第１ドーピング層１１５は、成長中または成長後に高濃度の第１導電型の不純物でドーピングされうる。   In other embodiments of the present invention, the first doping layer 115 may be formed using an epitaxial deposition method. For example, the device isolation layer 110 may be formed on the substrate 105, and then the first doping layer 115 may be grown from the surface of the substrate 105 exposed from the device isolation layer 110. The first doping layer 115 may be doped with a high-concentration first conductivity type impurity during or after the growth.

図５を参照すれば、第２導電型の半導体柱１２０は、第１ドーピング層１１５から基板１０５の一面に対して上向きに伸長して形成される。半導体柱１２０は、例えば、第１ドーピング層１１５上にエピタキシャル蒸着法を利用して成長できる。半導体柱１２０は、成長と同時にまたはその成長後に低濃度の第２導電型の不純物でドーピングされうる。   Referring to FIG. 5, the second conductivity type semiconductor pillar 120 is formed to extend upward from the first doping layer 115 with respect to one surface of the substrate 105. The semiconductor pillar 120 can be grown on the first doping layer 115 using an epitaxial deposition method, for example. The semiconductor pillar 120 may be doped with a low-concentration second conductivity type impurity simultaneously with or after the growth.

エピタキシャル蒸着法を利用すれば、半導体柱１２０は、素子分離膜１１０からは成長せず、第１ドーピング層１１５から選択的に成長できる。ただし、エピタキシャル蒸着法による場合にも側面方向への成長は可能なために、半導体柱１２０は、上へ行くほど幅または直径の大きい放射形構造でありうる。しかし、蒸着条件を制御することによって、半導体柱１２０の形態は多様に変形されうる。   If the epitaxial deposition method is used, the semiconductor pillar 120 can be selectively grown from the first doping layer 115 without growing from the element isolation film 110. However, since the growth in the lateral direction is possible even in the case of the epitaxial deposition method, the semiconductor pillar 120 may have a radial structure whose width or diameter increases toward the top. However, the shape of the semiconductor pillar 120 can be variously modified by controlling the deposition conditions.

半導体柱１２０は、例えば、分子ビームエピタクシー（Ｍｏｌｅｃｕｌａｒ Ｂｅａｍ Ｅｐｉｔａｘｙ；ＭＢＥ）法または高真空化学気相蒸着（Ｕｌｔｒａ Ｈｉｇｈ Ｖａｃｕｕｍ Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ：ＵＨＶＣＶＤ）法を利用して半導体物質のナノワイヤー構造に成長できる。   The semiconductor pillar 120 can be grown to a nanowire structure of a semiconductor material using, for example, a molecular beam epitaxy (MBE) method or an ultra high vacuum chemical vapor deposition (UHVCVD) method. .

図６を参照すれば、半導体柱１２０の側壁１２０２上にスペーサ絶縁膜１２５を形成する。スペーサ絶縁膜１２５は、例えば、半導体柱１２０の側壁１２０２を熱酸化させて形成する。他の例として、スペーサ絶縁膜１２５は、半導体柱１２０の側壁１２０２上に酸化膜または窒化膜を形成した後、これを異方性エッチングして形成してもよい。   Referring to FIG. 6, a spacer insulating film 125 is formed on the sidewall 1202 of the semiconductor pillar 120. The spacer insulating film 125 is formed, for example, by thermally oxidizing the side wall 1202 of the semiconductor pillar 120. As another example, the spacer insulating film 125 may be formed by forming an oxide film or a nitride film on the sidewall 1202 of the semiconductor pillar 120 and then anisotropically etching it.

図７を参照すれば、半導体柱１２０上に第１導電型の第２ドーピング層１３０を形成する。半導体柱１２０の上面１２０３は、第２ドーピング層１３０と電気的に連結されうる。第２ドーピング層１３０は、例えば、エピタキシャル蒸着法を利用して半導体柱１２０から成長できる。スペーサ絶縁膜１２５は、半導体柱１２０の側壁１２０２に半導体柱１２０が成長することを回避できる。半導体柱１２０は、成長と同時に、またはその後に高濃度の第１導電型の不純物でドーピングされうる。   Referring to FIG. 7, the second doping layer 130 of the first conductivity type is formed on the semiconductor pillar 120. The upper surface 1203 of the semiconductor pillar 120 may be electrically connected to the second doping layer 130. The second doping layer 130 can be grown from the semiconductor pillar 120 using, for example, an epitaxial deposition method. The spacer insulating film 125 can avoid the semiconductor pillar 120 from growing on the side wall 1202 of the semiconductor pillar 120. The semiconductor pillar 120 may be doped with a high-concentration first-conductivity type impurity simultaneously with or after the growth.

第２ドーピング層１３０は、半導体柱１２０の上面１２０３を覆う。第２ドーピング層１３０は、半導体柱１２０の上面１２０３から上へ行くほどその幅または直径が大きくなる。したがって、第２ドーピング層１３０の幅または直径は、半導体柱１２０及び第１ドーピング層１１５の幅または直径より大きい。   The second doping layer 130 covers the upper surface 1203 of the semiconductor pillar 120. The width or diameter of the second doping layer 130 increases as it goes upward from the upper surface 1203 of the semiconductor pillar 120. Accordingly, the width or diameter of the second doping layer 130 is larger than the width or diameter of the semiconductor pillar 120 and the first doping layer 115.

図８を参照すれば、第２ドーピング層１３０及び半導体柱１２０を取り囲むように第１物質層１３５、第２物質層１４０、第３物質層１４５、及び第４物質層１５０を順に形成する。第１物質層１３５及び第３物質層１４５は、例えば、絶縁層であって、酸化膜、窒化膜または高誘電率膜を含む。第２物質層１４０は、電荷トラップの可能な窒化膜、ドット構造またはナノクリスタル構造で形成される。第４物質層１５０は、導電層、例えば、ポリシリコン、金属、または金属シリサイドを含む。   Referring to FIG. 8, a first material layer 135, a second material layer 140, a third material layer 145, and a fourth material layer 150 are sequentially formed to surround the second doping layer 130 and the semiconductor pillar 120. The first material layer 135 and the third material layer 145 are, for example, insulating layers and include an oxide film, a nitride film, or a high dielectric constant film. The second material layer 140 is formed of a nitride film, a dot structure, or a nanocrystal structure capable of charge trapping. The fourth material layer 150 includes a conductive layer, for example, polysilicon, metal, or metal silicide.

この実施形態で、第４物質層１５０は、半導体柱１２０の周辺全体を覆うように十分厚く形成される。しかし、本発明の他の実施形態において、第４物質層１５０は、半導体柱１２０を取り囲むように適切な厚さに形成できる。   In this embodiment, the fourth material layer 150 is formed to be sufficiently thick so as to cover the entire periphery of the semiconductor pillar 120. However, in another embodiment of the present invention, the fourth material layer 150 may be formed to an appropriate thickness so as to surround the semiconductor pillar 120.

図９を参照すれば、第２ドーピング層１３０上の第１物質層１３５、第２物質層１４０、第３物質層１４５及び第４物質層１５０を除去して、トンネリング絶縁層１３５ａ、電荷保存層１４０ａ、ブロッキング絶縁層１４５ａ及び制御ゲート電極１５０ａをそれぞれ形成する。例えば、第２ドーピング層１３０が露出されるまで第１物質層１３５、第２物質層１４０、第３物質層１４５及び第４物質層１５０を平坦化する。平坦化は、化学的機械的平坦化（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｌａｎａｒｉｚａｔｉｏｎ：ＣＭＰ）法またはエッチバックを利用できる。   Referring to FIG. 9, the first material layer 135, the second material layer 140, the third material layer 145, and the fourth material layer 150 on the second doping layer 130 are removed to form a tunneling insulating layer 135a and a charge storage layer. 140a, a blocking insulating layer 145a, and a control gate electrode 150a are formed. For example, the first material layer 135, the second material layer 140, the third material layer 145, and the fourth material layer 150 are planarized until the second doping layer 130 is exposed. As the planarization, a chemical mechanical planarization (CMP) method or an etch back can be used.

次いで、マスクパターンを利用してトンネリング絶縁層１３５ａ、電荷保存層１４０ａ、ブロッキング絶縁層１４５ａ及び制御ゲート電極１５０ａをパターニングする。これにより、トンネリング絶縁層１３５ａ、電荷保存層１４０ａ、ブロッキング絶縁層１４５ａ及び制御ゲート電極１５０ａは、半導体柱１２０を取り囲み、第２ドーピング層１３０下に限定されうる。   Next, the tunneling insulating layer 135a, the charge storage layer 140a, the blocking insulating layer 145a, and the control gate electrode 150a are patterned using a mask pattern. Accordingly, the tunneling insulating layer 135a, the charge storage layer 140a, the blocking insulating layer 145a, and the control gate electrode 150a may surround the semiconductor pillar 120 and be limited under the second doping layer 130.

本発明の他の実施形態で、トンネリング絶縁層１３５ａ、電荷保存層１４０ａ、ブロッキング絶縁層１４５ａ及び制御ゲート電極１５０ａは、第２ドーピング層１３０をエッチングマスクとしてエッチングされてもよい。この場合、トンネリング絶縁層１３５ａ、電荷保存層１４０ａ、ブロッキング絶縁層１４５ａ及び制御ゲート電極１５０ａは、半導体柱１２０を取り囲むシェル構造を有してもよい。   In other embodiments of the present invention, the tunneling insulating layer 135a, the charge storage layer 140a, the blocking insulating layer 145a, and the control gate electrode 150a may be etched using the second doping layer 130 as an etching mask. In this case, the tunneling insulating layer 135a, the charge storage layer 140a, the blocking insulating layer 145a, and the control gate electrode 150a may have a shell structure surrounding the semiconductor pillar 120.

次いで、第２ドーピング層１３０上にコンタクトプラグ１５５を形成する。次いで、コンタクトプラグ１５５上にビットライン電極１６０を形成する。コンタクトプラグ１５５及びビットライン電極１６０は、導電層、例えば、ポリシリコン、金属または金属シリサイドを含む。   Next, a contact plug 155 is formed on the second doping layer 130. Next, the bit line electrode 160 is formed on the contact plug 155. The contact plug 155 and the bit line electrode 160 include a conductive layer, for example, polysilicon, metal, or metal silicide.

次いで、当業者に周知のように、不揮発性メモリ素子を完成できる。   The non-volatile memory device can then be completed as is well known to those skilled in the art.

以下では、図１０ないし図１３を参照して、本発明の実施形態による半導体パッケージ２００ａ、２００ｂ、２００ｃ、及び２００ｄを説明する。なお、半導体チップ２０５は、図１ないし図３の不揮発性メモリ素子１００に対応する。   Hereinafter, semiconductor packages 200a, 200b, 200c, and 200d according to embodiments of the present invention will be described with reference to FIGS. The semiconductor chip 205 corresponds to the nonvolatile memory element 100 of FIGS. 1 to 3.

図１０を参照すれば、半導体チップ２０５は、ソルダーバンプ２１０を利用して基板２２０に接合される。一つ以上のソルダーボール２３０は、半導体チップ２０５の反対側基板２２０に付着される。ソルダーボール２３０は、半導体チップ２０５と電気的に連結されて外部端子として機能する。モールディング材２４０は、半導体チップ２０５を覆うように基板２２０上に形成される。このような半導体パッケージ２００ａは、フリップチップＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）形態と呼ばれうる。   Referring to FIG. 10, the semiconductor chip 205 is bonded to the substrate 220 using solder bumps 210. One or more solder balls 230 are attached to the opposite substrate 220 of the semiconductor chip 205. The solder ball 230 is electrically connected to the semiconductor chip 205 and functions as an external terminal. The molding material 240 is formed on the substrate 220 so as to cover the semiconductor chip 205. Such a semiconductor package 200a may be called a flip chip BGA (Ball Grid Array) form.

他の例として、ソルダーバンプ２１０が形成されている半導体チップ２０５を電子装置の主基板に直ちに実装して、ウェーハレベルパッケージ（Ｗａｆｅｒ Ｌｅｖｅｌ Ｐａｃｋａｇｅ；ＷＬＰ）を具現してもよい。   As another example, the semiconductor chip 205 on which the solder bumps 210 are formed may be immediately mounted on the main substrate of the electronic device to implement a wafer level package (WLP).

図１１を参照すれば、半導体チップ２０５と基板２２０とを、ワイヤー２１５を利用して連結できる。ソルダーボール２３０は、半導体チップ２０５が反対側基板２２０に連結されており、したがって、半導体チップ２０５はソルダーボール２３０と電気的に連結されうる。このような半導体パッケージ２００ｂはＢＧＡ形態と呼ばれうる。   Referring to FIG. 11, the semiconductor chip 205 and the substrate 220 can be connected using the wire 215. In the solder ball 230, the semiconductor chip 205 is connected to the opposite substrate 220, and thus the semiconductor chip 205 can be electrically connected to the solder ball 230. Such a semiconductor package 200b can be referred to as a BGA configuration.

図１２を参照すれば、複数の半導体チップ２０５を基板２２０上に積層してＭＣＰ（Ｍｕｌｔｉ Ｃｈｉｐ Ｐａｃｋａｇｅ）形態の半導体パッケージ２００ｃを形成できる。半導体チップ２０５はいずれも同じ構造または相異なる構造を持つ。例えば、半導体チップ２０５のうち、一部のみ上述した不揮発性メモリ素子１００と同じ構造を持ち、他の半導体チップ２０５は異なる構造を有することができる。   Referring to FIG. 12, a plurality of semiconductor chips 205 may be stacked on a substrate 220 to form a semiconductor package 200c in the form of an MCP (Multi Chip Package). All of the semiconductor chips 205 have the same structure or different structures. For example, only a part of the semiconductor chip 205 may have the same structure as the above-described nonvolatile memory element 100, and the other semiconductor chips 205 may have different structures.

図１３を参照すれば、基板２２０上に複数の半導体チップ２０５を積層し、半導体チップ２０５に貫通通路２１７を形成しての積層形態の半導体パッケージ２００ｄを形成できる。貫通通路２１７を通じて、半導体チップ２０５は、基板２２０を経由してソルダーボール２３０に電気的に連結されうる。   Referring to FIG. 13, a stacked semiconductor package 200 d in which a plurality of semiconductor chips 205 are stacked on a substrate 220 and a through passage 217 is formed in the semiconductor chip 205 can be formed. The semiconductor chip 205 can be electrically connected to the solder ball 230 via the substrate 220 through the through passage 217.

図１４は、本発明の一実施形態によるカード３００を示す概略図である。   FIG. 14 is a schematic diagram illustrating a card 300 according to an embodiment of the present invention.

図１４を参照すれば、制御器３１０とメモリ３２０は電気的な信号を交換するように配置されうる。例えば、制御器３１０から命令を下せば、メモリ３２０はデータを伝送する。メモリ３２０は、図１ないし図３の不揮発性メモリ素子１００に対応できる。このようなカード３００は、マルチメディアカード（Ｍｕｌｔｉ Ｍｅｄｉａ Ｃａｒｄ；ＭＭＣ）または保安デジタル（Ｓｅｃｕｒｅ Ｄｉｇｉｔａｌ Ｃａｒｄ；ＳＤ）カードのようなメモリ装置に利用できる。   Referring to FIG. 14, the controller 310 and the memory 320 may be arranged to exchange electrical signals. For example, if an instruction is issued from the controller 310, the memory 320 transmits data. The memory 320 can correspond to the nonvolatile memory device 100 of FIGS. Such a card 300 can be used in a memory device such as a multimedia card (MMC) or a secure digital card (SD) card.

不揮発性メモリ素子１００は、例えば、チップ形態であって、ワイヤーボンディングまたはソルダーバンプを利用して主基板と連結されるか、または制御器３１０に直接連結されうる。他の例として、不揮発性メモリ素子１００が前述した半導体パッケージ２００ａ、２００ｂ、２００ｃ、２００ｄの一つまたはこれと類似した形態で製作されて、主基板に実装されうる。   The nonvolatile memory device 100 may be in the form of a chip, for example, and may be connected to the main substrate using wire bonding or solder bumps, or may be directly connected to the controller 310. As another example, the non-volatile memory device 100 may be manufactured in one of the semiconductor packages 200a, 200b, 200c, and 200d described above or a similar form and mounted on the main substrate.

図１５は、本発明の一実施形態によるシステム４００を示す概略的なブロック図である。   FIG. 15 is a schematic block diagram illustrating a system 400 according to one embodiment of the invention.

図１５を参照すれば、プロセッサー４１０、入／出力装置４２０及びメモリ４３０は、バス４４０を利用して互いにデータ通信できる。プロセッサー４１０はプログラムを実行し、システム４００を制御する役割を担う。入／出力装置４２０は、システム４００のデータを入力または出力するところに利用できる。メモリ４３０は、図１ないし図３の不揮発性メモリ素子１００に対応できる。メモリ４３０は、例えば、プロセッサー４１０の動作のためのコード及びデータを保存する。   Referring to FIG. 15, the processor 410, the input / output device 420, and the memory 430 can communicate data with each other using the bus 440. The processor 410 is responsible for executing programs and controlling the system 400. The input / output device 420 can be used to input or output data of the system 400. The memory 430 may correspond to the nonvolatile memory device 100 of FIGS. The memory 430 stores code and data for the operation of the processor 410, for example.

さらに、システム４００は、入／出力装置４２０を利用して外部装置、例えば、パソコンまたはネットワークに連結されて、相互にデータ交換をすることができる。   Further, the system 400 may be connected to an external device such as a personal computer or a network using the input / output device 420 to exchange data with each other.

このようなシステム４００は、例えば、携帯電話、ＭＰ３プレーヤー、ナビゲーション、固状ディスク（Ｓｏｌｉｄ Ｓｔａｔｅ Ｄｉｓｋ；ＳＳＤ）または家電製品に利用できる。   Such a system 400 can be used, for example, for a mobile phone, an MP3 player, navigation, a solid state disk (SSD), or a home appliance.

発明の特定実施形態についての以上の説明は例示及び説明を目的として提供された。本発明は前記実施形態に限定されず、本発明の技術的思想内で当業者によって前記実施形態を組み合わせて実施するなど、いろいろな多くの修正及び変更が可能であるということは明らかである。   The foregoing descriptions of specific embodiments of the invention have been presented for purposes of illustration and description. The present invention is not limited to the above-described embodiment, and it is apparent that various modifications and changes can be made by those skilled in the art within the technical idea of the present invention.

本発明は、メモリ関連の技術分野に好適に用いられる。   The present invention is suitably used in the technical field related to memory.

本発明の一実施形態による不揮発性メモリ素子を示す部分切断された斜視図である。1 is a partially cut perspective view illustrating a nonvolatile memory device according to an embodiment of the present invention. 図１の不揮発性メモリ素子のＩＩ−ＩＩ’線の断面図である。It is sectional drawing of the II-II 'line | wire of the non-volatile memory element of FIG. 図１の不揮発性メモリ素子のＩＩＩ−ＩＩＩ’線の断面図である。FIG. 3 is a cross-sectional view taken along the line III-III ′ of the nonvolatile memory element of FIG. 1. 本発明の一実施形態による不揮発性メモリ素子の製造方法を示す断面図である。1 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device according to an embodiment of the present invention. 本発明の一実施形態による不揮発性メモリ素子の製造方法を示す断面図である。1 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device according to an embodiment of the present invention. 本発明の一実施形態による不揮発性メモリ素子の製造方法を示す断面図である。1 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device according to an embodiment of the present invention. 本発明の一実施形態による不揮発性メモリ素子の製造方法を示す断面図である。1 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device according to an embodiment of the present invention. 本発明の一実施形態による不揮発性メモリ素子の製造方法を示す断面図である。1 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device according to an embodiment of the present invention. 本発明の一実施形態による不揮発性メモリ素子の製造方法を示す断面図である。1 is a cross-sectional view illustrating a method for manufacturing a nonvolatile memory device according to an embodiment of the present invention. 本発明の実施形態による半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package by embodiment of this invention. 本発明の実施形態による半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package by embodiment of this invention. 本発明の実施形態による半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package by embodiment of this invention. 本発明の実施形態による半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package by embodiment of this invention. 本発明の一実施形態によるカードを示す概略的なブロック図である。1 is a schematic block diagram illustrating a card according to an embodiment of the present invention. 本発明の一実施形態によるシステムを示す概略的なブロック図である。1 is a schematic block diagram illustrating a system according to an embodiment of the present invention.

符号の説明Explanation of symbols

１００ 不揮発性メモリ素子、
１０５ 基板、
１１０ 素子分離膜、
１１５ 第１ドーピング層、
１２０ 半導体柱、
１３０ 第２ドーピング層、
１３５ａ トンネリング絶縁層、
１４０ａ 電荷保存層、
１４５ａ ブロッキング絶縁層、
１５０ａ 制御ゲート電極、
１５５ コンタクトプラグ、
１６０ ビットライン電極。 100 non-volatile memory device,
105 substrates,
110 element isolation membrane,
115 first doping layer;
120 semiconductor pillar,
130 second doping layer;
135a Tunneling insulating layer,
140a charge storage layer,
145a blocking insulating layer,
150a control gate electrode,
155 contact plug,
160 Bit line electrode.

Claims (26)

基板上に形成され、第１導電型の第１ドーピング層と、
前記第１ドーピング層から前記基板の一面に対して上向きに伸長し、前記第１導電型と逆の導電性を有する第２導電型の半導体柱と、
前記半導体柱の側壁を一回り取り囲む制御ゲート電極と、
前記半導体柱と前記制御ゲート電極との間に介在される電荷保存層と、
前記半導体柱と電気的に連結されるように前記半導体柱上に配置され、前記第１導電型の第２ドーピング層と、
を備えることを特徴とする不揮発性メモリ素子。 A first doping layer of a first conductivity type formed on the substrate;
A semiconductor column of a second conductivity type extending upward from the first doping layer with respect to one surface of the substrate and having a conductivity opposite to the first conductivity type;
A control gate electrode surrounding the side wall of the semiconductor pillar once;
A charge storage layer interposed between the semiconductor pillar and the control gate electrode;
A second doping layer of the first conductivity type disposed on the semiconductor pillar to be electrically connected to the semiconductor pillar;
A non-volatile memory device comprising: 前記第１ドーピング層は、前記半導体柱の底面の中心部を覆うことを特徴とする請求項１に記載の不揮発性メモリ素子。   The nonvolatile memory device of claim 1, wherein the first doping layer covers a central portion of a bottom surface of the semiconductor pillar. 前記第１ドーピング層は、前記半導体柱の底面全体を覆うことを特徴とする請求項１に記載の不揮発性メモリ素子。   The nonvolatile memory device of claim 1, wherein the first doping layer covers the entire bottom surface of the semiconductor pillar. 前記第１ドーピング層の側壁を取り囲むように、前記基板上に形成された素子分離膜をさらに備えることを特徴とする請求項１に記載の不揮発性メモリ素子。   The non-volatile memory device of claim 1, further comprising an element isolation film formed on the substrate so as to surround a side wall of the first doping layer. 前記第１ドーピング層は、前記基板の一部分に前記第１導電型の不純物がドーピングされて限定されることを特徴とする請求項１に記載の不揮発性メモリ素子。   The nonvolatile memory device of claim 1, wherein the first doping layer is limited by doping a portion of the substrate with the impurity of the first conductivity type. 前記第１ドーピング層は、前記基板上のエピタキシャル層として提供されることを特徴とする請求項１に記載の不揮発性メモリ素子。   The nonvolatile memory device of claim 1, wherein the first doping layer is provided as an epitaxial layer on the substrate. 前記第２ドーピング層の幅は、前記第１ドーピング層の幅より広いことを特徴とする請求項１に記載の不揮発性メモリ素子。   The nonvolatile memory device of claim 1, wherein a width of the second doping layer is wider than a width of the first doping layer. 前記電荷保存層は、前記半導体柱を取り囲み、前記制御ゲート電極の上面及び底面を覆うように伸長して形成されることを特徴とする請求項７に記載の不揮発性メモリ素子。   The nonvolatile memory device of claim 7, wherein the charge storage layer is formed to extend so as to surround the semiconductor pillar and cover an upper surface and a bottom surface of the control gate electrode. 前記電荷保存層と前記半導体柱との間のトンネリング絶縁層、及び前記電荷保存層と前記制御ゲート電極との間のブロッキング絶縁層をさらに備えることを特徴とする請求項１に記載の不揮発性メモリ素子。   The nonvolatile memory according to claim 1, further comprising a tunneling insulating layer between the charge storage layer and the semiconductor pillar, and a blocking insulating layer between the charge storage layer and the control gate electrode. element. 前記トンネリング絶縁層及び前記ブロッキング絶縁層は、前記半導体柱を取り囲み、前記制御ゲート電極の上面及び底面を覆うように伸長して形成されることを特徴とする請求項９に記載の不揮発性メモリ素子。   The nonvolatile memory device of claim 9, wherein the tunneling insulating layer and the blocking insulating layer are formed to extend so as to surround the semiconductor pillar and cover an upper surface and a bottom surface of the control gate electrode. . 前記半導体柱はナノワイヤー構造からなることを特徴とする請求項１に記載の不揮発性メモリ素子。   The nonvolatile memory device of claim 1, wherein the semiconductor pillar has a nanowire structure. 前記第２ドーピング層と電気的に連結されたビットライン電極をさらに備えることを特徴とする請求項１に記載の不揮発性メモリ素子。   The nonvolatile memory device of claim 1, further comprising a bit line electrode electrically connected to the second doping layer. 基板上に形成され、第１導電型の第１ドーピング層と、
前記第１ドーピング層から前記基板の一面に対して上向きに伸長し、前記第１導電型と逆の導電性を有する第２導電型の半導体柱と、
前記半導体柱の側壁を一回り取り囲む制御ゲート電極と、
前記半導体柱と前記制御ゲート電極との間に介在され、前記制御ゲート電極の上面及び底面を覆う電荷保存層と、
前記半導体柱と電気的に連結されるように前記半導体柱上に配置され、前記第１導電型の第２ドーピング層と、
を備えることを特徴とする不揮発性メモリ素子。 A first doping layer of a first conductivity type formed on the substrate;
A semiconductor column of a second conductivity type extending upward from the first doping layer with respect to one surface of the substrate and having a conductivity opposite to the first conductivity type;
A control gate electrode surrounding the side wall of the semiconductor pillar once;
A charge storage layer interposed between the semiconductor pillar and the control gate electrode and covering an upper surface and a bottom surface of the control gate electrode;
A second doping layer of the first conductivity type disposed on the semiconductor pillar to be electrically connected to the semiconductor pillar;
A non-volatile memory device comprising: 前記第１ドーピング層は、前記半導体柱の底面を覆うことを特徴とする請求項１３に記載の不揮発性メモリ素子。   The nonvolatile memory device of claim 13, wherein the first doping layer covers a bottom surface of the semiconductor pillar. 基板上に第１導電型の第１ドーピング層を形成する工程と、
前記第１ドーピング層から前記基板の一面に対して上向きに伸長するように、前記第１導電型と逆の導電性を有する第２導電型の半導体柱を形成する工程と、
前記半導体柱と電気的に連結されるように前記半導体柱上に、前記第１導電型の第２ドーピング層を形成する工程と、
前記半導体柱の側壁を一回り取り囲む電荷保存層を形成する工程と、
前記半導体柱の反対側の前記電荷保存層上に制御ゲート電極を形成する工程と、
を含むことを特徴とする不揮発性メモリ素子の製造方法。 Forming a first doping layer of a first conductivity type on a substrate;
Forming a semiconductor column of a second conductivity type having conductivity opposite to the first conductivity type so as to extend upward from the first doping layer with respect to one surface of the substrate;
Forming a second doping layer of the first conductivity type on the semiconductor pillar to be electrically connected to the semiconductor pillar;
Forming a charge storage layer surrounding the side wall of the semiconductor pillar once;
Forming a control gate electrode on the charge storage layer opposite the semiconductor pillar;
A method for manufacturing a non-volatile memory device, comprising: 前記第１ドーピング層は、前記基板の一部分に前記第１導電型の不純物をドーピングして形成することを特徴とする請求項１５に記載の不揮発性メモリ素子の製造方法。   16. The method of claim 15, wherein the first doping layer is formed by doping the first conductivity type impurity into a part of the substrate. 前記第１ドーピング層は、前記基板上にエピタキシャル蒸着法を利用して形成することを特徴とする請求項１５に記載の不揮発性メモリ素子の製造方法。   16. The method of claim 15, wherein the first doping layer is formed on the substrate using an epitaxial deposition method. 前記第１ドーピング層は、前記基板上の素子分離膜間に限定することを特徴とする請求項１５に記載の不揮発性メモリ素子の製造方法。   The method of claim 15, wherein the first doping layer is limited between element isolation layers on the substrate. 前記半導体柱は、ナノワイヤー構造で形成することを特徴とする請求項１５に記載の不揮発性メモリ素子の製造方法。   The method of claim 15, wherein the semiconductor pillar is formed with a nanowire structure. 前記半導体柱は、前記第１ドーピング層上にエピタキシャル蒸着法を利用して形成することを特徴とする請求項１９に記載の不揮発性メモリ素子の製造方法。   The method of claim 19, wherein the semiconductor pillar is formed on the first doping layer using an epitaxial deposition method. 前記第２ドーピング層を形成する前に、前記半導体柱の側壁を取り囲むスペーサ絶縁膜を形成する工程と、
前記第２ドーピング層を形成する工程後、前記スペーサ絶縁膜を除去する工程と、
をさらに含むことを特徴とする請求項１５に記載の不揮発性メモリ素子の製造方法。 Forming a spacer insulating film surrounding a side wall of the semiconductor pillar before forming the second doping layer;
Removing the spacer insulating film after the step of forming the second doping layer;
The method of manufacturing a nonvolatile memory device according to claim 15, further comprising: 前記スペーサ絶縁膜は、前記半導体柱の側壁を熱酸化させて形成することを特徴とする請求項２１に記載の不揮発性メモリ素子の製造方法。   The method of claim 21, wherein the spacer insulating film is formed by thermally oxidizing a side wall of the semiconductor pillar. 前記電荷保存層は、前記第２ドーピング層及び前記半導体柱を覆うように形成した後、平坦化及び異方性エッチングを利用して前記半導体柱を取り囲み、前記制御ゲート電極の上面及び底面を覆うように限定することを特徴とする請求項１５に記載の不揮発性メモリ素子の製造方法。   The charge storage layer is formed to cover the second doping layer and the semiconductor pillar, and then surrounds the semiconductor pillar using planarization and anisotropic etching, and covers the top and bottom surfaces of the control gate electrode. The method of manufacturing a nonvolatile memory device according to claim 15, wherein the method is limited as described above. 前記第２ドーピング層を形成する工程後、
前記半導体柱と前記電荷保存層との間に介在されたトンネリング絶縁層を形成する工程と、
前記電荷保存層と前記制御ゲート電極との間に介在されたブロッキング絶縁層を形成する工程と、
をさらに含むことを特徴とする請求項１５に記載の不揮発性メモリ素子の製造方法。 After the step of forming the second doping layer,
Forming a tunneling insulating layer interposed between the semiconductor pillar and the charge storage layer;
Forming a blocking insulating layer interposed between the charge storage layer and the control gate electrode;
The method of manufacturing a nonvolatile memory device according to claim 15, further comprising: 前記トンネリング絶縁層及び前記ブロッキング絶縁層は、前記第２ドーピング層及び前記半導体柱を覆うようにそれぞれ形成した後、平坦化及び異方性エッチングを利用して前記半導体柱を取り囲み、前記制御ゲート電極の上面及び底面を覆うように限定することを特徴とする請求項２４に記載の不揮発性メモリ素子の製造方法。   The tunneling insulating layer and the blocking insulating layer are formed so as to cover the second doping layer and the semiconductor pillar, respectively, and surround the semiconductor pillar using planarization and anisotropic etching, and the control gate electrode 25. The method of manufacturing a nonvolatile memory device according to claim 24, wherein the method is limited to cover the upper surface and the bottom surface of the semiconductor memory device. 請求項１に記載の不揮発性メモリ素子を備え、基板上に付着された半導体チップと、
前記半導体チップの反対側の前記基板に付着され、前記半導体チップに電気的に連結された一つ以上のソルダーボールと、を備えることを特徴とする半導体パッケージ。 A semiconductor chip comprising the non-volatile memory element according to claim 1 and attached on a substrate;
One or more solder balls attached to the substrate on the opposite side of the semiconductor chip and electrically connected to the semiconductor chip.
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