JP2008242870A - Data reading device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data reading device, capable of efficiently reducing data read time without complicating the configuration. <P>SOLUTION: A plurality of look ahead circuits C1, C2 and C3 read ahead data from a predetermined address of a data storage part 5. A selection means 31 selects necessary data from the data read ahead by the look ahead circuits C1, C2 and C3. When the data is selected by the selection means 31, the look ahead circuits C1, C2 and C3 read ahead the following data from the predetermined address of the data storage part 5. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data reading apparatus that shortens a reading time by prefetching data.

  When the programmable controller executes information processing using data such as field device status, measured values, or operation results, the arithmetic processing device such as the MPU performs various calculations, printing, Processing such as data transfer to another computer is executed. In general, a semiconductor memory such as an SRAM or a flash memory is used as a data storage unit for storing data. In general, the arithmetic processing device has the ability to read data at high speed, but the data storage unit cannot cope with the speed, and by providing a delay circuit, the arithmetic processing device until data reading from the data storage unit is completed. There is a case where a method of waiting is used.

  As a technique for reducing the time required for reading data, there is a method using a cache circuit or a prefetch circuit. When the cache circuit is used, the address and data read once are stored in a semiconductor memory that can shorten the read time, and the next time data is read from the same address, not the data storage unit, Reading data from this semiconductor memory shortens the reading time.

On the other hand, the prefetch circuit is used when reading data at consecutive addresses from the data storage unit. For example, after the data of the address value “0x1000” is read, the prefetch circuit reads the data of the next address value “0x1001” while the arithmetic processing device performs other information processing, for example, calculation or communication processing. Store in high-speed semiconductor memory in the prefetch circuit. Next, when the arithmetic processing unit tries to read the data having the address value “0x1001”, the read time is shortened by reading from the prefetch circuit instead of the low-speed data storage unit.
Japanese Patent Application Laid-Open No. 11-282631

  However, when the delay circuit is provided, it takes a long time to read data from the data storage unit, and during that time, the arithmetic processing unit waits for data reading. For this reason, even if an attempt is made to use a high-speed arithmetic processing device, it is impossible to increase the speed of the system.

  The method using the cache circuit is effective when reading from the same address as the past address. However, for example, when the programmable controller reads a measurement value or device information at regular time intervals and performs processing such as transferring this to another device, the data at the same address is not read repeatedly, and the read time is reduced. Cannot be shortened.

  The use of the prefetch circuit is effective when reading data sequentially from successive addresses. However, for example, after reading the measurement data of the address value “0x1000”, the device information of the address value “0x2000” is read, and then the measurement data and device information of the address value “0x1002” and the address value “0x2001” are read. In such a case, the effect is suppressed. Furthermore, in order to cope with such a reading procedure, a complicated mechanism for predicting the address of data to be read next can be prepared, but the circuit configuration becomes large.

  An object of the present invention is to provide a data reading apparatus capable of efficiently reducing the data reading time without complicating the configuration.

A data reading device according to the present invention is a data reading device that shortens a reading time by prefetching data, and includes a plurality of prefetch circuits that prefetch data from a predetermined address of a data storage unit, and data prefetched by the prefetch circuit. Selecting means for selecting necessary data from the above, and when the data is selected by the selecting means, the prefetch circuit prefetches the next data from a predetermined address of the data storage unit. Features.
According to this data reading device, data is pre-read from a predetermined address by a plurality of pre-read circuits, and the pre-read circuit from which data is selected pre-reads the next data from a predetermined address. Reading time can be shortened.

  The address of data prefetched by the prefetch circuit may be defined by an address initial value and an addition value, and the next address may be obtained by adding the addition value to the current address.

  The initial address values given to the individual prefetch circuits may be non-contiguous values.

  The added value may be an integer other than 1.

  According to the data reading device of the present invention, the data is pre-read from a predetermined address by a plurality of pre-reading circuits, and the pre-reading circuit in which the data is selected pre-reads the next data from the predetermined address. Data read time can be shortened.

  Hereinafter, an embodiment of a data reading apparatus according to the present invention will be described with reference to FIGS.

  FIG. 1 is a block diagram showing a configuration of an information processing system using the data reading device of this embodiment, and FIG. 2 is a block diagram showing a configuration of a prefetch circuit. This information processing system is configured using a programmable controller.

  As shown in FIG. 1, a data reading device 100 according to the present embodiment is connected between a CPU 4 as an information processing device and a data storage unit 5 that stores a data group, and data stored in the data storage unit 5. Is provided to the CPU 4 at any time.

  As shown in FIG. 1, the data reading device 100 includes a prefetch circuit C1, a prefetch circuit C2, and a prefetch circuit C3 that prefetch data used by the CPU 4 from the data storage unit 5, respectively, a prefetch circuit C1, a prefetch circuit C2, and a prefetch. A data switching circuit 1 for selecting one data from data read by the circuit C3, an address switching circuit 2 for selecting a read address, and a control unit 3 for controlling the data switching circuit 1 and the address switching circuit 2 And comprising. As shown in FIG. 1, the control unit 3 constitutes a selection unit 31.

  As shown in FIG. 2, the prefetch circuit C1 includes an address FIFO 61 that sequentially stores addresses of data prefetched from the data storage unit 5, a data FIFO 62 that sequentially stores data prefetched from the data storage unit 5, and An address register 63 for storing the address of data prefetched from the data storage unit 5, an adder 64 for adding an address addition value to the address of the address register 63, a storage unit 65 for storing an address initial value, and the above address addition A storage unit 66 that stores values and an address comparator 67 that compares an address stored in the address FIFO 61 with a read address designated by the CPU 4 are provided.

  The initial address value stored in the storage unit 65 indicates the address value of the first data prefetched by the prefetch circuit C1. The address addition value stored in the storage unit 66 indicates the difference between the address values of the data that are sequentially prefetched by the prefetch circuit C1. For example, when the address initial value is “0x1000” and the address addition value is “0x0002”, the prefetch circuit C1 has the address value “0x1000”, the address value “0x1002”, the address value “0x1004”, the address value “0x1006”. Read data in order. By using a complement as an address addition value, the address value can be reduced. For example, when the number of digits of the address is 4 digits in hexadecimal, the one's complement of “0x0002” is “0xfffe”.

  In the prefetch circuit C 1, the address value of the prefetched data is sequentially calculated by the adder 64 and stored in the address register 63. The prefetch circuit C1 prefetches the data stored in the data storage unit 5 using the address value stored in the address register 63 as a read address (read address # 1).

  The read data is stored in the data FIFO 62, and the read address # 1 of the data is stored in the address FIFO 61.

  The prefetch circuit C2 and the prefetch circuit C3 are configured in the same manner as the prefetch circuit C1, and the address initial value and the address addition value are individually set.

  Next, the operation of the data reading device 100 will be described.

  FIG. 3 is a flowchart showing an operation procedure of the control unit 3 of the data reading apparatus 100.

  In step S1 of FIG. 3, the CPU 4 waits for a data read address (read address # 0) to be specified, and then proceeds to step S2. As shown in FIGS. 1 and 2, the read address # 0 specified by the CPU 4 is given to the prefetch circuits C1 to C3, and the read addresses stored in the address FIFO 61 are stored in the address comparator 67 of each prefetch circuit. (Read address # 1, # 2, # 3) is compared with read address # 0. If the two match, an address match signal is output from the address comparator 67.

  Next, in step S2, it is determined whether or not an address match signal is output from the prefetch circuit C1, and if the determination is affirmed, the process proceeds to step S3, and if the determination is negative, the process proceeds to step S4.

  In step S3, the data switching circuit 1 is controlled by outputting an output data control signal from the selection means 31 (FIG. 1), and the read data # 1 of the prefetch circuit C1 is passed to the CPU 4 as the final read data. Further, the address switching circuit 2 is controlled by the output address control signal, and the prefetch circuit C1 is selected. The prefetch circuit C1 shifts to an operation of prefetching data (read data) of the next read address calculated by the adder 64 and stored in the address register 63 from the data storage unit 5.

  After step S3, the process returns to step S1.

  Next, in step S4, it is determined whether or not an address match signal is output from the prefetch circuit C2. If the determination is affirmative, the process proceeds to step S5, and if the determination is negative, the process proceeds to step S6.

  In step S5, the data switching circuit 1 is controlled by outputting an output data control signal from the selection means 31, and the read data # 2 of the prefetch circuit C2 is passed to the CPU 4 as final read data. Further, the address switching circuit 2 is controlled by the output address control signal, and the prefetch circuit C2 is selected. The prefetch circuit C <b> 2 shifts to an operation of prefetching data (read data) of the next read address calculated by the adder 64 and stored in the address register 63 from the data storage unit 5.

  After step S5, the process returns to step S1.

  Next, in step S6, it is determined whether or not an address match signal is output from the prefetch circuit C3. If the determination is affirmative, the process proceeds to step S7, and if the determination is negative, the process proceeds to step S8.

  In step S7, the data switching circuit 1 is controlled by outputting an output data control signal from the selection means 31, and the read data # 3 of the prefetch circuit C3 is passed to the CPU 4 as final read data. Further, the address switching circuit 2 is controlled by the output address control signal, and the prefetch circuit C3 is selected. The prefetch circuit C3 shifts to an operation of prefetching data (read data) of the next read address calculated by the adder 64 and stored in the address register 63 from the data storage unit 5.

  After step S7, the process returns to step S1.

  Next, in step S8, the data switching circuit 1 is controlled by outputting an output data control signal from the selection means 31, the data storage unit 5 and the CPU 4 are connected, and the process returns to step S1. In this case, the CPU 4 reads the read data # 0 of the read address # 0 from the data storage unit 5. The process of step S8 is executed when no address match signal is output from any of the prefetch circuits. In this case, the data read time is defined by the data storage unit 5.

  As described above, according to the data reading device 100 of the present embodiment, while the CPU 4 is executing predetermined information processing, data is prefetched by the prefetch circuits C1 to C3, and data having the same read address is prefetched. In the case of any of C1 to C3, the CPU 4 reads the data from the corresponding prefetch circuit. For this reason, the time required for reading data can be shortened.

  For example, the time for reading data from the data storage unit 5 is 100 ns, and the time for reading data from the prefetch circuits C1 to C3 to the CPU 4 is 10 ns. In addition, the address initial value of the prefetch circuit C1 is “0x1000”, the addition value of the prefetch circuit C1 is “0x0002”, the address initial value of the prefetch circuit C2 is “0x3000”, the addition value of the prefetch circuit C2 is “0xffff”, and the prefetch circuit The initial value of the address of C3 is “0x4000”, and the added value of the prefetch circuit C3 is “0x0001”.

When the CPU 4 reads a total of 6 data in the order of address values “0x1000”, “0x3000”, “0x4000”, “0x1002”, “0x2fff”, “0x4001”, the time required for the CPU 4 to read the data is
6 × 10ns = 60ns
The time when the CPU 4 reads data directly from the data storage unit 5 is 6 × 100 ns = 600 ns
It is greatly shortened compared with.

  The read time of data from the data storage unit 5 in the prefetch circuits C1 to C3 is 100 ns. However, since the CPU 4 usually spends a long time (100 ns or more) for information processing other than data reading, there is virtually no situation where the data prefetching by the prefetch circuits C1 to C3 is not in time for the data read timing of the CPU4. .

Similarly, when reading six data, if there are two prefetch circuits, the time required for the CPU 4 to read the data is
4 × 10ns + 2 × 100ns = 240ns
It becomes.

  Further, in the data reading device 100 of the present embodiment, since an arbitrary initial address value and address addition value can be set in the prefetch circuits C1 to C3, an appropriate prefetch algorithm can be obtained according to the contents of information processing. For example, as the initial address value, discontinuous values that are not continuous can be set for each prefetch circuit. Further, an integer of 2 or more or a negative integer can be given as the address addition value.

  The address initial value and the address addition value can be given as a part of the program or data corresponding to the program, and the user can freely set these values. Since the order of the data read by the information processing of the programmable controller follows the program, the method shown in this embodiment can be said to be more rational than the method of predicting the address of the next read data using a complicated mechanism. .

  As described above, according to the data reading device of the present invention, data is prefetched from a predetermined address by a plurality of prefetch circuits, and the prefetch circuit from which the data is selected Since data is prefetched, the data read time can be shortened.

  The scope of application of the present invention is not limited to the above embodiment. The present invention can be widely applied to a data reading apparatus that shortens the reading time by prefetching data.

The block diagram which shows the structure of the information processing system using the data reading device of one Embodiment. The block diagram which shows the structure of a prefetch circuit. The flowchart which shows the operation | movement procedure of the control part of a data reading device.

Explanation of symbols

5 Data Storage Unit 31 Selection Means 100 Data Reading Device C1, C2, C3 Prefetch Circuit

Claims (4)

In a data readout device that shortens the readout time by prefetching data,
A plurality of prefetch circuits for prefetching data from a predetermined address of the data storage unit;
Selecting means for selecting necessary data from the data pre-read by the pre-reading circuit;
With
When data is selected by the selection means, the prefetch circuit prefetches the next data from a predetermined address of the data storage unit. The address of data prefetched by the prefetch circuit is defined by an address initial value and an addition value, and a next address is obtained by adding the addition value to a current address. 2. The data reading device according to 1. 3. The data reading apparatus according to claim 2, wherein the initial address values given to the individual prefetch circuits are non-contiguous values. The data read device according to claim 2, wherein the added value is an integer other than one.

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