JP2008236831A - Motor drive controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a motor drive controller which can perform more precise motor drive control with lower noise and lower vibration than before. <P>SOLUTION: The motor drive controller 100 includes a means 20 for acquiring the information of a brushless motor 10, a means 30 for generating control data, a means 40 for outputting a sine wave signal, a means 50 for setting an operation mode, and a means 60 for controlling the drive voltage of the brushless motor 10. The sine wave signal output means 40 has a phase synchronization section 70 and a sine wave generator 42, the phase synchronization section 70 suppresses phase variation of an HG signal, i.e. an input signal, by the smoothing characteristics of a PLL circuit, and the sine wave generator 42 outputs a normalization sine wave signal in which disturbance of waveform is suppressed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a motor drive control device that controls driving of a brushless motor having, for example, a plurality of armature windings.

  The brushless motor includes, for example, a three-phase armature winding connected in a star shape, and a permanent magnet arranged so as to surround the armature winding, and a stator having a fixed armature winding side, a permanent The structure is a rotor that rotates on the magnet side, and the rotor is rotated by sequentially applying an alternating voltage to the U-phase, V-phase, and W-phase of the armature winding to generate rotational torque. .

  As a driving method of the brushless motor, a 120-degree rectangular wave energization system in which a constant rectangular wave current is passed through each phase winding by 120 degrees every 60 degrees of electrical angle, or a sine wave current is passed through each phase winding. A sine wave energization method is known. The 120-degree rectangular wave energization method has a problem that vibration and noise are generated because it is driven by a rectangular current, but the sine wave energization method can avoid this problem.

  However, in general, in sine wave energization, since it is necessary to obtain the rotational position of the rotor with a relatively high resolution in order to generate a sine wave, for example, a high-accuracy encoder is provided to increase the manufacturing cost. There was a problem. In order to solve this problem, for example, an inverter device as shown in Patent Document 1 has been proposed.

Patent Document 1 discloses a position detector that detects a rotational position of a rotor and outputs a position signal, and a clock pulse having a frequency multiplied according to a signal change period (corresponding to an electrical angle of 60 degrees) of the position signal. A pulse generation circuit that generates a clock signal, a phase estimation circuit that counts clock pulses based on the edge of the position signal and estimates the rotational phase of the rotor, and an inverter that outputs a sinusoidal current based on the estimated rotational phase A permanent magnet motor can be driven with low vibration and low noise by obtaining a resolution finer than an electrical angle of 60 degrees with a clock pulse having a multiplied frequency.
Japanese Patent No. 3500348

  However, the conventional one disclosed in Patent Document 1 measures the change period of the position signal (corresponding to an electrical angle of 60 degrees), and uses the pulse frequency of 1/32 of the measurement period as the change of the next position signal. It is used during the period (equivalent to the next electrical angle of 60 degrees). As can be easily understood, if the position signal change point shifts due to the position detector placement error, the permanent magnet position error, the magnetization error, or the like, the measurement cycle shifts. In other words, since this deviation differs for each period measurement of the position signal, the frequency of the generated pulse changes every 60 degrees of electrical angle by the deviation. Therefore, if a sine wave is generated using this pulse, the sine wave becomes discontinuous or distorted, which may cause uneven rotation and noise.

  Further, when starting up or intentionally shifting (changing the number of revolutions), the cycle of the position signal changes with time. Therefore, in the next section of the electrical angle of 60 degrees in which the period measurement is reflected, the rotation has already been performed at a period different from that period. Therefore, the frequency and phase shift of the generated pulse is further increased, the generated sine wave shift and distortion are also increased, and there is a risk of step-out.

  Also, when the rotation is very slow compared to the steady state, such as when starting up, the period of the position signal is very long. For example, the period measurement counter overflows, making it difficult to measure the change period of the position signal. It becomes impossible to estimate the rotational phase of the.

  The present invention has been made to solve such a problem, and provides a motor drive control device that can perform precise motor drive control with lower noise and vibration than conventional ones. For the purpose.

  The motor drive control device according to the present invention is a motor drive control device that rotates the rotor by causing a periodic current to flow through an armature winding of a plurality of phases in accordance with the rotational position of the rotor of the motor. Position signal output means for outputting a periodic position signal according to the rotational position of the child, absolute phase information output means for smoothing the position signal and outputting absolute phase information according to the position signal, and the absolute phase And a sine wave drive means for outputting a sine wave drive signal for causing a sine wave current to flow through the plurality of armature windings according to information.

  With this configuration, the motor drive control device of the present invention can suppress the shift of the change point of the position signal with respect to the absolute phase information by smoothing the position signal, so that the rotation unevenness, vibration and Generation of noise can be suppressed. Therefore, the motor drive control device of the present invention can make distortion and discontinuity of the sine wave drive signal smaller than the conventional one, and can perform precise motor drive control with low noise and vibration. it can.

  In the motor drive control device of the present invention, the absolute phase information output means includes a phase synchronization circuit that is phase-synchronized with the position signal, and the phase of the output signal of the phase synchronization circuit and the position signal are phase-synchronized. In the phase synchronization state, the absolute phase information is output.

  With this configuration, the motor drive control device of the present invention smoothes the position signal by the smoothing effect obtained when the phase of the output signal of the phase synchronization circuit and the position signal are phase-synchronized, and the position signal for the absolute phase information Since the shift of the change points of the above can be suppressed to be smaller than that of the conventional one, the occurrence of uneven rotation, vibration and noise can be suppressed.

  Further, in the motor drive control device according to the present invention, the absolute phase information output means includes a plurality of predetermined reference phases respectively corresponding to change points of the signal level of the position signal and phases corresponding to the absolute phase information. A phase comparator for obtaining a phase difference, a pulse signal generator for generating a pulse signal having a frequency corresponding to the phase difference, and a signal having a phase corresponding to the absolute phase information on the basis of the pulse signal. And a phase signal generator to be generated.

  With this configuration, the motor drive control device of the present invention compares a plurality of predetermined reference phases respectively corresponding to each change point of the signal level of the position signal and a phase corresponding to the absolute phase information to obtain a phase difference. Since a pulse signal having a frequency corresponding to the phase difference is obtained and more precise absolute phase information can be output. Also, with this configuration, the motor drive control device of the present invention can widen the dynamic range of phase comparison by increasing the count number range when the phase signal generator is configured with a counter. Stable operation is possible.

  Furthermore, the motor drive control device according to the present invention further includes a rectangular wave driving unit that outputs a rectangular wave driving signal for causing a rectangular wave current to flow through the plurality of armature windings in accordance with the position signal, The motor is driven by the sine wave drive signal when the synchronization circuit is in the phase synchronization state, and the motor is driven by the rectangular wave drive signal when the phase synchronization circuit is not in the phase synchronization state. Yes.

  With this configuration, the motor drive control device according to the present invention is phase-shifted when the motor rotation speed is extremely low, such as during startup or intentional shifting, or when the motor rotation speed change is very fast. When synchronization is not normal, the motor is driven by a rectangular wave, and when the motor is in phase synchronization normally, such as when the motor is in a steady state, the motor is driven by a sine wave. It does not occur and stable motor driving can always be performed.

  Furthermore, the motor drive control device of the present invention includes a frequency detection means for detecting a frequency corresponding to the rotation speed of the rotor, a target frequency corresponding to a predetermined target rotation speed of the rotor, and the frequency detection means. A frequency difference detecting means for detecting a frequency difference from the detected frequency, and a control signal generating means for generating a drive voltage control signal for driving the motor based on the frequency difference. Yes.

  With this configuration, the motor drive control device of the present invention can perform the motor speed control more precisely than the apparatus that controls the motor speed by feedback control.

  Furthermore, the motor drive control device of the present invention has a configuration provided with sine wave amplitude modulation means for amplitude modulating the sine wave drive signal in accordance with the drive voltage control signal.

  With this configuration, the motor drive control device of the present invention can drive the motor with a sine wave at an arbitrary voltage, so that the drive control of the motor can be easily performed.

  Furthermore, the motor drive control device of the present invention has a configuration including drive signal amplitude modulation means for amplitude modulating the sine wave drive signal and the rectangular wave drive signal in accordance with the drive voltage control signal.

  With this configuration, the motor drive control device of the present invention can drive the motor with a sine wave and a rectangular wave of an arbitrary voltage, so that the drive control of the motor can be easily performed.

  The present invention can provide a motor drive control device having the effect of being able to perform precise motor drive control with lower noise and vibration than conventional ones.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. An example in which the motor drive control device of the present invention is applied to drive control of a brushless motor will be described. In the brushless motor illustrated here, three-phase (U-phase, V-phase and W-phase) armature windings are connected in a star shape, and this armature winding is used as a stator, and the number of arrangement is six. A pole permanent magnet rotates as a rotor on the outside of the stator.

  First, the configuration of an embodiment of a motor drive control device according to the present invention will be described.

  As shown in FIG. 1, the motor drive control device 100 according to the present embodiment includes a motor information acquisition unit 20 that acquires information on the brushless motor 10, a control data generation unit 30 that generates control data, and a sine wave signal. A sine wave signal output means 40 for outputting, an operation mode setting means 50 for setting an operation mode, and a drive voltage control means 60 for controlling the drive voltage of the brushless motor 10 are provided.

  The brushless motor 10 includes a motor coil 11 having a U phase, a V phase, and a W phase, and three hall sensors 12 (12a to 12c) that detect a rotational position of a rotor (not shown) having a six-pole permanent magnet. , And a frequency generator (hereinafter referred to as “FG”) 13 that outputs a pulse signal in accordance with the number of rotations of the rotor.

  The Hall sensor 12 converts a change in the magnetic field of the rotor into a change in voltage, and detects the rotational position of the rotor. It is assumed that the hall sensors 12 are arranged on the stator at an angle of 120 degrees with respect to the rotation center of the rotor.

  The FG 13 is composed of, for example, an optical encoder or a magnetic sensor, and generates a periodic signal having a frequency proportional to the rotational speed of the brushless motor 10.

  In the present embodiment, the rotational position of the rotor is detected using the hall sensor 12, but the present invention is not limited to this. For example, an optical encoder using a photodiode, an infrared sensor, etc. A sensor of a method other than the electromagnetic conversion method may be used.

  The motor information acquisition unit 20 includes a hall amplifier 21 that amplifies the output signal of the hall sensor 12 and an FG amplifier 22 that amplifies the FG signal output from the FG 13. The hall amplifier 21 corresponds to the position signal output means of the present invention.

  The hall amplifier 21 amplifies the signal output from the hall sensor 12, performs waveform shaping, and outputs binary hall signals HU, HV, and HW corresponding to the U phase, V phase, and W phase, respectively. Yes. In the following description, the three hall signals HU, HV, and HW are collectively referred to as “HG signal”.

  The FG amplifier 22 amplifies the output signal of the FG 13, performs waveform shaping, and outputs it as a binary FG signal. The FG signal is a predetermined number (for example, 100) of pulses per one rotation of the motor. The number of pulses per motor rotation is determined by the configuration of FG13. The FG amplifier 22 corresponds to the frequency detection means of the present invention.

  The control data generating means 30 includes a target frequency generator 31 that generates a pulse signal having a target frequency, a frequency comparator 32 that compares frequencies, and an error amplifier 33 that amplifies an error signal.

  The target frequency generator 31 generates a pulse signal having a target frequency corresponding to the target rotational speed of the brushless motor 10.

  The frequency comparator 32 compares the frequency of the FG signal output from the FG amplifier 22 with the frequency of the pulse signal output from the target frequency generator 31, and outputs an error signal corresponding to the difference between the two frequencies. It has become. The frequency comparator 32 corresponds to the frequency difference detecting means of the present invention.

  The error amplifier 33 amplifies the error signal output from the frequency comparator 32 and outputs control data for driving the brushless motor 10. Here, the error amplifier 33 outputs control data with a positive sign when the FG frequency is lower than the target frequency. By increasing the gain of the error amplifier 33, control data is output so that the speed corresponding to the target frequency and the motor rotation speed become substantially equal.

  As will be described later, the control data corresponds to the voltage applied to the motor coil 11 in the form of amplitude modulation of a sine wave driving waveform or a rectangular wave driving waveform. Based on this control data, speed control is performed so that the motor rotation speed becomes substantially equal to the speed corresponding to the target frequency. Here, the control data corresponds to the drive voltage control signal described in the claims. The error amplifier 33 corresponds to the control signal generation means of the present invention.

  The configuration of the error amplifier 33 may include not only the amplification of the error signal but also a filter that integrates a low frequency signal component of the error signal or cuts a high frequency noise component of the error signal, for example. Good.

  The sine wave signal output means 40 includes a phase synchronization unit 70, a counter 41, a sine wave generator 42 (42 U, 42 V, 42 W), and a lock determination unit 43.

  The phase synchronization unit 70 inputs the hall signals HU, HV, and HW and outputs the clock signal SinCk, and is configured by, for example, a PLL (Phase Locked Loop) circuit. Here, the PLL circuit corresponds to the phase synchronization circuit of the present invention.

  Specifically, the phase synchronization unit 70 compares the phase of the rising edge and the falling edge of the hall signals HU, HV, and HW that are input signals with the phase of the clock signal SinCk that is an output signal. Accordingly, the frequency of the clock signal SinCk is varied. As a result, the phase synchronization unit 70 can output the clock signal SinCk that is phase-synchronized with the edges of the hall signals HU, HV, and HW. The frequency of the clock signal SinCk is a frequency obtained by multiplying the edge frequencies of the hall signals HU, HV, and HW. In the present embodiment, the frequency of the clock signal SinCk is, for example, 192 times the frequency of the hall signal HU.

  Further, the phase synchronization unit 70 outputs a load signal with a predetermined absolute phase, for example, once in one cycle of the hall signals HU, HV, and HW. The absolute phase may be determined within one period of the rotor or may be determined within a plurality of periods.

  Hereinafter, the configurations of the phase synchronization unit 70 and the lock determination unit 43 will be described with reference to FIGS. FIG. 2 is a block diagram of the phase synchronization unit 70 and the lock determination unit 43. FIG. 3 shows the waveforms of the HG signal and the FG signal for one rotation of the motor, the count state of the counter 73 described later, and the like. As described above, since the hall sensors 12a to 12c are arranged at an angle of 120 degrees with each other, as shown in FIG. 3, one of the three hall signals HU, HV and HW is combined (an electrical angle of 360 degrees). 6) combinational logic states are obtained. Therefore, in the electrical angle, the high level and low level states of the signal change every 60 degrees. Since this is three cycles in one rotation of the motor, there are 18 state changes, and the motor changes every 20 degrees.

  First, the configuration of the phase synchronization unit 70 will be described. An example in which the phase synchronization unit 70 is configured with a PLL circuit will be described.

  As shown in FIG. 2, the phase synchronization unit 70 includes an edge detector 71, an offset generator 72, a counter 73, a register 74, a phase comparator 75, an amplifier 76, an integrator 77, and an adder. 78, a VCO (Voltage Controlled Oscillator) 79, a frequency divider 80, and a load signal generator 81. In FIG. 2, the symbol “==” indicates “equal to”.

  The edge detector 71 detects all rising edges and falling edges of the HG signal, and outputs an edge detection signal to the register 74 when an edge is detected. Specifically, as shown in FIG. 3, the edge detector 71 indicates the UR indicating the position of the rising edge of the Hall signal HU, the UF indicating the position of the falling edge, and the position of the rising edge of the Hall signal HV. The VF indicating the position of the VR and the falling edge, the WR indicating the position of the rising edge of the Hall signal HW, and the WF indicating the position of the falling edge are detected. Note that six edge detection signals are obtained in one cycle of UR to VF shown in FIG. 3, that is, one cycle of the HG signal.

  As will be described later, the offset generator 72 generates a signal indicating a predetermined unique reference counter value corresponding to each of the six edges of the HG signal. The reference counter value corresponds to the reference phase described in the claims.

  The counter 73 is a down counter that receives the clock signal VcoCk output from the VCO 79, counts down every time the clock signal VcoCk is input, and repeats counting from 767 to 0. The counter 73 corresponds to the phase signal generator of the present invention.

  The register 74 is connected to the edge detector 71 and the counter 73, and latches (holds) the counter value of the counter 73 at a timing when the edge detector 71 outputs an edge detection signal.

  The phase comparator 75 is connected to the offset generator 72 and the register 74, and compares the reference counter value generated by the offset generator 72 with the counter value held by the register 74 to calculate the difference. Yes.

  Specifically, the phase comparator 75 subtracts the reference counter value generated by the offset generator 72 from the counter value held by the register 74, and compares each phase value of the counter value corresponding to six edges of the HG signal. Data indicating the result (hereinafter referred to as “phase difference PhDat”) is output. That is, the phase comparator 75 compares the reference counter value of the counter 73, that is, the absolute phase of the clock signal VcoCk, with the absolute phase of each edge of the HG signal.

  This will be described more specifically with reference to FIG. The reference counter value output from the offset generator 72 to the phase comparator 75 is the next value, and each reference counter value has a width of ± 64. These reference counter values are determined in advance based on the ideal detection position of each edge of the HG signal.

(1) The reference counter value corresponding to the rising edge UR of the HU signal is set to “704”.
(2) The reference counter value corresponding to the falling edge WF of the HW signal is “576”.
(3) The reference counter value corresponding to the rising edge VR of the HV signal is “448”.
(4) The reference counter value corresponding to the falling edge UF of the HU signal is set to “320”.
(5) The reference counter value corresponding to the rising edge WR of the HW signal is “192”.
(6) The reference counter value corresponding to the falling edge VF of the HV signal is “64”.
First, when the rising edge UR of the HU signal occurs, the counter value of the counter 73 is loaded into the register 74, and the reference counter value “704” corresponding to the UR is output from the offset generator 72, and the phase comparator 75 compares the counter value of the counter 73 with the reference counter value “704”, calculates the phase difference PhDat, and outputs it.

  Similarly, the phase comparator 75 obtains the counter value at the time of the falling edge WF of the HW signal and the reference counter value “576”, the counter value at the time of the rising edge VR of the HV signal, and the reference counter value “448”. The counter value at the time of the falling edge UF of the HU signal and the reference counter value “320” are sequentially compared, and the phase difference PhDat is sequentially calculated and output. Further, the phase comparator 75 sequentially compares the counter value at the rising edge WR of the HW signal and the reference counter value “192”, and the counter value at the falling edge VF of the HV signal and the reference counter value “64”. The phase difference PhDat is sequentially calculated and output.

  Here, the value of the phase difference PhDat is the phase difference “0” when the counter value when the edge of the HG signal arrives is equal to the reference counter value corresponding to the edge of the HG signal. Is larger than each reference counter value (when the counter phase is a lag phase), a positive phase difference from +1 to +64, and when the counter value of the counter 73 is smaller than each reference counter value (the counter phase is an advanced phase) ) Is a negative phase difference from −1 to −64.

Returning to FIG. 2, the description of the configuration of the phase synchronization unit 70 will be continued.
The amplifier 76 amplifies the phase difference PhDat and outputs it to the adder 78. The integrator 77 integrates the phase difference PhDat and outputs it to the adder 78. The adder 78 adds the output signal of the amplifier 76 and the output signal of the integrator 77 and outputs the result to the VCO 79. With the above configuration, when the frequency of the HG signal is an average constant frequency, the output of the integrator 77 becomes an average constant value, and the phase difference PhDat is controlled to “0” on the average. Therefore, since the phase synchronization unit 70 does not have a steady phase difference due to the effect of the integrator 77, accurate absolute phase information can be output.

  The configuration of the amplifier 76, the integrator 77, and the adder 78 is an error amplifier that amplifies the phase difference PhDat, and is a known PI (Proposal + Integration) controller whose gain is increased by the integrator 77 in the low frequency region. ing.

  The VCO 79 is a digital voltage controlled oscillator, and outputs a clock signal VcoCk having a frequency proportional to the value of the output signal of the adder 78. That is, when the phase difference PhDat is positive (counter phase is delayed), the frequency is increased to advance the counter phase, and when the phase difference PhDat is negative (counter phase is advanced), the frequency is decreased. And delay the counter phase. As a result, the frequency of the clock signal VcoCk and the absolute phase of the counter 73 are controlled so that the value of the phase difference PhDat becomes “0”. In the present embodiment, it is assumed that the clock signal VcoCk has a frequency that is 768 times that of the HG signal. The VCO 79 corresponds to the pulse signal generator of the present invention.

For example, as shown in FIG. 4, the configuration of the VCO 79 can be realized by accumulating the input data VcoIn by an adder 79a and a register 79b and using the carry signal as a clock signal VcoCk. The addition clock signal clk input to the register 79b is a clock signal having a fixed frequency f _clk , and the fixed frequency f _clk is preferably sufficiently higher than the clock signal VcoCk. Further, the frequency f _VcoCk of the clock signal VcoCk is obtained by the following equation when the bit width of the cumulative addition data is n bits, and is proportional to the input data VcoIn.

^{_{f VcoCk = VcoIn × (1/2 n}} ) × f clk (Hz)
The configuration of the VCO 79 is not limited to that shown in FIG. 4. For example, after the input data VcoIn is converted into an analog signal by a D / A converter, this signal is input as a control voltage for the analog VCO. It is good also as a structure.

Returning to FIG. 1, the description of the configuration of the phase synchronization unit 70 will be continued.
The frequency divider 80 divides the clock signal VcoCk by ¼ and outputs a clock signal SinCk for generating a sine wave. Here, the reason why the frequency divider 80 is provided will be described. As described above, since the clock signal VcoCk is a clock 768 times the HG signal frequency, a wide phase difference range (± 64 range) can be secured, and the PLL circuit can be operated stably. . However, in general, as a sine wave for driving a motor, a high resolution such as a clock having a frequency of 768 times the HG signal frequency is often unnecessary, so a frequency divider 80 is provided and the clock signal VcoCk is divided by a quarter. The clock signal SinCk having a frequency that is 192 times the HG signal frequency is output.

  The load signal generator 81 is connected to the counter 73, and generates and outputs a Load signal when the counter value of the counter 73 becomes zero. The timing at which the load signal generator 81 outputs the Load signal is, for example, slightly before the rising edge UR of the Hall signal HU as shown in FIG. This position corresponds to the predetermined absolute phase described in the description of the configuration of the phase synchronization unit 70. In FIG. 3, by setting the absolute phase at the output position of the second Load signal to 0 degree, the absolute phase of, for example, one cycle of the HG signal can be determined.

  As described above, the phase synchronization unit 70 according to the present embodiment is configured by a PLL circuit, and inputs an HG signal and outputs a clock signal SinCk for generating a sine wave. In general, a PLL circuit has a smoothing effect in which a noise-like change in an input signal phase is smoothed by a feedback loop, and a phase change in an output clock signal can be suppressed to a small level. Therefore, the phase synchronization unit 70 can suppress the phase change of the HG signal that is the input signal due to the smoothing effect of the PLL circuit.

Here, smoothing will be described with reference to FIGS.
FIG. 5A shows one waveform of the HG signal (for example, the hall signal HU), and is a conceptual diagram showing a state in which a waveform corresponding to five rotations of the motor is taken with a certain absolute phase as a reference. In an ideal motor, the rising edge and the falling edge of the HG signal appear at the same position in a plurality of periods, but in reality, each edge position of the HG signal is the position of a component such as a hall sensor or a permanent magnet. Variations in the width of ΔT due to mounting accuracy errors, external noise, and the like. However, since the phase synchronization unit 70 is configured by a PLL circuit, smoothing can be performed as shown in FIG.

  The waveform of smoothing by the PLL circuit is, for example, as shown in FIG. FIG. 6 conceptually shows the phase shift between the phase of the input signal and the phase of the output signal. Due to the smoothing effect of the PLL circuit, the phase change of the output clock can be suppressed to, for example, about “0.1” even if there is a change of, for example, an arbitrary unit “1” as the noise-like phase change of the input signal. In other words, even if the electrical angle deviation of the Hall signal is 10 degrees, for example, the electrical angle can be suppressed to 1 degree, for example. It is well known that such an effect can be realized by appropriately designing the loop bandwidth of the PLL circuit. The characteristics of the loop band are related to the configuration of the amplifier 76, the integrator 77, and the adder 78 in the circuit of the phase synchronization unit 70 shown in FIG. 2. For example, when the gain of the amplifier 76 is lowered, the phase synchronization tracking speed is reduced. However, the smoothing characteristics are improved.

  As described above, even if the edge positions of the HG signal vary due to the mounting accuracy error of the Hall sensor 12 or the permanent magnet, the external noise, or the like, the phase synchronization unit 70 uses the smoothing characteristics of the PLL circuit to change each edge position of the HG signal. Since the variation in edge position can be eliminated, the clock signal SinCk having a sufficiently smaller phase change than the conventional one can be output.

Returning to FIG. 2, the configuration of the lock determination unit 43 will be described.
As shown in FIG. 2, the lock determination unit 43 includes a data comparator 43 a, a mono multivibrator (hereinafter referred to as “MM”) 43 b, and a logic circuit 43 c, and is an HG that is an input signal in the phase synchronization unit 70. It is determined whether or not the phase of the signal is synchronized with the phase of the clock signal VcoCk that is the output signal of the VCO 79. In the following description, a state where the phase of the HG signal and the phase of the clock signal VcoCk are synchronized is referred to as a “locked state”, and a state where the two are not synchronized is referred to as an “unlocked state”. This locked state corresponds to the phase synchronization state described in the claims. Note that “synchronized” does not mean only the state where the phase of the HG signal and the phase of the clock signal VcoCk are completely matched, but the state where both are matched with a predetermined width. Is also included.

  The data comparator 43a is connected to the phase comparator 75, compares the phase difference PhDat with a predetermined reference value (for example, “32”), and outputs the result. Specifically, the data comparator 43a compares whether or not the absolute value of the phase difference PhDat is smaller than “32” and outputs a signal of PdOK = 1 as a determination result when the absolute value is smaller. As described above, since the range of the phase difference PhDat is set to ± 64, the data comparator 43a determines whether or not the phase difference PhDat is within the range of ± 32.

  The MM 43b is triggered by the rising edge of the PdOK signal and outputs a signal indicating "1" for a predetermined time.

  When the PdOK signal is “1” and the output signal of the MM 43b is “0”, the logic circuit 43c determines that the phase synchronization unit 70 is in the locked state, and outputs a PLL_LOCK signal indicating the determination result as “1”. It has become. That is, the logic circuit 43c determines that the phase synchronization unit 70 is in the locked state when the state where the phase difference is within the range of ± 32 continues for the set time tMM.

  More specifically, the operation of the lock determination unit 43 outputs a signal of PdOK = 1 when the phase difference PhDat is within a range of ± 32, and the phase difference PhDat is ±±, as shown in FIG. When not within the range of 32, a signal of PdOK = 0 is output. The MM 43b is triggered by the rising edge of the PdOK signal and outputs a signal indicating “1”. The logic circuit 43c outputs a signal of PLL_LOCK = 1 after the state of the output signal = 1 of the MM 43b continues for the set time tMM until the PdOK signal = 0. Therefore, the period during which the logic circuit 43c outputs the signal PLL_LOCK = 1 corresponds to the period during which the phase synchronization unit 70 is locked.

Returning to FIG. 1, the description of the configuration of the sine wave signal output means 40 will be continued.
The counter 41 is initialized to a predetermined value (for example, “0”) by the Load signal output from the phase synchronization unit 70 and is incremented by the clock signal SinCk. Due to the configuration of the frequency divider 80 and the load signal generator 81 of the phase synchronization unit 70 (see FIG. 2), when the counter 41 counts from “0” to “191”, the counter value of the counter 41 returns to “0”. This counter value represents the absolute phase of one cycle of the HG signal (electrical angle 360 degrees), and is 32 counts per 60 electrical angles. As described above, the configuration in which the counter 41 counts 192 from “0” to “191” is a case where the absolute phase is represented by one cycle of the HG signal, for example, when the absolute phase is represented by two cycles of the HG signal. The counter 41 may count 384 (= 192 × 2).

  The phase synchronization unit 70 and the counter 41 correspond to the absolute phase information output unit of the present invention. The counter value of the counter 41 corresponds to “absolute phase information” recited in the claims. On the other hand, the counter value of the counter 73 (see FIG. 2) corresponds to “phase corresponding to absolute phase information” recited in the claims. As described above, the difference between the counter 41 and the counter 73 is only the difference in phase resolution (192 division / HG cycle or 768 division / HG cycle). Therefore, instead of the counter 41, the counter 73 may be used directly as “absolute phase information” for generating a sine wave. In this case, “absolute phase information” and “phase corresponding to absolute phase information” are the same component.

  The sine wave generator 42 normalizes the three-phase sine wave waveform to be applied to the U phase, V phase and W phase of the motor coil 11 based on the counter value of the counter 41 (normalizes the amplitude to ± 1). ) And output. By driving the U phase, V phase and W phase based on this normalized sine wave signal (hereinafter referred to as “normalized sine wave signal”), a sine wave current flows to the motor coil 11 and the brushless motor 10. Will rotate. The sine wave generator 42 corresponds to the sine wave driving means of the present invention.

  As described above, the phase synchronization unit 70 can eliminate the variation in the edge of the HG signal due to the smoothing characteristic of the PLL circuit, and therefore outputs the clock signal SinCk whose phase change is sufficiently smaller than the conventional one. It is something that can be done. The sine wave generator 42 generates a normalized sine wave signal based on the counter value of the counter 41 that counts up with the clock signal SinCk. Therefore, the normalized sine wave signal generated by the sine wave generator 42 has a smaller waveform disturbance than the conventional one, and as a result, the influence on the motor rotation can be reduced.

  Next, the configuration of the operation mode setting unit 50 will be described.

  The operation mode setting means 50 includes a multiplier 51 (51U, 51V, 51W), a selector 52 (52U, 52V, 52W), and an operation mode command unit 53, and whether the phase synchronization unit 70 is in a locked state or not. The operation mode of the brushless motor 10 is set according to whether it is in the locked state. Here, the operation modes of the brushless motor 10 include a “sine wave energization mode” for driving the brushless motor 10 with a sine wave and a “rectangular wave energization mode” for driving with a rectangular wave.

  The multiplier 51 multiplies the control data output from the control data generating means 30 and the normalized sine wave signal output from the sine wave generator 42. For example, the multiplier 51U multiplies the control data by the normalized sine wave signal output from the sine wave generator 42U.

  The selector 52 receives the PLL_LOCK signal from the lock determination unit 43 and outputs the control data output from the control data generation unit 30 and the multiplier 51 according to whether the phase synchronization unit 70 is in the locked state or the unlocked state. One of the output signals is selected and output. The output data of the selector 52 is hereinafter referred to as “drive data”. In FIG. 1, the output data of the selectors 52U, 52V, and 52W are represented as drive data dataU, dataV, and dataW, respectively.

  Specifically, when the phase synchronization unit 70 is in the locked state (PLL_LOCK = 1), the selectors 52U, 52V, and 52W select the output signals of the multipliers 51U, 51V, and 51W, respectively. On the other hand, the selectors 52U, 52V, and 52W select the control data output by the control data generating means 30 when the phase synchronization unit 70 is in the unlocked state (PLL_LOCK = 0). Therefore, when the phase synchronization unit 70 is in the unlocked state, the drive data dataU, dataV, and dataW are the same data.

  The operation mode command unit 53 is connected to the hall amplifier 21 and the lock determination unit 43, and commands the operation mode of the drive voltage control means 60 depending on whether the phase synchronization unit 70 is in the locked state or the unlocked state. An operation mode command signal is output for the purpose. The operation mode command unit 53 corresponds to the rectangular wave driving means of the present invention.

  For example, the operation mode command unit 53 operates the operation mode command signal ph_U for controlling the drive voltage control unit 60 to operate in the “sine wave energization mode” when the phase synchronization unit 70 is in the locked state (PLL_LOCK = 1). , Ph_V, ph_W are output to the drive voltage control means 60.

  On the other hand, when the phase synchronization unit 70 is in the unlocked state (PLL_LOCK = 0), the operation mode command unit 53 causes the hall signals HU, HV and HW so that the drive voltage control unit 60 operates in the “rectangular wave energization mode”. The operation mode command signals ph_U, ph_V, ph_W are output to the drive voltage control means 60 in accordance with the signal state.

  Next, the configuration of the drive voltage control means 60 will be described.

  The drive voltage control means 60 includes a PWM drive unit 61 (61U, 61V, 61W) that performs pulse width modulation (hereinafter referred to as “PWM”).

  The PWM drive unit 61 receives drive data from the selector 52 and operates based on an operation mode command signal output from the operation mode command unit 53. The PWM drive unit 61 corresponds to the sine wave drive means, rectangular wave drive means, sine wave amplitude modulation means, and drive signal amplitude modulation means of the present invention.

  For example, the PWM drive unit 61 outputs the control data generated by the control data generation unit 30 when the operation mode command unit 53 outputs an operation mode command signal for controlling the operation in the “rectangular wave energization mode”. Input as drive data from the selector 52, the motor coil 11 is PWM driven with a pulse width proportional to the drive data, and a current flows.

  Specifically, as shown in FIG. 8, the rectangular wave drive waveforms U, V, and W when the phase synchronization unit 70 is in the unlocked state (PLL_LOCK = 0) with respect to the hall signals HU, UV, and HW are The phase relationship is as shown in the middle part of FIG. Here, signals indicated by symbols “M”, “PWM_H”, and “PWM_L” correspond to the operation mode command signals ph_U, ph_V, and ph_W, respectively, commanded from the operation mode command unit 53.

  Next, FIG. 9 shows an example of PWM pulses corresponding to each operation mode “M”, “PWM_H”, and “PWM_L” when the PWM drive unit 61 drives the rectangular wave. The mode “M” is a mode in which no current flows through the motor coil 11, and a pulse with a duty of 50% is output. In the mode “PWM_H”, driving is performed with a high level time longer than 50% in accordance with driving data (always positive in this case). In the mode “PWM_L”, the high level time is reversed to be shorter than 50% according to the drive data (here, always positive).

  On the other hand, when the PWM drive unit 61 outputs an operation mode command signal for controlling the operation mode command unit 53 to operate in the “sine wave energization mode”, the multiplier 51 controls the control data and the normalized sine wave. A signal multiplied by the signal is input as drive data from the selector 52, and the motor coil 11 is PWM-driven with a pulse width proportional to the drive data, and a current flows.

  The operation waveform in the “sine wave energization mode” in the PWM drive unit 61 is indicated by “Sin” in FIG. 9. That is, since the drive data is a positive / negative signal centered on “0”, the duty of the output pulse is 50% when the drive data is “0”, and the high level of the pulse according to the drive data when the drive data is positive. The width of becomes longer. When the drive data is negative, the high level width of the pulse is shortened according to the drive data. The basic period of the pulse is a predetermined value tpwm. It is preferable that tpwm be sufficiently shorter than the period of the sine wave drive.

  By the PWM drive as shown in FIG. 9, between the terminals to which the motor coil 11 is connected (not shown), a current flows from a terminal having a high pulse duty to a terminal having a low pulse duty (terminal having a high average voltage to a terminal having a low average voltage), As a result, the current is smoothed by the inductance component of the motor coil 11 and a sinusoidal current corresponding to the drive data flows.

  In the above description, the example in which the phase synchronization unit 70 is configured by a PLL circuit has been described. However, the present invention is not limited to this, and the position signal indicating the position of the rotor is smoothed to be the position signal. Any device that outputs the corresponding absolute phase information may be used. Conventionally, for example, a PLL circuit is sometimes used for controlling the speed of a motor. Such a PLL circuit used for speed control or the like may have the function of the phase synchronization unit 70 according to the present invention, or the phase synchronization unit 70 may be provided separately from the PLL circuit used for speed control or the like. Also good.

  Next, the operation of the motor drive control device 100 in the present embodiment will be described.

  First, in the motor information acquisition means 20, the hall amplifier 21 inputs and amplifies a position signal indicating the position of the rotor from the hall sensor 12 provided in the brushless motor 10, and a phase synchronization unit of the sine wave signal output means 40. HG signal is output to 70 and the operation mode command unit 53 of the operation mode setting means 50. The FG amplifier 22 receives and amplifies a signal indicating the rotational speed of the rotor from the FG 13 provided in the brushless motor 10, and outputs an FG signal to the frequency comparator 32 of the control data generating unit 30.

  Next, in the control data generating means 30, the target frequency generator 31 generates a pulse signal having a target frequency corresponding to the target rotational speed of the brushless motor 10 and outputs the pulse signal to the frequency comparator 32.

  Next, the frequency comparator 32 compares the frequency of the FG signal output from the FG amplifier 22 with the frequency of the pulse signal output from the target frequency generator 31, and generates an error signal corresponding to the difference between the two in the error amplifier. To 33.

  Subsequently, the error amplifier 33 amplifies the error signal output from the frequency comparator 32 and outputs it to the operation mode setting means 50 as control data for driving the brushless motor 10.

  Next, in the sine wave signal output means 40, the phase synchronizer 70 inputs the HG signal and outputs a clock signal SinCk for generating a sine wave. Here, since the phase synchronization unit 70 can suppress the phase change of the HG signal that is the input signal due to the smoothing effect of the PLL circuit, the phase change of the clock signal SinCk can be suppressed small.

  In addition, the phase synchronization unit 70 outputs a Load signal with a predetermined absolute phase once per period of the HG signal. In the present embodiment, the phase synchronization unit 70 generates and outputs a Load signal when the counter value of the counter 73 (see FIG. 2) becomes zero.

  Subsequently, the counter 41 is initialized to a counter value of, for example, “0” by the Load signal output from the phase synchronization unit 70, and counts up by the clock signal SinCk. When counting from “0” to “191”, the counter value of the counter 41 returns to “0”.

  Next, the sine wave generator 42 normalizes the three-phase sinusoidal waveform to be applied to the U phase, V phase, and W phase of the motor coil 11 based on the counter value of the counter 41, and normalizes the sine wave signal. Is output to the operation mode setting means 50.

  On the other hand, the lock determination unit 43 receives the phase difference PhDat from the phase comparator 75 (see FIG. 2) of the phase synchronization unit 70, determines whether the phase synchronization unit 70 is in the locked state or the unlocked state, A PLL_LOCK signal indicating the determination result is output to the operation mode setting means 50.

  Next, in the operation mode setting unit 50, the multiplier 51 multiplies the control data output from the control data generation unit 30 and the normalized sine wave signal output from the sine wave generator 42.

  The selector 52 receives the PLL_LOCK signal from the lock determination unit 43, and outputs the control data and multiplier output by the control data generation unit 30 depending on whether the phase synchronization unit 70 is in the locked state or the unlocked state. One of the output signals 51 is selected and output to the drive voltage control means 60 as drive data. For example, the selector 52 selects the output signal of the multiplier 51 when the phase synchronization unit 70 is in the locked state, and the control data output by the control data generating means 30 when the phase synchronization unit 70 is in the unlocked state. select.

  Further, the operation mode command unit 53 outputs an operation mode command signal for commanding the operation mode of the drive voltage control means 60 according to whether the phase synchronization unit 70 is in the locked state or the unlocked state. Output to means 60. For example, the operation mode command unit 53 outputs an operation mode command signal for controlling the drive voltage control unit 60 to operate in the “sine wave energization mode” when the phase synchronization unit 70 is in the locked state. When the phase synchronization unit 70 is in the unlocked state, the drive voltage control unit 60 outputs an operation mode command signal according to the state of the HG signal so that the drive voltage control unit 60 operates in the “rectangular wave energization mode”. Output to.

  Next, in the drive voltage control means 60, the PWM drive unit 61 receives drive data from the selector 52 and operates based on the operation mode command signal output from the operation mode command unit 53.

  For example, the PWM drive unit 61 outputs the control data generated by the control data generation unit 30 when the operation mode command unit 53 outputs an operation mode command signal for controlling the operation in the “rectangular wave energization mode”. Input as drive data from the selector 52, the motor coil 11 is PWM driven with a pulse width proportional to the drive data, and a current flows.

  On the other hand, when the PWM drive unit 61 outputs an operation mode command signal for controlling the operation mode command unit 53 to operate in the “sine wave energization mode”, the multiplier 51 controls the control data and the normalized sine wave. A signal multiplied by the signal is input as drive data from the selector 52, and the motor coil 11 is PWM-driven with a pulse width proportional to the drive data, and a current flows. As a result, a current flows from a terminal having a high pulse duty to a terminal having a low pulse duty between terminals connected to the motor coil 11, and a sine wave current that is smoothed by the inductance component of the motor coil 11 and flows according to drive data flows.

  As described above, according to the motor drive control device 100 in the present embodiment, the phase synchronization unit 70 smoothes the input HG signal to generate the clock signal SinCk whose phase change is sufficiently smaller than that of the conventional one. The counter 41 counts up with the clock signal SinCk and outputs a counter value indicating the absolute phase information of the HG signal. The PWM drive unit 61 performs sine wave driving and rectangular wave driving based on the absolute phase information. Due to the configuration, it is possible to suppress the occurrence of uneven rotation, vibration and noise.

  Therefore, the motor drive control device of the present invention can make distortion and discontinuity of the sine wave drive signal smaller than the conventional one, and can perform precise motor drive control with low noise and vibration. it can.

  When the HG signal has an extremely low frequency, such as during startup or intentional shifting, or when the frequency change is very fast, the phase synchronization unit 70 that is phase-synchronized with the HG signal may not be locked properly. There is. For this reason, the motor drive control device 100 according to the present embodiment is configured to perform rectangular wave driving when the phase synchronization unit 70 is in the unlocked state, and sine wave drive when in the locked state. Motor drive is possible.

  Here, the rectangular wave drive is only a transitional case such as start-up or intentional shifting, so the vibration and noise problems peculiar to the rectangular wave drive are negligible in practical use. Very little time. Since it operates with sine wave drive most of the time, the effects of low vibration and low noise, which are the features of sine wave drive, are sufficiently maintained.

  In the above-described embodiment, the output signals of the FG 13 and the FG amplifier 22 can be replaced with any one of Hall element signals HU, HV, and HW, or a combined signal. This is because even in this case, a frequency proportional to the motor speed is generated. However, it is preferable to provide the FG 13 separately from the Hall sensor 12 because the number of pulses can be increased as compared with the pulses by the HG signal, so that more precise speed control can be performed.

  As described above, the motor drive control device according to the present invention has the effect of being able to perform precise motor drive control with lower noise and vibration than the conventional one, and a plurality of armature windings. This is useful as a motor drive control device for controlling the drive of a brushless motor having a wire.

The block diagram which shows the structure in one Embodiment of the motor drive control apparatus which concerns on this invention. The block diagram which shows the structure of the phase-synchronization signal generation part and lock determination part in one Embodiment of the motor drive control apparatus which concerns on this invention The figure which shows the relationship between a Hall signal, FG signal, a reference | standard count value, and a count value in one embodiment of the motor drive control device according to the present invention. The block diagram which shows the structure of VCO in one Embodiment of the motor drive control apparatus which concerns on this invention FIG. 4 is a conceptual diagram of smoothing characteristics of a phase synchronization unit in an embodiment of a motor drive control device according to the present invention; (a) a conceptual diagram illustrating a state in which a waveform of an HG signal for five motor rotations is captured; Schematic diagram showing the waveform of the HG signal The figure which shows notionally the phase shift | offset | difference of the phase of the input signal in the phase synchronization part in one Embodiment of the motor drive control apparatus which concerns on this invention, and the phase of an output signal Explanatory drawing of operation | movement of the lock determination part in one Embodiment of the motor drive control apparatus which concerns on this invention. In one embodiment of the motor drive control device according to the present invention, the Hall signals HU, HV and HW in the PWM drive unit, the rectangular wave drive waveforms U, V and W, and the sine wave drive waveforms U, V and W Diagram showing phase relationship The figure which shows the example of the PWM pulse at the time of the rectangular wave drive in PWM drive part in one Embodiment of the motor drive control apparatus which concerns on this invention

Explanation of symbols

10 brushless motor 11 motor coil 12 (12a to 12c) hall sensor 13 FG
20 Motor information acquisition means 21 Hall amplifier (position signal output means)
22 FG amplifier (frequency detection means)
30 Control data generating means 31 Target frequency generator 32 Frequency comparator (frequency difference detecting means)
33 Error amplifier (control signal generating means)
40 sine wave signal output means 41 counter (absolute phase information output means)
42 (42U, 42V, 42W) Sine wave generator (sine wave drive means)
43 Lock determination unit 43a Data comparator 43b MM
43c Logic circuit 50 Operation mode setting means 51 (51U, 51V, 51W) Multiplier 52 (52U, 52V, 52W) Selector 53 Operation mode command section (rectangular wave drive means)
60 Drive voltage control means 61 (61U, 61V, 61W) PWM drive section (sine wave drive means, rectangular wave drive means, sine wave amplitude modulation means, drive signal amplitude modulation means)
70 Phase synchronization unit (absolute phase information output means, phase synchronization circuit)
71 Edge detector 72 Offset generator 73 Counter (phase signal generator)
74 register 75 phase comparator (phase comparator)
76 Amplifier 77 Integrator 78 Adder 79 VCO (Pulse Signal Generator)
79b Register 80 Divider 81 Load signal generator 100 Motor drive controller

Claims (7)

A motor drive control device that rotates the rotor by passing a periodic current through a plurality of armature windings according to the rotational position of the rotor of the motor,
Position signal output means for outputting a periodic position signal according to the rotational position of the rotor, absolute phase information output means for smoothing the position signal and outputting absolute phase information according to the position signal, and A motor drive control device comprising: sine wave drive means for outputting a sine wave drive signal for causing a sine wave current to flow through the plurality of armature windings according to absolute phase information. The absolute phase information output means includes a phase synchronization circuit that is phase-synchronized with the position signal, and outputs the absolute phase information in a phase synchronization state in which the phase of the output signal of the phase synchronization circuit and the position signal are phase-synchronized. The motor drive control device according to claim 1, wherein the motor drive control device outputs the motor drive control device. The absolute phase information output means compares a plurality of predetermined reference phases respectively corresponding to each change point of the signal level of the position signal and a phase corresponding to the absolute phase information to obtain a phase difference A pulse signal generator that generates a pulse signal having a frequency corresponding to the phase difference, and a phase signal generator that generates a signal having a phase corresponding to the absolute phase information with reference to the pulse signal. The motor drive control device according to claim 1 or 2, characterized by the above-mentioned. A rectangular wave driving means for outputting a rectangular wave driving signal for causing a rectangular wave current to flow through the armature windings of the plurality of phases according to the position signal;
The motor is driven by the sine wave drive signal when the phase synchronization circuit is in the phase synchronization state, and the motor is driven by the rectangular wave drive signal when the phase synchronization circuit is not in the phase synchronization state. The motor drive control device according to claim 2 or 3. Frequency detecting means for detecting a frequency corresponding to the rotational speed of the rotor, and a frequency difference between a predetermined target frequency corresponding to the target rotational speed of the rotor and a frequency detected by the frequency detecting means. 5. The frequency difference detection means and a control signal generation means for generating a drive voltage control signal for driving the motor based on the frequency difference. The motor drive control device according to item 1. 6. The motor drive control device according to claim 5, further comprising sine wave amplitude modulation means for modulating the amplitude of the sine wave drive signal in accordance with the drive voltage control signal. 6. The motor drive control device according to claim 5, further comprising drive signal amplitude modulation means for modulating the amplitude of the sine wave drive signal and the rectangular wave drive signal in accordance with the drive voltage control signal.

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