JP2008235796A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device which has high performance by acting stress upon a field effect transistor. <P>SOLUTION: The semiconductor device includes an n-channel type field effect transistor Qn and p-channel type field effect transistor Qp, formed on a semiconductor substrate 1. The semiconductor device further has a first insulating film Z1, which is so formed as to cover both the transistors Qn and Qp to apply stress to the semiconductor substrate 1, and a second insulating film Z2 which is in contact with the first insulating film Z1 and so formed as to cover the n-channel type field effect transistor Qn from over the first insulating film Z1 so as to apply tensile stress to the semiconductor substrate 1. The thickness of the second insulating film Z2 is thinner than that of the first insulating film Z1, and one or both of them are silicon nitride films. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique effective when applied to a semiconductor device including an n-channel field effect transistor and a p-channel field effect transistor.

  A semiconductor device that processes and stores a large amount of information at a high speed is equipped with a plurality of field effect transistors called MISFETs (Metal Insulator Semiconductor Field Effect Transistors), and constitutes, for example, a logic circuit or a memory array. These field effect transistors are formed on a semiconductor substrate, and high integration of the semiconductor device has been realized by miniaturization.

  Generally, a MIS field effect transistor has a stacked structure of a gate electrode (Metal), a gate insulating film (Insulator), and a channel formation region (Semiconductor), and has a source region and a drain region for conducting to the channel formation region. It is based on a structure having

  Depending on the polarity of the carrier flowing in the channel region, an n-channel field effect transistor (hereinafter simply referred to as an n-ch transistor) when the carrier is an electron, and a p-channel field effect transistor when the carrier is a hole (hole) ( Hereinafter, this is simply referred to as a p-ch transistor).

  In recent years, as a technique for improving the performance of a semiconductor device by increasing the processing speed of a field effect transistor, a technique for applying stress to a channel region has been studied and put into practical use as a technique other than miniaturization. In n-ch transistors, it has been clarified that carrier mobility is improved by applying tensile stress to the channel region, and in p-ch transistors, carrier mobility is improved by applying compressive stress to the channel region. ing.

  Many semiconductor devices having a circuit based on a complementary logic configuration in which these bipolar transistors are paired have n-channel and p-channel field effect transistors. In order to increase the speed by applying stress to the channel region, it is necessary to apply different stresses such as tension or compression to the n-type or p-type channel region, respectively.

For example, Japanese Unexamined Patent Application Publication No. 2006-324278 (Patent Document 1) and Japanese Unexamined Patent Application Publication No. 2006-324278 are disclosed in which an insulating film having different stresses is formed on an n-ch transistor or a p-ch transistor to speed up each transistor. No. 2003-273240 (Patent Document 2) and the like.
JP 2006-324278 A JP 2003-273240 A

  However, in the technology for applying stress to the field effect transistor as described above, the present inventor has found the following problems.

  For example, in the technique disclosed in Patent Document 1, an insulating film that provides tensile stress is formed so as to cover an n-ch transistor, and an insulating film that generates compressive stress is formed so as to cover a p-ch transistor. . Here, first, for example, a first silicon nitride film causing tensile stress is deposited so as to cover both transistors at once, and the first silicon nitride film on the p-ch transistor is selectively removed by photolithography. Thereafter, for example, a second silicon nitride film that causes compressive stress is deposited, and the second silicon nitride film on the n-ch transistor is selectively removed by photolithography.

  At this time, when the first silicon nitride film on the p-ch transistor is removed by etching, the semiconductor substrate region under the p-ch transistor and the insulating film (separation part) separating the two transistors are overetched and damaged. There is a possibility to give. Thereafter, when forming a conductive plug or the like conducting to the source / drain region, a part of the electrode may run on the separation portion due to misalignment or the like. Further, the present inventors have found that when a contact electrode is formed on the separation part scraped by overetching as described above, a leakage current to the semiconductor substrate and a malfunction of the transistor are caused. For example, in the memory circuit, the leakage current to the semiconductor substrate causes an increase in power consumption in a standby state or a memory holding state. Further, the malfunction of the transistor is a cause of reducing the reliability of the semiconductor device.

  Therefore, in the technique disclosed in Patent Document 2 studied by the present inventor, a first stress film is formed so as to collectively cover the n-ch transistor and the p-ch transistor, and n-ch transistor is formed on the first stress film. A second stress film that provides a desired stress is selectively formed on either the ch transistor or the p-ch transistor. At this time, the second stress film is selectively formed by performing patterning by a photolithography method after being deposited so as to collectively cover the respective transistors in the same manner as the first stress film. At this time, when the second stress film is etched, a silicon oxide film is sandwiched in order to prevent overetching of the first stress film or the semiconductor substrate under the first stress film.

  At this time, the formation of a silicon oxide film having a small stress effect under the second stress film that is responsible for the main stress application to the transistor reduces the effect of the stress on the transistor. The inventor found out.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for improving reliability in a semiconductor device in which stress is selectively applied to an n-channel field effect transistor and a p-channel field effect transistor to improve performance. .

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a semiconductor substrate, the first insulation that is formed so as to cover both transistors and causes stress to the semiconductor substrate. And a second insulating film that is in contact with the first insulating film and that covers the n-channel field effect transistor from above the first insulating film and that causes a tensile stress on the semiconductor substrate. However, the thickness of the second insulating film is thinner than the thickness of the first insulating film, and the first insulating film, the second insulating film, or both are insulating films containing nitrogen.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, reliability can be improved in a semiconductor device in which high performance is achieved by selectively applying stress to an n-channel field effect transistor and a p-channel field effect transistor.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
In Embodiment 1 of the present invention, in a semiconductor device having an n-channel field effect transistor (hereinafter referred to as an n-ch transistor) and a p-channel field effect transistor (hereinafter referred to as a p-ch transistor), A technique for improving the performance of a transistor using a plurality of stress films will be exemplified.

  FIG. 1 is a cross-sectional view of a main part of the semiconductor device exemplified in the first embodiment.

  On the main surface of the semiconductor substrate 1, a p-type well region 2 for forming the n-ch transistor Qn and an n-type well region 3 for forming the p-ch transistor Qp are formed. , 3 are isolated from each other by an isolation portion 4 made of an insulating film. In the first embodiment, for example, the semiconductor substrate 1 is made of single crystal silicon. The isolation portion 4 has a shallow trench type STI (Shallow Trench Isolation) structure made of silicon oxide or the like, but may have a well-known field insulating film structure.

  The n-ch transistor Qn basically has a source / drain region 5n formed in the p-type well region 2 and a gate electrode 7 formed with the gate insulating film 6 interposed therebetween. In the first embodiment, the source / drain region 5n is made of an n-type semiconductor whose majority carriers are electrons, the gate insulating film 6 is made of, for example, silicon oxide, and the gate electrode 7 is made of, for example, polycrystalline silicon.

  The source / drain region 5n has a so-called extension region 8n that is shallower than that, has the same carrier polarity, and has a low carrier concentration, and the gate electrode 7 is formed on its side wall from, for example, silicon oxide. The side wall spacer 9 is provided.

  The p-ch transistor Qp is formed in the n-type well region 3 and has the same configuration as the n-ch transistor Qn. However, the source / drain region 5p and the extension region 8p, which are parts having polarity, are made of a p-type semiconductor opposite to that of the n-ch transistor Qn.

  In each of the transistors Qn and Qp described above, each of the above-described regions constituting the basic terminal, that is, the source / drain regions 5n and 5p and the gate electrode 7 are in ohmic contact with the conductive plug 10 which is electrically connected to the outside. A silicide layer 11 for realizing contact is provided on each surface. The conductive plug 10 is made of a metal mainly composed of, for example, aluminum (Al) or tungsten (W). The conductive plug 10 is formed so as to be embedded in an interlayer insulating film 12 made of, for example, silicon oxide. A similar interlayer insulating film 13 is further formed on the interlayer insulating film 12, and a wiring layer 14 is embedded in the interlayer insulating film 13 for forming a circuit configuration in conduction with other elements. The wiring layer 14 is made of a metal mainly composed of, for example, Al or copper (Cu).

  The above is a general configuration of a semiconductor device having the n-ch transistor Qn and the p-ch transistor Qp. In addition to the above, the semiconductor device illustrated in Embodiment 1 is characterized by the following structure.

  First, a first silicon nitride film (first insulating film) Z1 is formed so as to cover the n-ch transistor Qn and the p-ch transistor Qp. The first silicon nitride film Z1 is a stress film that applies stress to the single crystal silicon, that is, it applies stress to the transistors Qn and Qp formed on the semiconductor substrate 1. In the first embodiment, the stress of the first silicon nitride film Z1 may be tensile stress or compressive stress, and the difference between these effects will be described in detail later.

  Further, a second silicon nitride film (second insulating film) Z2 is formed so as to be in contact with the first silicon nitride film Z1 and to cover the n-ch transistor Qn from above the first silicon nitride film Z1. . Similarly to the above, the second silicon nitride film Z2 is a stress film that gives stress to the single crystal silicon. That is, in the first embodiment, the n-ch transistor Qn is covered with the silicon nitride films Z1 and Z2 as the two layers of stress films. In particular, in the first embodiment, it is assumed that the stress of the second silicon nitride film Z2 of the second layer is a tensile stress.

  Here, the effect will be described in detail with respect to the case where the first silicon nitride film Z1 covering the transistors Qn and Qp is a stress film that causes compressive stress. At this time, since the stress film covering the p-ch transistor Qp is only the first silicon nitride film Z1, the carrier mobility is improved by the compressive stress in this state, and the performance of the p-ch transistor Qp is improved.

  On the other hand, in the n-ch transistor Qn, if only the effect of the first silicon nitride film Z1 causing the compressive stress is seen, the carrier mobility is lowered by the compressive stress. In order to avoid this problem, the technique studied by the present inventors has removed the first silicon nitride film Z1 on the n-ch transistor Qn and patterned another stress film that brings about tensile stress. However, in the photolithography process for removing the first silicon nitride film Z1, there is another problem that the n-ch transistor Qn is damaged particularly by the etching process and a leak current is generated in the source / drain region 5n, for example. It was generated.

  On the other hand, in the first embodiment, the first silicon nitride film Z1 on the n-ch transistor Qn is left without being removed and brought into contact with it to bring another layer of stress film, that is, tensile stress. A second silicon nitride film Z2 is formed. Thereby, the compressive stress of the first silicon nitride film Z1 that lowers the carrier mobility of the n-ch transistor Qn can be offset. Furthermore, if the second silicon nitride film Z2 is a stress film that provides a stronger tensile stress, the stress applied to the n-ch transistor Qn can be made a total tensile stress, and the performance of the n-ch transistor Qn can be improved. Can do.

  Next, the effect will be described in detail with respect to the case where the first silicon nitride film Z1 covering the transistors Qn and Qp is a stress film that brings about a tensile stress. Regarding the n-ch transistor Qn, in addition to the first silicon nitride film Z1, the second silicon nitride film Z2 that provides tensile stress is formed as a second stress film, so that a stronger tensile stress can be applied. The carrier mobility of the n-ch transistor Qn is improved and the performance is improved.

  On the other hand, only the first silicon nitride film Z1 having a tensile stress is formed on the p-ch transistor Qp, and the carrier mobility is lowered. At this time, the method of removing the first silicon nitride film Z1 on the p-ch transistor Qp and forming a different compressive stress film investigated by the present inventor causes damage to the transistor itself by etching, as described above. End up.

  Here, it is known that germanium (Ge) is ion-implanted into a silicon nitride film having a tensile stress, thereby reducing the stress. Therefore, in the first embodiment, germanium is ion-implanted into the first silicon nitride film Z1 on the p-ch transistor Qp, so that the tensile stress is relaxed, and the original p-ch transistor Qp has the same structure. It is possible to maintain performance. In particular, in view of side effects when reaching the semiconductor substrate 1 during ion implantation, it is more desirable to use the same group IV element as silicon, and from this point of view, the germanium element is optimal. In the first embodiment, germanium is used as the ion species to be implanted, but here, the purpose is to relieve the stress of the second silicon nitride film Z2 that brings about tensile stress, and it is desirable that the atomic weight is large. It is not limited to germanium.

  In the first embodiment, the second silicon nitride film Z2 is thinner than the first silicon nitride film Z1. Thus, when patterning by photolithography is performed, in which the second silicon nitride film Z2 is left on the n-ch transistor Qn and is removed by etching on the p-ch transistor Qp, the first nitridation of the first layer is performed. Since the silicon film Z1 is thick, the p-ch transistor Qp is not damaged by etching. Therefore, as indicated as a problem above, no leak current is generated in the source / drain region 5p, for example. As a result, the reliability of the semiconductor device can be improved. Further, there is no need to form an etch stop layer between the first silicon nitride film Z1 and the silicon nitride films Z1 and Z2 in contact with each other without etching the second silicon nitride film Z2 on the p-ch transistor Qp. The structure can be made. As a result, the stress action of the second silicon nitride film Z2 is not relaxed by the etch stop layer, and the effect can be exhibited. Details of a specific manufacturing process will be described later.

  As described above, according to the technique exemplified in the first embodiment, reliability is improved in a semiconductor device in which stress is selectively applied to an n-channel field effect transistor and a p-channel field effect transistor to improve performance. Can be improved.

  Next, a manufacturing method of the semiconductor device having the configuration described above in the first embodiment will be described with reference to FIGS.

  First, as shown in FIG. 2, n-ch transistor Qn and p-ch transistor Qp are formed on the main surface of semiconductor substrate 1. The method is the same as usual and will not be described in detail here. The configuration of each transistor Qn, Qp is as described above.

  Thereafter, as shown in FIG. 3, a first silicon nitride film Z <b> 1 that applies stress to the semiconductor substrate 1 is formed so as to cover both the transistors Qn and Qp. In the first embodiment, the first silicon nitride film Z1 is formed by, for example, a chemical vapor deposition (CVD) method.

  Subsequently, a second silicon nitride film Z2 that applies tensile stress to the semiconductor substrate 1 is formed so as to cover the first silicon nitride film Z1 and to be thinner than the thickness of the first silicon nitride film Z1. To do. In the first embodiment, the second silicon nitride film Z2 is formed by, for example, a CVD method.

  Thereafter, as shown in FIG. 4, a photoresist film 15 is applied so as to cover the second silicon nitride film Z2. The photoresist film 15 is patterned by ordinary photolithography so as to remain on the n-ch transistor Qn and to be removed on the p-ch transistor Qp.

  Next, as shown in FIG. 5, when the second silicon nitride film Z2 is etched using the photoresist film 15 as an etching mask and the exposed second silicon nitride film Z2 is removed, the first layer is formed. Etching is stopped leaving the first silicon nitride film Z1. As a result, two layers of stress films, ie, a first silicon nitride film Z1 and a second silicon nitride film Z2, remain on the n-ch transistor Qn, and the second silicon nitride film Z2 is left on the p-ch transistor Qp. The structure is removed, and only the first silicon nitride film Z1 remains as a stress film.

  At this time, since the second silicon nitride film Z2 of the second layer is thinner than the first silicon nitride film Z1, it is not possible to stop etching by removing the thin second silicon nitride film Z2 of these stacked structures. It can be easily performed by controlling the etching time. Even if some over-etching is caused in the first silicon nitride film Z1, the etching reaches the p-ch transistor Qp and the possibility of damaging the transistor itself is low. As described above, since the step of partially removing the first silicon nitride film Z1 of the first layer as in the method studied by the present inventor is not included, the leakage current in the contact formation portion is reduced by a subsequent process, for example. Does not cause damage. As a result, according to the technique exemplified in the first embodiment, the reliability of the semiconductor device can be improved. Furthermore, since the second silicon nitride film Z2 is thinned, selective etching can be easily controlled with time, so that it is not necessary to form an etch stop layer or the like between the first silicon nitride film Z1 and n-ch. The effect of stress on the transistor Qn is not relaxed.

  By the way, in Embodiment 1, in order to selectively expose the region where the transistor is formed as described above, it is not necessary to have such a fine processing accuracy as to process the gate electrode 7 of the transistor itself, for example. However, if it is necessary to form a finer pattern in this process as the miniaturization proceeds in the future, for example, an antireflection film (BARC: Bottom-Anti-Reflection Coating) is used as the base of the photoresist film 15. May be formed.

  Further, when a stress film that brings about a tensile stress is formed as the first silicon nitride film Z1, the tensile stress is relaxed on the p-ch transistor Qp in order to recover the performance of the p-ch transistor Qp. You may need it. At this time, after the above-described process, for example, germanium element is ion-implanted into the first silicon nitride film Z1 covering the p-ch transistor Qp using the photoresist film 15 as an ion implantation mask to relieve the tensile stress. Can do.

  Thereafter, as shown in FIG. 6, the photoresist film 15 is removed, and an interlayer insulating film 12 is deposited. In the first embodiment, as the interlayer insulating film 12, for example, silicon oxide or the like is formed by a CVD method or the like. Subsequently, contact holes 16 are formed by an ordinary photolithography method in order to establish electrical conduction to the source / drain regions 5n, 5p and the gate electrode 7.

  Here, in the first embodiment, the interlayer insulating film 12, the isolation part 4, and the sidewall spacer 9 are formed of the same silicon oxide film. Therefore, if a different kind of intermediate film (so-called liner film) does not exist between the interlayer insulating film 12 and the isolation portion 4 or the sidewall spacer 9, when misalignment occurs when forming the contact hole 16, It is impossible to stop over-etching on the separation portion 4 and the sidewall spacer 9. Forming the conductive plug 10 in the overetched separation portion 4 or the like in this manner can cause a decrease in the reliability of the semiconductor device, such as an increase in leakage current. In order to avoid this problem, it is necessary to design with a margin in advance as a margin for misalignment when the contact hole 16 is formed. This becomes a cause of hindering performance enhancement of the semiconductor device due to miniaturization of the transistor.

  On the other hand, according to the technique exemplified in the first embodiment, the main surface of the semiconductor substrate 1 including the transistors Qn and Qp is covered with the first silicon nitride film Z1. As a result, when the interlayer insulating film 12 formed of the silicon oxide film is anisotropically etched, the etching can be stopped in a self-aligned manner by using a condition with a high selection ratio with respect to the first silicon nitride film Z1. . Subsequently, anisotropic etching is performed on the first silicon nitride film Z1 under a condition having a high selectivity with respect to the silicon oxide film. Thereby, even if the contact hole 16 partially rides on the separation portion 4 or the sidewall spacer 9 due to misalignment, the etching can be stopped in a self-aligning manner. That is, according to the technique exemplified in the first embodiment, by leaving the first silicon nitride film Z1, it is not necessary to provide a large margin for misalignment when forming the contact hole 16, and the semiconductor device is improved by miniaturization. Performance can be promoted.

  In the structure of the semiconductor device illustrated in the first embodiment, the n-ch transistor Qn is covered with a silicon nitride film that is thicker than the p-ch transistor Qp, qualitatively. Although the second silicon nitride film Z2 of the second layer is thin, when the contact hole 16 is formed in both the transistors Qn and Qp in the same process, the silicon nitride film on the n-ch transistor Qn is etched. However, it takes longer time. As a result, there is a possibility of overetching the source / drain region 5p of the p-ch transistor Qp. Even if the etching selectivity between the silicide layer 11 to be contacted and the silicon nitride film is increased, it is necessary to take a long etching time. Can not.

  For this purpose, the second silicon nitride film left on the n-ch transistor Qn in the step of selectively removing the second silicon nitride film Z2 on the p-ch transistor Qp described with reference to FIGS. It is effective to consider the dimensions of the photoresist film 15 that protects Z2 from anisotropic etching. Details will be described below. In the first embodiment, the channel region under the gate electrode 7 of the n-ch transistor Qn is mainly the region where the second silicon nitride film Z2 is to be subjected to stress. That is, the photoresist film 15 may be left so as to protect the second silicon nitride film Z2 around the gate electrode 7 of the n-ch transistor Qn, and may be removed near the source / drain region 5n. As a result, the thickness of the silicon nitride film that must be etched by anisotropic etching to form the contact hole 16 is substantially equal on the n-ch transistor Qn and the p-ch transistor Qp. As a result, overetching of the source / drain region 5p in the p-ch transistor Qp as described above can be avoided.

  Thereafter, as shown in FIG. 7, a metal film containing, for example, Al or W is buried in the contact hole 16 to form the conductive plug 10. Further, an interlayer insulating film 13 is formed from above by the same method, and a wiring layer 14 is formed for electrical connection with other elements to form a circuit configuration. The wiring layer 14 is assumed to be a metal film containing, for example, Al or Cu.

  A desired semiconductor device is formed by repeating plug / wiring formation on the upper layer by the same method as described above.

  As described above, the semiconductor device exemplified in the first embodiment can be manufactured.

(Embodiment 2)
In the first embodiment, the technique for realizing high performance of the transistor by stress control by forming two layers of stress films on the n-ch transistor Qn has been exemplified. In the second embodiment, a technique for forming a two-layer stress film on the p-ch transistor Qp and performing stress control and the effect thereof will be described in detail.

  FIG. 8 is a cross-sectional view of main parts of the semiconductor device illustrated in the second embodiment.

  The configuration of each of the transistors Qn and Qp is the same as that in the first embodiment, and a detailed description thereof is omitted here. What is characteristic in the second embodiment is the configuration shown below.

  First, a first silicon nitride film (first insulating film) Z1 is formed so as to cover the n-ch transistor Qn and the p-ch transistor Qp. The first silicon nitride film Z1 is a stress film that applies stress to the single crystal silicon, that is, it applies stress to the transistors Qn and Qp formed on the semiconductor substrate 1. In the first embodiment, the stress of the first silicon nitride film Z1 may be tensile stress or compressive stress, and the difference between these effects will be described in detail later.

  Further, a second silicon nitride film (second insulating film) Z2 is formed so as to be in contact with the first silicon nitride film Z1 and cover the p-ch transistor Qp from above the first silicon nitride film Z1. . Similarly to the above, the second silicon nitride film Z2 is a stress film that gives stress to the single crystal silicon. That is, in the second embodiment, the p-ch transistor Qp is covered with the silicon nitride films Z1 and Z2 as the two stress films. In particular, in the second embodiment, it is assumed that the stress of the second silicon nitride film Z2 of the second layer is a compressive stress.

  Here, the details of the effect will be described with respect to the case where the first silicon nitride film Z1 covering the transistors Qn and Qp is a stress film that brings about a tensile stress. At this time, since the stress film covering the n-ch transistor Qn is only the first silicon nitride film Z1, in this state, the carrier mobility is improved by the tensile stress, and the n-ch transistor Qn has high performance.

  On the other hand, in the p-ch transistor Qp, if only the effect of the first silicon nitride film Z1 causing the tensile stress is seen, the carrier mobility is lowered by the tensile stress. At this time, the method of removing the first silicon nitride film Z1 on the p-ch transistor Qp and forming a different compressive stress film investigated by the present inventor causes damage to the transistor itself by etching, as described above. End up. This causes another problem of generating a leak current in the source / drain region 5p, for example.

  On the other hand, in the second embodiment, the first silicon nitride film Z1 on the p-ch transistor Qp is left without being removed, and a second stress film, that is, a compressive stress is brought into contact therewith. A silicon dinitride film Z2 is formed. As a result, the tensile stress of the first silicon nitride film Z1 that reduces the carrier mobility of the p-ch transistor Qp can be offset. Furthermore, if the second silicon nitride film Z2 is a stress film that provides a stronger compressive stress, the stress applied to the p-ch transistor Qp can be made a compressive stress as a whole, and the performance of the p-ch transistor Qp can be improved. Can do.

  Next, the effect will be described in detail with respect to the case where the first silicon nitride film Z1 covering the transistors Qn and Qp is a stress film that causes compressive stress. Regarding the p-ch transistor Qp, in addition to the first silicon nitride film Z1, the second silicon nitride film Z2 that provides compressive stress is formed as the second-layer stress film, so that stronger compressive stress can be applied. The carrier mobility of the p-ch transistor Qp is improved and the performance is improved.

  In the second embodiment, it is assumed that the thickness of the second silicon nitride film Z2 is thinner than the thickness of the first silicon nitride film Z1. As a result, similarly to the effect described in the first embodiment, the second silicon nitride film Z2 as the second layer can be etched without damaging the n-ch transistor Qn. As a result, the reliability of the semiconductor device can be improved. Further, there is no need to form an etch stop layer between the first silicon nitride film Z1 and the silicon nitride films Z1, Z2 in contact with each other, without etching the second silicon nitride film Z2 on the n-ch transistor Qn. The structure can be made. As a result, the stress action of the second silicon nitride film Z2 is not relaxed by the etch stop layer, and the effect can be exhibited.

  As described above, according to the technique exemplified in the second embodiment, reliability is improved in a semiconductor device in which stress is selectively applied to an n-channel field effect transistor and a p-channel field effect transistor to improve performance. Can be improved.

  The semiconductor device having the structure exemplified in the second embodiment is applied with a modification in which the second silicon nitride film Z2 is a stress film that causes compressive stress and is patterned so as to remain on the p-ch transistor Qp. For example, it can be manufactured in the same manner as the semiconductor device having the structure described in the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first and second embodiments, the two layers of stress films to be subjected to stress control are the silicon nitride films Z1 and Z2, but they do not have to be the same type, and any stress film that provides a desired stress can be used. The same effect can be obtained by applying. If a stress film different from the first layer is used as the second stress film, the second stress film can be selectively etched away with higher accuracy.

  In the first and second embodiments, the MIS type field effect transistor is used as the element to which the stress is applied. However, as long as the element can improve the performance of the semiconductor device by improving the carrier mobility. The same effect can be obtained by applying.

  The present invention can be applied to the semiconductor industry required for information processing, for example, in personal computers and mobile devices.

It is principal part sectional drawing of the semiconductor device which is one embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; It is principal part sectional drawing of the semiconductor device which is other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 P-type well area | region 3 N-type well area | region 4 Separation part 5n, 5p Source / drain area | region 6 Gate insulating film 7 Gate electrode 8n, 8p Extension area | region 9 Side wall spacer 10 Conductive plug 11 Silicide layer 12, 13 interlayer Insulating film 14 Wiring layer 15 Photoresist film 16 Contact hole Qn n-ch transistor (n-channel field effect transistor)
Qp p-ch transistor (p-channel field effect transistor)
Z1 first silicon nitride film (first insulating film)
Z2 Second silicon nitride film (second insulating film)

Claims (5)

A semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a semiconductor substrate,
(A) a first insulating film which is formed so as to cover the n-channel field effect transistor and the p-channel field effect transistor and which brings tensile or compressive stress on the semiconductor substrate;
(B) Second insulation that is in contact with the first insulating film and that covers the n-channel field effect transistor from above the first insulating film and that causes tensile stress to the semiconductor substrate. And having a membrane
The thickness of the second insulating film is thinner than the thickness of the first insulating film,
The semiconductor device, wherein the first insulating film, the second insulating film, or both are insulating films containing nitrogen. The semiconductor device according to claim 1,
A portion of the first insulating film covering the p-channel field effect transistor contains germanium. A semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor formed on a semiconductor substrate,
(A) a first insulating film which is formed so as to cover the n-channel field effect transistor and the p-channel field effect transistor and which brings tensile or compressive stress to the semiconductor substrate;
(B) Second insulation that is in contact with the first insulating film and that covers the p-channel field effect transistor from above the first insulating film and that causes compressive stress to the semiconductor substrate. And having a membrane
The thickness of the second insulating film is thinner than the thickness of the first insulating film,
The semiconductor device, wherein the first insulating film, the second insulating film, or both are insulating films containing nitrogen. (A) forming an n-channel field effect transistor and a p-channel field effect transistor on the main surface of the semiconductor substrate;
(B) forming a first insulating film that covers the n-channel field effect transistor and the p-channel field effect transistor so as to provide a tensile or compressive stress to the semiconductor substrate;
(C) A step of forming a second insulating film that covers the first insulating film and that is thinner than the first insulating film and that causes tensile or compressive stress on the semiconductor substrate. When,
(D) Select the other portion of the second insulating film so that the second insulating film remains on either the n-channel field effect transistor or the p-channel field effect transistor. And removing the
The method of manufacturing a semiconductor device, wherein the first insulating film, the second insulating film, or both are insulating films containing nitrogen. In the manufacturing method of the semiconductor device according to claim 4,
The second insulating film formed in the step (c) brings about a tensile stress on the semiconductor substrate,
The step (d) is a step of selectively removing the other portion of the second insulating film so that the second insulating film remains on the n-channel field effect transistor.
A method of manufacturing a semiconductor device, comprising a step of implanting germanium into a portion of the first insulating film covering the p-channel field effect transistor.

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