JP2008227567A - Phase interpolator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase interpolator for regulating a minute phase to be programmable, regardless of the process conditions, power supply voltage, and temperature variations. <P>SOLUTION: A clock of irregular interval is inputted to the feedback signal (FBCLK) of a PLL circuit, and a minute phase difference is given between a reference signal REFCLK and the feedback signal FBCLK by the essential phase matching function of the PLL circuit. Furthermore, a phase difference free from the process conditions, power supply voltage, and temperature dependency is achieved by using a charge pump (CP) circuit where the up and down currents are equal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a phase interpolator, and more particularly to a phase interpolator that can adjust a minute phase in a programmable manner regardless of variations in process conditions, power supply voltage, and temperature.

  Conventionally, when adjusting the phase of a clock signal or the like, it is common to adjust the phase by inputting a clock signal or the like to a delay cell and switching the number of stages or combinations of the delay cells to output. It is done. Also, the phase of the delay cell is adjusted by changing the value of the delay cell by changing the value of the capacitor or the resistor constituting the delay cell. Further, there is a method of adjusting the phase by combining a delay cell and a PLL (phase locked loop) circuit.

  Here, the PLL circuit refers to an oscillation circuit that outputs a signal in which the frequency and phase of the input clock signal are synchronized by feedback control, and generally includes a phase frequency comparison circuit (PFD) 51, as shown in FIG. A charge pump circuit (CP) 52, a loop filter (LF) 53, a voltage controlled oscillation circuit (VCO) 54, and an N frequency divider (N-DIV) 55 are included. In the PLL circuit 50 shown in FIG. 7, the reference signal REFCLK is given from the outside, and the phase / frequency difference between the reference signal REFCLK and the feedback signal FBCLK obtained by dividing the oscillation output signal PLLOUT of the voltage control oscillation circuit 54 by N is the phase frequency. The comparison circuit 51 compares them. An up signal UP and a down signal DOWN corresponding to the phase / frequency difference are output from the phase frequency comparison circuit 51 to the charge pump circuit 52. The charge pump circuit 52 supplies charges to the loop filter 53 or extracts charges from the loop filter 53 in accordance with the up signal UP and the down signal DOWN from the phase frequency comparison circuit 51. A control signal VCONT determined by the electric charge accumulated in the capacitance of the loop filter 53 is input to the voltage control oscillation circuit 54, and the voltage control oscillation circuit 54 outputs an oscillation output signal PLLOUT having a frequency corresponding to the control voltage VCONT.

  Thus, the phase / frequency difference between the reference signal REFCLK and the feedback signal FBCLK obtained by dividing the oscillation output signal PLLOUT of the voltage controlled oscillation circuit 54 by N is detected, and the oscillation output signal of the voltage controlled oscillation circuit 54 is detected accordingly. By repeatedly changing the oscillation frequency of PLLOUT, the phase and frequency between the reference signal REFCLK and the feedback signal FBCLK are synchronized (locked).

A technique for adjusting the phase by combining such a PLL circuit and the above-described delay cell is disclosed in Patent Document 1. According to Patent Document 1, a variable delay circuit capable of adjusting a delay width is provided in front of a reference side input terminal of a PLL circuit, and a clock signal input to a latch circuit at the final stage is supplied to the PLL via the variable delay circuit. By returning to the circuit configuration, it is possible to adjust the delay width in the variable delay circuit even when the LSI process conditions, power supply voltage level, and temperature fluctuate, thereby reducing clock skew between LSIs. I can do it.
JP-A-8-321773

  By the way, when adjusting the phase by switching the number and combination of delay cells, the minimum unit of phase adjustment is a delay for one delay cell. Impossible. In addition, when the phase is adjusted by the capacitance and resistance that make up the delay cell, finer adjustment is possible, but in either method, the delay value depends greatly on process conditions, power supply voltage, and temperature fluctuations. There is a possibility that the chip does not operate under one delay adjustment condition because the delay value is different only by different use conditions.

  An object of the present invention is to provide a phase interpolator that can solve the problems based on the above-described prior art and can adjust a minute phase in a programmable manner even if process conditions, power supply voltage, and temperature fluctuate.

  In order to achieve the above object, the present invention provides a PLL circuit including a phase frequency comparison circuit, a charge pump circuit, a loop filter, a voltage controlled oscillation circuit, and a feedback N divider, and the voltage controlled oscillation circuit. An N divider for output that outputs an output signal obtained by dividing the oscillation output signal by N, and the N divider for feedback is included in 2N clocks of the oscillation output signal output from the voltage controlled oscillator circuit. A phase interpolator is provided that selects any two of them to generate non-equal intervals of clocks and outputs them as feedback signals to the phase frequency comparison circuit.

  The charge pump circuit is preferably a charge pump circuit in which an up current for supplying charge to the loop filter is equal to a down current for extracting charge from the loop filter.

  And a reset circuit for resetting the output N divider, the reset circuit receiving the signal synchronized with the feedback signal from the feedback N divider after the PLL circuit is locked. It is preferable to release the reset of the N divider and output the output signal.

  The phase interpolator of the present invention inputs a non-equal interval clock as the feedback signal (FBCLK) of the PLL circuit. However, a small phase difference between the reference signal REFCLK and the feedback signal FBCLK is provided by the phase matching function originally provided in the PLL circuit. Can be given. Also, by using a charge pump circuit in which the up current (current that supplies charge to the loop filter) and down current (current that draws charge from the loop filter) are equal (symmetrical), process conditions, power supply voltage, and temperature fluctuations Even if there is a phase difference, the phase difference hardly changes and a phase difference having no dependency on various conditions can be realized.

  Hereinafter, a phase interpolator of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

  FIG. 1 is a diagram showing an example of the configuration of the phase interpolator of the present invention. A phase interpolator 10 shown in FIG. 1 includes a phase frequency comparison circuit (PFD) 11, a charge pump circuit (CP) 12, a loop filter (LF) 13, a voltage controlled oscillation circuit (VCO) 14, and an N divider for feedback. A PLL circuit 20 composed of (N-DIV) 15, an output N frequency divider 16, and a flip-flop (F / F) 17 are provided. In this configuration, both the feedback N divider 15 and the output N divider 16 are 8 dividers that divide the input signal (the oscillation output signal PLLOUT of the voltage controlled oscillation circuit) by 8.

  In the PLL circuit 20 constituting the phase interpolator 10, the phase / frequency difference between the reference signal REFCLK and the feedback signal FBCLK obtained by dividing the oscillation output signal PLLOUT of the voltage controlled oscillation circuit 14 is compared by the phase frequency comparison circuit 11. Charge is supplied from the charge pump circuit 12 to the loop filter 13 or extracted from the loop filter 13 by the up signal UP and the down signal DOWN according to the phase / frequency difference, and the voltage controlled oscillation circuit 14 responds to the control voltage determined by the charge. An oscillation output signal PLLOUT having a predetermined frequency is output. In the conventional PLL circuit described above, the reference signal REFCLK and the reference signal REFCLK are changed by repeatedly changing the oscillation frequency of the oscillation output signal PLLOUT until the phase / frequency difference between the reference signal REFCLK and the feedback signal FBCLK is minimized. The phase and frequency with the feedback signal FBCLK are locked. However, in the case of the PLL circuit 20 in this configuration, the oscillation frequency of the oscillation output signal PLLOUT is repeatedly changed until the phase / frequency difference between the reference signal REFCLK and the feedback signal FBCLK reaches a predetermined value as will be described later. The phase and frequency between the signal REFCLK and the feedback signal FBCLK are locked.

  Here, in the case of the frequency divider used in the conventional PLL circuit, the feedback signal FBCLK that is the output has equal intervals between the rising edges. On the other hand, in the feedback 8-divider 15 used in this configuration, the feedback signal FBCLK does not have equal intervals between rising edges. The feedback 8 frequency divider 15 is a frequency divider capable of adjusting the output edge position of the feedback signal FBCLK, and can select any two clocks having different edge positions from 16 clocks of the oscillation output signal PLLOUT. Yes. Such a non-uniformly spaced feedback signal FBCLK is input to the phase frequency comparison circuit 11, and a desired minute phase difference is given between the reference signal REFCLK and the feedback signal FBCLK by a phase matching function originally provided in the PLL circuit. Can do. Further, by making the up current and the down current of the charge pump circuit 12 of the PLL circuit 20 in this configuration equal (symmetric), a phase in which the phase difference does not fluctuate even if the process conditions, power supply voltage, and temperature fluctuate. An interpolator can be realized.

  The flip-flop 17 shown in FIG. 1 is a reset circuit that resets the output divide-by-eight divider 16, and is at the “L” level before the PLL circuit 20 is locked to the D terminal, and at the “H” level after the lock. The enable signal EN_DIV is input, and the start signal DIV_START, which is the operation start timing of the output 8 divider 16 at the “H” level, is input to the CK terminal from the feedback 8 divider 15 and output from the Q terminal. A reset signal DIV_RST for resetting the divide-by-8 divider 16 is output. The output 8 divider 16 receives the output of the PLL circuit 20 (oscillation output signal of the voltage controlled oscillation circuit 14) PLLOUT, and when the reset signal DIV_RST becomes "H" level, the output 8 divider The reset state of the device 16 is released, and an output signal CLKOUT obtained by dividing the oscillation output signal PLLOUT by 8 is output. In other words, the output 8 divider 16 outputs the output signal CLKOUT whose phase is adjusted starting from the “H” level of the reset signal DIV_RST.

FIG. 2 is a diagram showing an example of a circuit of the feedback divide-by-8 divider 15 shown in FIG. As shown in FIG. 2, the feedback divide-by-eight divider 15 includes an inverter 40 for inverting the input signal IN (oscillation output signal PLLOUT), and an inverted signal of the input signal IN divided by 2, 4, and 8 respectively. Flip-flops (F / F) 36, 37, 38, 39 that divide by 16, inverters 41, 42, 43, 44 that invert the outputs of these F / Fs 36, 37, 38, 39, F / Fs 36, Sixteen 5-input ANDs 45 that receive the outputs Q of 37, 38, and 39 and their inverted outputs Q_ as their inputs, and four 4-input ORs 46 that collectively input the outputs of each of these five-inputs AND45. And a 4-input OR 47 having the outputs of the four 4-input ORs 46 as inputs, and a 2-input AND 48 having the inputs of the input signal IN and the outputs of the 4-input OR 47 as inputs. That. Further, control signals S0, S1,..., S15 are input to each 5-input AND 45.
The feedback 8 divider 15 receives the inverted output Q_ of the F / F 36 and the inverted output Q_ of the F / F 37 and inputs the output to the D terminal of the F / F 37, and the F / F 36. The 2-input AND 31 that takes the logical product of the inverted output Q_ of the F / F 37, the output of the 2-input AND 31 and the inverted output Q_ of the F / F 38 are input, and the output is input to the D terminal of the F / F 38 2-input ENOR 34, F / F 36 inverted output Q_, F / F 37 inverted output Q_, and F / F 38 inverted output Q_ are ANDed, and 3-input AND 32 output and F / F 39 inverted A two-input ENOR 35 for inputting the output Q_ and inputting the output to the D terminal of the F / F 39 is provided.

  Although details will be described later from the feedback 8 divider 15, the start signal DIV_START, which becomes the operation start timing of the output 8 divider 16 at the “H” level described above, is selected by the control signal S 5. Output from the input AND45.

  FIG. 3 is a diagram illustrating an example of the operation of the feedback 8 divider 15 shown in FIG. 2. The output Q of each F / F, the inverted output Q_ with respect to the input signal IN, and the output signal of the feedback 8 divider The operation state of OUT (FBCLK) is shown. Here, the outputs and inverted outputs of the F / Fs 36, 37, 38, 39 are respectively Q (a), Q (b), Q (c), Q (d) and Q (a) _, Q (b) _ , Q (c) _, Q (d) _.

  As shown in FIG. 3, the F / F 36 generates an output Q (a) obtained by dividing the input signal IN by two by repeating “H” output and “L” output at the timing when the input signal IN falls each time. . Similarly, an output Q (b) obtained by dividing the input signal by 4 is generated by the 2-input ENOR 33 and the F / F 37, and an output Q (c) obtained by dividing the input signal by 8 by the 2-input AND 31, the 2-input ENOR 34, and the F / F 38 is generated. Then, an output Q (d) divided by 16 by the 3-input AND 32, 2-input ENOR 35, and F / F 39 is generated. These outputs Q (a), Q (b), Q (c), Q (d) and their inverted outputs Q (a) _, Q (b) _, Q (c) _, Q (d) _ 4 are combined and input to 16 5-input ANDs 45. Also, 16 control signals S0 to S15 are input to each of the 16 5-input ANDs 45, and the corresponding 5-input AND 45 is selected when the logical state is “H”. For example, when S1 is “H” and the outputs Q (a), Q (b), Q (c), and Q (d) are all “H”, the second five inputs from the left shown in FIG. The output from the AND 45 becomes “H”, and the output OUT becomes “H” due to the logical product of the input signal IN with the 2-input AND 48 via the 4-input EORs 46 and 47. For example, when S2 is “H” and the outputs Q (a) _, Q (b), Q (c), and Q (d) are “H”, the third from the left shown in FIG. The output from the 5-input AND 45 becomes “H”, and the output signal OUT becomes “H” by the logical product of the 2-input AND 48 and the input signal IN via the 4-input EORs 46 and 47. Therefore, as shown in FIG. 3, when S1 is “H”, the output OUT becomes “H” at the first (# 1) edge of the input signal IN, and when S2 is “H”, the second (# The output OUT becomes “H” at the edge of 2), and thereafter, similarly, the output edge position of the output signal OUT is selected by the control signals S0 to S15. In the case of this operation, the feedback frequency divider 15 divides by 8. Therefore, by combining two of these 16 control signals to “H”, two clocks having arbitrary edge positions can be obtained. Can be output.

  FIG. 4 is a diagram illustrating an example of the operation of the clock divided by 8 that is output at an arbitrary edge position by the feedback 8 divider 15 illustrated in FIG. When an input signal IN (oscillation output signal PLLOUT) as shown in FIG. 4 is input to the feedback 8 divider 15, for example, the output (A), as the feedback signal FBCLK, is set by the control signals S 0 to S 15. Clocks with different edge positions are generated as in (B) and (C). For example, the output (A) is obtained by setting the control signals S1 and S9 to “H” (other control signals are “L”, the same applies hereinafter), and the output (B) is obtained by setting the control signals S1 and S5 to “H”. The output (C) is obtained by setting the control signals S1 and S2 to “H”. In this operation, two clocks are selected from the 16 clocks of the oscillation output signal PLLOUT and set to generate a feedback signal divided by 8 at non-equal intervals. May be selected (divide by 16), or any two of 64 clocks may be selected (divide by 32). In this case, however, the output frequency divider also needs to be divided by 16 and 32 in accordance with them.

  FIG. 5 is a diagram showing an example of the operation of the phase interpolator 10 of the present invention. [A], [B], and [C] in FIG. 5 correspond to the operation outputs (A), (B), and (C) of the feedback 8-divider 15 shown in FIG. As described above, the output (A) is obtained by setting the control signals S1 and S9 to “H”, and the output (B) is obtained by setting the control signals S1 and S5 to “H” and the output (C ) Is a waveform obtained by setting the control signals S1 and S2 to “H”.

  The CP state shown in FIG. 5 is the state of the output (CPOUT) of the charge pump circuit 12 output according to the phase / frequency difference from the phase frequency comparison circuit, and the UP state in which the up signal is output. It takes three states: a state in which an up current flows, a DOWN state in which a down signal is output (a state in which a down current flows), and a Z state in which neither is output (a high impedance state).

  In FIG. 5A, the rising edges of the reference signal REFCLK and the feedback signal FBCLK coincide and the output of the charge pump circuit 12 is balanced in the Z state.

  On the other hand, in FIGS. 5B and 5C, since the reference signal REFCLK and the feedback signal FBCLK do not match, the output state of the charge pump circuit 12 always repeats the UP state and the DOWN state, respectively. For example, in the case of FIG. 5B, it is determined that the feedback signal FBCLK is delayed because the feedback signal FBCLK is “L” level at the first rising edge of the reference signal REFCLK, and the output of the charge pump circuit 12 is set to the UP state. To do. Thereafter, when the feedback signal FBCLK rises, the Z state is reached. Further, at the rising edge of the next feedback signal FBCLK, the reference signal REFCLK is at the “L” level, so that the feedback signal FBCLK is advanced and the output of the charge pump circuit is determined. Is in the DOWN state. Here, when the amount of current of the up current and the amount of down current of the charge pump circuit 12 are equal, the amount of charge injected / released is the same at the position where the time of the UP state and the DOWN state becomes equal, that is, both the UP and DOWN states. The balance position does not change even if the process conditions, power supply voltage, and temperature fluctuate. In the case of [B] in FIG. 5, since the control signals S1 and S5 are “H”, the UP and DOWN states are respectively for the oscillation output signal PLLOUT2 clocks, the Z state is 4 clocks, and the feedback signal FBCLK is the reference signal REFCLK. Further, it is stable at a position where the phase is shifted by two clocks, that is, a position where the phase is shifted by 2/8 * T (T is the period of the reference signal).

  In the case of [C] in FIG. 5, since the control signals S1 and S2 are “H”, the UP and DOWN states are respectively the oscillation output signal PLLOUT 3.5 clocks, the Z state is one clock, and the feedback signal FBCLK is the reference. Stable at a position where the phase is shifted by 3.5 clocks from the signal REFCLK, that is, a position where the phase is shifted by 3.5 / 8 * T.

  In each of [A], [B], and [C] in FIG. 5, after the phase difference is stabilized, the enable signal EN_DIV that notifies the locked state becomes “H”. When the start signal DIV_START notifying the start of the output from the feedback 8 divider 15 becomes “H”, the reset signal DIV_RST from the F / F 17 becomes “H”, and the reset of the output 8 divider 16 is released. As a result, the output signal CLKOUT rises. In this operation, as shown in FIG. 2, the output of the 5-input AND 45 selected by the control signal S1 is output from the feedback 8-divider 15 as the start signal DIV_START. Therefore, the output signal CLKOUT is output in synchronization with the feedback signal FBCLK selected by the control signal S1.

  As described above, according to the present invention, a phase interpolator almost independent of process conditions, power supply voltage, and temperature can be realized. The minimum unit of controllable phase in this operation is 0.5 / 8 * T = T / 16, but a 16 divider or 32 divider having the same function as described above is used. Then, the controllable minimum unit of phase difference can be set more finely, and the minimum unit of adjustable phase difference can be set to T / 32 and T / 64, respectively.

  By the way, the charge pump circuit 12 constituting the phase interpolator of the present invention is preferably a circuit as shown in FIG. 6, for example, and as described above, the current amounts of the up current and the down current are preferably equal. That is, when the up signal UP from the phase frequency comparison circuit 11 is “L”, a constant current Icp is supplied to supply charge to the loop filter, and when the down signal DOWN is “H”, the charge accumulated in the loop filter is supplied. Can be extracted with a constant current Icp. As apparent from FIG. 6, the current mirror circuit composed of the PMOS transistors MP1 and MP2 provided on the power supply side and the current mirror circuit composed of the NMOS transistors MN1 and MN2 provided on the ground side, And the current flowing to the ground side are equal to the reference current Icp and are symmetric.

  The phase interpolator of the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications and changes may be made without departing from the spirit of the present invention. is there.

It is a figure which shows an example of a structure of the phase interpolator of this invention. It is a figure which shows an example of the circuit of the feedback 8 frequency divider 15 which comprises the phase interpolator 10 shown in FIG. FIG. 3 is a diagram illustrating an example of the operation of the feedback eighth divider 30 illustrated in FIG. 2. It is a figure which shows an example of the operation | movement of the clock divided by 8 output in arbitrary edge positions by the feedback 8 frequency divider. It is a figure which shows an example of operation | movement of the phase interpolator of this invention. It is a figure which shows an example of the charge pump circuit of the PLL circuit which comprises the phase interpolator of this invention. It is a figure which shows the conventional PLL circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Phase interpolator 11, 51 Phase frequency comparison circuit 12, 52 Charge pump circuit 13, 53 Loop filter 14, 54 Voltage control oscillation circuit 15, 16, 45 Frequency divider 17, 36, 37, 38, 39 Flip-flop 20, 50 PLL circuit 40, 41, 42, 43, 44 Inverter 31, 48 2-input AND
32 3-input AND
33, 34, 35 2-input ENOR
45 5-input AND
46, 47 4-input OR
MP1, MP2, MP3 PMOS transistors MN1, MN2, MN3, MN4 NMOS transistors

Claims (3)

A PLL circuit composed of a phase frequency comparison circuit, a charge pump circuit, a loop filter, a voltage control oscillation circuit and a feedback N divider, and an output signal obtained by dividing the oscillation output signal of the voltage control oscillation circuit by N An output N divider,
The feedback N divider selects any two of 2N clocks of the oscillation output signal output from the voltage controlled oscillation circuit to generate non-equal intervals, and supplies the phase frequency comparison circuit to the phase frequency comparison circuit. A phase interpolator that outputs as a feedback signal.   2. The phase interpolator according to claim 1, wherein the charge pump circuit is a charge pump circuit in which an up current for supplying electric charge to the loop filter and a down current for extracting electric charge from the loop filter are equal.   A reset circuit for resetting the output N divider, the reset circuit receiving the signal synchronized with the feedback signal from the feedback N divider after the PLL circuit is locked, and receiving the output N divider; 3. The phase interpolator according to claim 1, wherein the reset of the peripheral is released and the output signal is output. 4.

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