JP5827787B2 - PLL circuit - Google Patents

Description

  The present disclosure relates generally to electronic circuits, and more particularly to circuits that perform automatic phase control.

  A PLL (Phase Locked Loop) circuit receives a reference clock signal and outputs an oscillation signal whose phase is synchronized with the reference clock signal. If noise is mixed in the reference clock signal in a state where the phase is synchronized, there is a case where the PLL is unlocked (phase is out of synchronization) due to this noise. In order to prevent such a problem, the reference clock signal is generally passed through a noise filter circuit to remove noise and then input to the PLL phase comparison circuit.

  The noise filter circuit as described above has a low-pass filter characteristic. In general, for the purpose of removing noise, it is preferable to make the cutoff frequency of the filter as low as possible. However, if the cutoff frequency is too low at the input portion of the PLL circuit, the reference clock signal itself cannot pass through the filter as a detectable signal. Therefore, there has been a problem that a filter having appropriate characteristics must be designed in accordance with the use of the PLL circuit including the operating conditions such as the operating frequency.

Japanese Patent Laid-Open No. 4-101577 JP 2000-269947 A JP 2001-267914 A

  In view of the above, a PLL circuit that can automatically set the noise filter circuit appropriately is desired.

  The PLL circuit generates a second clock signal by filtering the first clock signal, and generates a control signal according to a phase comparison result between the second clock signal and the third clock signal. And a phase comparison circuit that performs at least a first delay circuit that causes a signal delay according to a value of the control signal, and an oscillation circuit that oscillates the third clock signal according to the signal delay, The circuit includes a second delay circuit having the same configuration as the first delay circuit and providing a signal delay according to the value of the control signal, and the first clock signal is filtered by the second delay circuit. Then, the second clock signal is generated.

  According to at least one embodiment of the present disclosure, the filter circuit includes a delay circuit that has the same configuration as the delay circuit in the oscillation circuit and that causes a signal delay according to the value of the control signal. As a result, filter processing according to the oscillation frequency is possible. In addition, by using a circuit having the same circuit configuration as the delay circuit of the oscillation loop and the delay circuit of the filter processing, the amount of change in the filter processing characteristic with respect to the amount of change in the oscillation period is made substantially constant regardless of the value of the oscillation frequency. Stable control can be realized. Even if the characteristics of the delay circuit of the oscillation loop fluctuate due to process fluctuations or temperature changes, the characteristics of the delay circuit for filter processing also fluctuate in the same way, so that stable control can be realized under various conditions. .

It is a figure which shows an example of a structure of a PLL circuit. It is a figure which shows an example of a structure of a voltage controlled oscillator. It is a figure which shows an example of a structure of a variable filter circuit. It is a figure which shows another example of a structure of a PLL circuit. It is a figure which shows an example of a structure of a V / I converter. It is a figure which shows an example of a structure of a current control oscillator. It is a figure which shows an example of a structure of a variable filter circuit. It is a figure which shows another example of a structure of a PLL circuit. It is a figure which shows an example of a structure of a voltage converter. It is a figure which shows another example of a structure of a PLL circuit. It is a figure which shows an example of a structure of a current converter. It is a figure which shows another example of a structure of a PLL circuit. It is a figure which shows another example of a structure of a PLL circuit. It is a figure which shows the modification of a structure of the PLL circuit of FIG. It is a figure which shows another modification of the structure of the PLL circuit of FIG. It is a figure which shows an example of the circuit structure of a phase comparator. FIG. 14 is a diagram showing still another modification of the configuration of the PLL circuit in FIG. 13. It is a figure which shows an example of a structure of a lock | rock detection circuit. It is a figure for demonstrating operation | movement of the lock | rock detection circuit of FIG. It is a figure which shows an example of a structure of the system incorporating a PLL circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram illustrating an example of a configuration of a PLL circuit. The PLL circuit shown in FIG. 1 includes a variable filter circuit 10, a phase comparator 11, a charge pump 12, a loop filter 13, and a voltage controlled oscillator (VCO) 14. The variable filter circuit 10 filters the reference clock signal RCLK to generate a clock signal after the filtering process. The phase comparator 11 compares the phase of the filtered clock signal and the output clock signal OCLK, and generates a signal indicating the phase comparison result. The charge pump 12 generates a voltage signal corresponding to the phase comparison result based on the signal indicating the phase comparison result from the phase comparator 11. The loop filter 13 performs a low-pass filter process on the voltage signal from the charge pump 12 and effectively integrates it, thereby removing unnecessary fine fluctuations and generating a control signal corresponding to the phase comparison result. The voltage controlled oscillator 14 is an oscillator that oscillates at an oscillation frequency corresponding to an input voltage value, and includes an oscillation loop 15 including at least one or a plurality of variable delay circuits 14-1, 14-2,. . The voltage controlled oscillator 14 includes at least a delay circuit (for example, 14-1) that causes a signal delay corresponding to the voltage value of the control signal from the loop filter 13, and oscillates the output clock signal OCLK according to the signal delay. Here, the variable delay circuits 14-1, 14-2,... Have the same configuration. For example, when the number of the plurality of variable delay circuits of the voltage controlled oscillator 14 is three and the oscillation frequency is 100 MHz, the delay of the variable delay circuit is 1/100 ÷ 6≈1.6 ns. Here, it is assumed that each variable delay circuit is an inverter type circuit that inverts the output logic value with respect to the input logic value, and the division divisor is set to 6, which is two times three.

  In the configuration of FIG. 1, the variable filter circuit 10 includes a variable delay circuit 16 that has the same configuration as the delay circuit (for example, 14-1) and provides a signal delay according to the voltage value of the control signal. The variable filter circuit 10 uses the variable delay circuit 16 to filter the reference clock signal RCLK, thereby generating a clock signal after filtering. As described above, the variable delay circuit 16 performs the filtering process according to the voltage of the control signal that controls the oscillation frequency of the output clock signal OCLK, thereby enabling the filtering process according to the oscillation frequency. Further, circuits having the same circuit configuration are used for the variable delay circuit of the oscillation loop and the variable delay circuit of the filter processing. Thus, stable control can be realized by setting the change amount of the filter processing characteristic with respect to the change amount of the oscillation period to be substantially constant regardless of the value of the oscillation frequency. In addition, even if the characteristics of the variable delay circuit in the oscillation loop fluctuate due to process fluctuations or temperature changes, the characteristics of the variable delay circuit for filter processing also fluctuate in the same way, so that stable control can be realized under various conditions. Can do.

  FIG. 2 is a diagram illustrating an example of the configuration of the voltage controlled oscillator 14. The voltage controlled oscillator 14 illustrated in FIG. 2 includes PMOS transistors 20 and 21, NMOS transistors 22 and 23, and a resistor 24. The voltage controlled oscillator 14 further includes PMOS transistors 25-1 to 25-3, NMOS transistors 26-1 to 26-3, inverters 27-1 to 27-3, and capacitive elements 28-1 to 28-3. The PMOS transistor 25-1, the NMOS transistor 26-1, the inverter 27-1, and the capacitive element 28-1 constitute a first variable delay circuit 14-1. The PMOS transistor 25-2, the NMOS transistor 26-2, the inverter 27-2, and the capacitive element 28-2 constitute a second variable delay circuit 14-2. The PMOS transistor 25-3, the NMOS transistor 26-3, the inverter 27-3, and the capacitive element 28-3 constitute a third variable delay circuit 14-3. The first to third variable delay circuits 14-1 to 14-3 are connected in cascade, and the output of the third variable delay circuit 14-3 is connected to the input of the first variable delay circuit 14-1 to oscillate. A loop 15 is formed.

  A control signal voltage from the loop filter 13 shown in FIG. 1 is applied to the gate of the NMOS transistor 22. As a result, a drain current having a current amount Id corresponding to the control signal voltage flows through the NMOS transistor 22. At this time, the same current amount Id also flows through the PMOS transistor 20 connected in series with the NMOS transistor 22. The PMOS transistors 20 and 21 form a current mirror circuit, and a current of the same current amount Id flows through the PMOS transistor 21 as well. Further, the same current Id flows through the NMOS transistor 23 connected in series with the PMOS transistor 21. The gate voltages of the PMOS transistors 20 and 21 that cause the current Id to flow are applied to the gates of the PMOS transistors 25-1 to 25-3 as the delay control signal P. In addition, the gate voltage of the NMOS transistor 23 through which the current of the current amount Id flows is applied to the gates of the NMOS transistors 26-1 to 26-3 as the delay control signal N. Accordingly, the resistance values (current amounts) of the PMOS transistors 25-1 to 25-3 and the NMOS transistors 26-1 to 26-3 change according to the control signal voltage from the loop filter 13 shown in FIG.

  When the control signal voltage from the loop filter 13 decreases and the resistance value increases (the current amount decreases), the charge / discharge speed of the capacitive elements 28-1 to 28-3 decreases, and the transition of the signal waveform becomes gentle. . As a result, the transition timing of the output signals of the inverters 27-1 to 27-3 is delayed. That is, the time from the start of transition of the input signal to the transition of the output signal when the output signal transitions in response to the transition of the input signal becomes longer. When the resistance values of the PMOS transistors 25-1 to 25-3 and the NMOS transistors 26-1 to 26-3 are increased in this way, each of the first to third variable delay circuits 14-1 to 14-3 is increased. Delay time becomes longer. That is, when the control signal voltage from the loop filter 13 decreases, the oscillation frequency of the oscillation loop 15 decreases.

  Conversely, when the control signal voltage from the loop filter 13 increases and the resistance value decreases (the amount of current increases), the charge / discharge speed of the capacitive elements 28-1 to 28-3 increases, and the signal waveform transitions sharply. Become. As a result, the transition timing of the output signals of the inverters 27-1 to 27-3 is advanced. That is, the time from the start of the input signal transition to the transition of the output signal when the output signal transitions in response to the transition of the input signal is shortened. When the resistance values of the PMOS transistors 25-1 to 25-3 and the NMOS transistors 26-1 to 26-3 are reduced in this way, each of the first to third variable delay circuits 14-1 to 14-3 is reduced. Delay time is shortened. That is, when the control signal voltage from the loop filter 13 increases, the oscillation frequency of the oscillation loop 15 increases.

  FIG. 3 is a diagram illustrating an example of the configuration of the variable filter circuit 10. The variable filter circuit 10 illustrated in FIG. 3 includes PMOS transistors 30 and 31, NMOS transistors 32 and 33, and a resistor 34. The variable filter circuit 10 further includes a PMOS transistor 35, an NMOS transistor 36, an inverter 37, and a capacitive element 38. The PMOS transistor 35, the NMOS transistor 36, the inverter 37, and the capacitive element 38 constitute the variable delay circuit 16 (see FIG. 1).

  A control signal voltage from the loop filter 13 shown in FIG. 1 is applied to the gate of the NMOS transistor 32. As a result, a drain current having a current amount Id corresponding to the control signal voltage flows through the NMOS transistor 32. At this time, the same current amount Id also flows through the PMOS transistor 30 connected in series with the NMOS transistor 32. The PMOS transistors 30 and 31 form a current mirror circuit, and the same current amount Id flows through the PMOS transistor 31 as well. Further, the same current Id flows through the NMOS transistor 33 connected in series with the PMOS transistor 31. The gate voltages of the PMOS transistors 30 and 31 that cause the current Id to flow are applied to the gate of the PMOS transistor 35 as the delay control signal P. Further, the gate voltage of the NMOS transistor 33 through which the current of the current amount Id flows is applied to the gate of the NMOS transistor 36 as the delay control signal N. Accordingly, the resistance values of the PMOS transistor 35 and the NMOS transistor 36 change according to the control signal voltage from the loop filter 13 shown in FIG.

  When the control signal voltage from the loop filter 13 decreases and the resistance value increases (current amount decreases), the charge / discharge speed of the capacitive element 38 decreases and the transition of the signal waveform becomes gentle. As a result, the transition timing of the output signal of the inverter 37 is delayed. That is, the time from the start of transition of the input signal to the transition of the output signal when the output signal transitions in response to the transition of the input signal becomes longer. At that time, when noise is included in the filter input signal, the minimum width and height of noise necessary for noise to appear in the filter output signal is increased. That is, when the control signal voltage from the loop filter 13 is lowered, larger noise can be removed.

  Conversely, when the control signal voltage from the loop filter 13 increases and the resistance value decreases (the amount of current increases), the charge / discharge speed of the capacitive element 38 increases and the signal waveform transition becomes steep. As a result, the transition timing of the output signal of the inverter 37 is advanced. That is, the time from the start of the input signal transition to the transition of the output signal when the output signal transitions in response to the transition of the input signal is shortened. At that time, when noise is included in the filter input signal, the minimum width and height of noise necessary for noise to appear in the filter output signal are reduced. That is, as the control signal voltage from the loop filter 13 increases, the noise that can be removed becomes smaller.

  FIG. 4 is a diagram illustrating another example of the configuration of the PLL circuit. 4, the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted. The PLL circuit shown in FIG. 4 is different from the PLL circuit shown in FIG. 1 in that a V / I converter 17 is provided and the oscillation frequency is current controlled instead of voltage controlled. Accordingly, a current control oscillator (ICO) 14 A is provided instead of the voltage control oscillator 14, and a variable filter circuit 10 A is provided instead of the variable filter circuit 10. The operation of the PLL circuit of FIG. 4 is the same as that of the PLL circuit of FIG. 1 except that current control is performed instead of voltage control.

  The V / I converter 17 converts the voltage value of the control signal from the loop filter 13 into a current value. The current control oscillator 14A is an oscillator that oscillates at an oscillation frequency corresponding to an input current value, and includes an oscillation loop 15A configured by at least one or a plurality of variable delay circuits 14A-1, 14A-2,. . The current control oscillator 14A includes at least a delay circuit (for example, 14-1) that causes a signal delay corresponding to the current value of the control signal from the V / I converter 17, and oscillates the output clock signal OCLK according to the signal delay. To do. The variable filter circuit 10A includes a variable delay circuit 16A that has the same configuration as the delay circuit (for example, 14-1) and that provides a signal delay corresponding to the current value of the control signal. The variable filter circuit 10A generates a filtered clock signal by filtering the reference clock signal RCLK with the variable delay circuit 16A.

  FIG. 5 is a diagram illustrating an example of the configuration of the V / I converter 17. The V / I converter 17 shown in FIG. 5 includes PMOS transistors 40 to 42, an NMOS transistor 43, and a resistor 44. A control signal voltage from the loop filter 13 shown in FIG. 4 is applied to the gate of the NMOS transistor 43. As a result, a drain current having a current amount Id corresponding to the control signal voltage flows through the NMOS transistor 43. At this time, the same current amount Id also flows through the PMOS transistor 40 connected in series with the NMOS transistor 43. The PMOS transistors 40, 41, and 42 form a current mirror circuit, and the same current amount Id flows through the PMOS transistors 41 and 42 as well. One of the currents flowing through the PMOS transistors 41 and 42 is supplied to the current control oscillator 14A, and the other is supplied to the variable filter circuit 10A.

  FIG. 6 is a diagram illustrating an example of the configuration of the current control oscillator 14A. In FIG. 6, the same components as those in FIG. 2 are referred to by the same numerals, and a description thereof will be omitted. The current control oscillator 14A illustrated in FIG. 6 includes a PMOS transistor 50 and NMOS transistors 51 and 52. The current control oscillator 14A further includes PMOS transistors 25-1 to 25-3, NMOS transistors 26-1 to 26-3, inverters 27-1 to 27-3, and capacitive elements 28-1 to 28-3. The first to third variable delay circuits 14A-1 to 14A-3 are connected in cascade, and the output of the third variable delay circuit 14A-3 is connected to the input of the first variable delay circuit 14A-1 to oscillate. A loop 15A is formed.

  A control signal current from the V / I converter 17 shown in FIG. The NMOS transistors 51 and 52 form a current mirror circuit, and the same amount of current flows through the NMOS transistor 52 as described above. Further, the same amount of current flows through the PMOS transistor 50 connected in series with the NMOS transistor 52. The gate voltage of the PMOS transistor 50 through which this amount of current flows is applied to the gates of the PMOS transistors 25-1 to 25-3. In addition, the gate voltage of the NMOS transistor 52 through which the current amount is supplied is applied to the gates of the NMOS transistors 26-1 to 26-3. Therefore, the resistance values (current amounts) of the PMOS transistors 25-1 to 25-3 and the NMOS transistors 26-1 to 26-3 change according to the control signal current from the V / I converter 17 shown in FIG. The oscillation frequency of the oscillation loop 15A changes.

  FIG. 7 is a diagram illustrating an example of the configuration of the variable filter circuit 10A. In FIG. 7, the same components as those of FIG. 3 are referred to by the same numerals, and a description thereof will be omitted. A variable filter circuit 10 </ b> A illustrated in FIG. 7 includes a PMOS transistor 60 and NMOS transistors 61 and 62. The variable filter circuit 10A further includes a PMOS transistor 35, an NMOS transistor 36, an inverter 37, and a capacitive element 38. The PMOS transistor 35, NMOS transistor 36, inverter 37, and capacitive element 38 constitute a variable delay circuit 16A (see FIG. 4).

  A control signal current from the V / I converter 17 shown in FIG. The NMOS transistors 61 and 62 form a current mirror circuit, and the same amount of current flows through the NMOS transistor 62 as described above. Further, the same amount of current flows through the PMOS transistor 60 connected in series with the NMOS transistor 62. The gate voltage of the PMOS transistor 60 that supplies this amount of current is applied to the gate of the PMOS transistor 35. In addition, the gate voltage of the NMOS transistor 62 that causes the current amount to flow is applied to the gate of the NMOS transistor 36. Therefore, the magnitude of noise that can be removed by the variable filter circuit 10A changes according to the control signal current from the V / I converter 17 shown in FIG.

  FIG. 8 is a diagram illustrating still another example of the configuration of the PLL circuit. In FIG. 8, the same components as those of FIG. 1 are referred to by the same numerals, and a description thereof will be omitted. The PLL circuit shown in FIG. 8 differs from the PLL circuit shown in FIG. 1 in that a voltage converter 18 that converts the voltage value of the control signal is provided. The variable delay circuit 16 of the variable filter circuit 10 operates according to the voltage value of the control signal after the voltage value is converted by the voltage converter 18. The voltage converter 18 adjusts the relationship between the voltage value before conversion and the voltage value after conversion in accordance with an external filter characteristic control signal such as a CPU.

  FIG. 9 is a diagram illustrating an example of the configuration of the voltage converter 18. The voltage converter 18 illustrated in FIG. 9 includes an operational amplifier 70, a plurality of resistor elements 71 connected in series, and a plurality of switch circuits 72. The operational amplifier 70 receives the input voltage to the voltage converter 18 at the non-inverting input terminal. The output of the operational amplifier 70 is connected to one end of the row of the plurality of resistance elements 71. The other end of the row of the plurality of resistance elements 71 is connected to the ground. The voltage at the intermediate point divided by the row of the plurality of resistance elements 71 is fed back to the inverting input terminal of the operational amplifier 70. The plurality of voltages generated by voltage division by the plurality of resistor elements 71 are selected by the conductive one of the plurality of switch circuits 72 and become the output voltage of the voltage converter 18. Which of the plurality of switch circuits 72 is made conductive is determined by an output voltage selection signal (filter characteristic control signal) supplied from the outside. Thereby, a voltage higher or lower than the output voltage (the output voltage of the loop filter 13) can be freely generated and supplied to the variable delay circuit 16.

  FIG. 10 is a diagram illustrating still another example of the configuration of the PLL circuit. 10, the same components as those in FIG. 4 are referred to by the same numerals, and a description thereof will be omitted. The PLL circuit shown in FIG. 10 differs from the PLL circuit shown in FIG. 4 in that a current converter 18A for converting the current value of the control signal is provided. The variable delay circuit 16A of the variable filter circuit 10A operates according to the current value of the control signal after the current value is converted by the current converter 18A. The current converter 18A adjusts the relationship between the current value before conversion and the current value after conversion in accordance with an external filter characteristic control signal such as a CPU.

  FIG. 11 is a diagram illustrating an example of the configuration of the current converter 18A. The current converter 18A illustrated in FIG. 11 includes a PMOS transistor 80, NMOS transistors 81 and 82, a plurality of PMOS transistors 83, and a plurality of switch circuits 84. A control signal current from the V / I converter 17 shown in FIG. The NMOS transistors 81 and 82 form a current mirror circuit, and the same amount of current flows through the NMOS transistor 82 as described above. Further, the same amount of current flows through the PMOS transistor 80 connected in series to the NMOS transistor 82. The gate voltage of the PMOS transistor 80 that flows this amount of current is applied to the gates of the plurality of PMOS transistors 83, forming a current mirror circuit. A plurality of currents generated by the plurality of PMOS transistors 83 are sent out as output currents of the current converter 18 through one or more conductive switch circuits of the plurality of switch circuits 84. The number of switch circuits 72 to be turned on is determined by an output current selection signal (filter characteristic control signal) supplied from the outside. Thereby, a current larger than the output current (the output current of the V / I converter 17) can be freely generated and supplied to the variable delay circuit 16A. The gate widths of the NMOS transistors 81 and 82 may be different, and the drain current flowing through the NMOS transistor 82 may be 1 / n (n: natural number) of the drain current flowing through the NMOS transistor 81. In this case, a current smaller than or larger than the output current (the output current of the V / I converter 17) can be freely generated and supplied to the variable delay circuit 16A.

  FIG. 12 is a diagram illustrating still another example of the configuration of the PLL circuit. 12, the same components as those in FIG. 8 are referred to by the same numerals, and a description thereof will be omitted. The PLL circuit shown in FIG. 12 is different from the PLL circuit shown in FIG. 8 in that an N divider 90, an M divider 91, and a decoder 92 are additionally provided. The N divider 90 divides the filtered clock signal output from the variable filter circuit 10 by the division ratio N corresponding to the division setting signal. The M frequency divider 91 divides the output clock signal OCLK output from the voltage controlled oscillator 14 by the frequency division ratio M according to the frequency division setting signal. The clock signals after frequency division by these frequency dividers 90 and 91 are input to the phase comparator 11 as signals for phase comparison. The decoder 92 decodes the frequency division setting signal that specifies N frequency division and the frequency division setting signal that specifies M frequency division, and generates a filter characteristic control signal. The voltage converter 18 adjusts the relationship between the voltage value before conversion and the voltage value after conversion according to the filter characteristic control signal. In the configuration of FIG. 12, two frequency dividers, the N frequency divider 90 and the M frequency divider 91, are provided. However, only one of them may be provided.

  It is assumed that appropriate noise removal is realized in the configuration of FIG. 1 in which the voltage converter 18 is not provided. Consider the case where two frequency dividers, an N frequency divider 90 and an M frequency divider 91, are provided under the same conditions as shown in FIG. In this case, when the phase is synchronized, 1 / N of the reference clock signal RCLK is equal to 1 / M of the output clock signal OCLK, so that the frequency of the reference clock signal RCLK is N / M of the output frequency. . Since the control voltage of the variable delay circuit 16 is an appropriate value in a state where the frequency divider is not provided (that is, N = M = 1), in the case of the configuration shown in FIG. The control voltage applied to 16 may be N / M times the appropriate value. That is, the decoder 92 may generate a signal that causes the voltage converter 18 to generate a voltage N / M times the input voltage.

  FIG. 13 is a diagram illustrating still another example of the configuration of the PLL circuit. In FIG. 13, the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted. The PLL circuit shown in FIG. 13 is different from the PLL circuit shown in FIG. 1 in that a switch circuit 19 is provided. When connected to the lower node in the figure, the switch circuit 19 selects the first path for supplying the reference clock signal RCLK to the phase comparator 11 as a phase comparison target signal without passing through the variable filter circuit 10. Further, when connected to the upper node in the figure, the switch circuit 19 supplies a clock signal after filtering obtained from the reference clock signal RCLK via the variable filter circuit 10 to the phase comparator 11 as a signal for phase comparison. The second route to be selected is selected. The switch circuit 19 is configured to be able to select and switch between one of the first path and the second path.

  The switch circuit 19 may perform a switching operation according to a filter bypass control signal from the outside such as a CPU. For example, in the initial operation (before locking) until the PLL circuit establishes phase synchronization, the reference clock signal RCLK is directly supplied to the phase comparator 11, and after the PLL circuit establishes phase synchronization (after locking). May supply the filtered clock signal to the phase comparator 11. If the variable filter circuit 10 is set in an initial state such that even a pulse signal of a clock necessary for establishing phase synchronization cannot pass through the variable filter circuit 10 in the initial operation for locking the phase, the PLL circuit Cannot execute the desired operation at all. As described above, when the reference clock signal RCLK is directly supplied to the phase comparator 11 during the initial operation for locking the phase, the phase synchronization is surely performed regardless of the initial state of the variable filter circuit 10. Can be established. In addition, after the phase synchronization is established, the filtered clock signal is supplied to the phase comparator 11 so that the influence of noise can be reliably removed.

  FIG. 14 is a diagram showing a modification of the configuration of the PLL circuit of FIG. 14, the same components as those in FIG. 13 are referred to by the same numerals, and a description thereof will be omitted. The PLL circuit shown in FIG. 14 is different from the PLL circuit shown in FIG. 13 in that a counter 100 is provided. The counter 100 counts the number of pulses of the reference clock signal RCLK, and asserts an output when the count value reaches a predetermined value. The switch circuit 19 switches from the first path to the second path in response to the assertion of the output of the counter 100. What is necessary is just to set the number of pulses required for the operation | movement (phase lock operation | movement) which establishes phase synchronization to complete | finish as said predetermined value.

  FIG. 15 is a diagram showing another modification of the configuration of the PLL circuit of FIG. In FIG. 15, the same components as those of FIG. 13 are referred to by the same numerals, and a description thereof will be omitted. The PLL circuit shown in FIG. 15 is different from the PLL circuit shown in FIG. 13 in that a lock detection circuit 101 is provided. The lock detection circuit 101 asserts an output when it detects a state in which the phases are synchronized based on the control signal output from the phase comparator 11. In response to the assertion of the output of the lock detection circuit 101, the switch circuit 19 switches from the first path to the second path.

  FIG. 16 is a diagram illustrating an example of a circuit configuration of the phase comparator 11. The phase comparator 11 of FIG. 16 includes NAND circuits 111 to 118, inverters 119 to 121, and an AND circuit 122. The phase comparator 11 waits for an input change while the frequency up signal output, which is the output of the NAND circuit 118, is HIGH, and the frequency down signal output, which is the output of the AND circuit 122, is LOW. HIGH of the frequency up signal output and LOW of the frequency down signal output are negated states of the respective signals. The frequency up signal output is applied to the gate of the PMOS transistor of the next stage charge pump 12, and the frequency down signal output is applied to the gate of the NMOS transistor of the next stage charge pump 12. These PMOS transistor and NMOS transistor charge / discharge the capacitive element of the charge pump 12.

  In the above standby state, for example, when the reference clock signal changes from HIGH to LOW before the comparison clock signal, the output of the NAND circuit 111 changes to HIGH, and the frequency up signal output of the NAND circuit 118 changes to LOW. That is, the frequency up signal output is asserted (LOW). Thereafter, when the comparison clock signal changes from HIGH to LOW, the output of the NAND circuit 116 changes to HIGH, and the frequency down signal output of the AND circuit 122 changes to HIGH. That is, the frequency down signal output is asserted (HIGH). Further, due to the change of the output of the NAND circuit 116 to HIGH, all the inputs of the NAND circuit 117 become HIGH, and the output of the NAND circuit 117 changes from HIGH to LOW. As a result, the frequency up signal output and the frequency down signal output change simultaneously to HIGH and LOW, respectively, and the phase comparator 11 is reset. Thereafter, when the reference clock signal and the comparison clock signal return to HIGH, the phase comparator 11 returns to the standby state.

  When the reference clock signal and the comparison clock signal change from HIGH to LOW at the same time in the standby state, a change in the frequency up signal output to LOW and a change in the frequency down signal output to HIGH occur simultaneously. Furthermore, immediately after that, the change of the frequency up signal output to HIGH and the change of the frequency down signal output to LOW occur simultaneously with the reset of the phase comparator 11.

  Thus, in a state where the clocks are phase-synchronized, the asserted state of the frequency up signal output and the asserted state of the frequency down signal output occur in the same period. In a state where there is a phase difference between the clocks, the asserted state of one signal output is generated longer than the asserted state of the other signal for a period equal to the phase difference. For the phase comparator 11 that outputs such a phase comparison result signal, an XOR circuit (exclusive OR circuit) can be used for the lock detection circuit 101 shown in FIG. In a state where the clock phase is synchronized, the logic value of the frequency up signal output and the logic value of the frequency down signal output are always opposite, so the output of the XOR circuit is fixed to HIGH. Further, in a state where there is a phase difference between the clocks, both signal outputs have the same logical value only during a period equal to the phase difference, so that the output of the XOR circuit becomes a period LOW equal to the phase difference. When the lock detection circuit 101 detects that the output of the XOR circuit is HIGH, the lock detection circuit 101 may switch the switch circuit 19 from the first path to the second path.

  FIG. 17 is a diagram showing still another modification of the configuration of the PLL circuit of FIG. In FIG. 17, the same components as those of FIG. 13 are referred to by the same numerals, and a description thereof will be omitted. The PLL circuit shown in FIG. 17 is different from the PLL circuit shown in FIG. 13 in that a lock detection circuit 102 is provided. The lock detection circuit 102 asserts an output when detecting a phase-synchronized state based on a control signal output from the loop filter 13 according to the phase comparison result of the phase comparator 11. In response to the assertion of the output of the lock detection circuit 102, the switch circuit 19 switches from the first path to the second path.

  FIG. 18 is a diagram illustrating an example of the configuration of the lock detection circuit 102. The lock detection circuit 102 illustrated in FIG. 18 includes a capacitive element 131, a resistive element 132, and a comparator 133. Capacitance element 131 and resistance element 132 constitute a differentiation circuit, and generate a voltage corresponding to differentiation of the input VCO control voltage waveform. The comparator 133 compares the differential voltage with the reference voltage, and sets the output to HIGH when the differential voltage becomes lower than the reference voltage.

  FIG. 19 is a diagram for explaining the operation of the lock detection circuit 102 of FIG. In FIG. 19, the VCO control voltage applied from the loop filter 13 to the voltage controlled oscillator 14 has a waveform such as a voltage waveform 140, for example. That is, when the operation of the PLL circuit starts, the VCO control voltage is adjusted according to the phase comparison result by the phase comparator 11 based on feedback control. When a VCO control voltage that synchronizes the phase between clocks is obtained (that is, when a lock state is established), the VCO control voltage subsequently changes at a substantially constant value.

  The voltage waveform 141 is a waveform obtained by differentiating the voltage waveform 140 and is a voltage waveform input to the inverting input terminal of the comparator 133 illustrated in FIG. A voltage waveform 142 is a reference voltage and is a voltage waveform input to the non-inverting input terminal of the comparator 133. The comparator 133 compares the differential voltage with the reference voltage and generates an output voltage indicated as a voltage waveform 143 according to the magnitude relationship. The output voltage of the comparator 133 is LOW for a while from the operation start timing T0 of the PLL circuit, and becomes HIGH at the timing T1 when the phase synchronization is established. The lock detection circuit 102 may control the switch circuit 19 based on the output of the comparator 133, and switch the switch circuit 19 from the first path to the second path when the output of the comparator 133 becomes HIGH.

  FIG. 20 is a diagram illustrating an example of the configuration of a system incorporating a PLL circuit. For example, the system 150 configured as a single chip as a semiconductor device includes a CPU 151, a flash memory 152, a RAM 153, a clock control circuit 154, various resources 156, and a bus 157. The CPU 151, flash memory 152, RAM 153, clock control circuit 154, and various resources 156 exchange signals with each other via the bus 157. The clock control circuit 154 includes the PLL circuit 155 shown in FIG. 8 or FIG. 9, for example, and generates an output clock signal according to the reference clock signal. The output clock signal generated by the clock control circuit 154 is supplied to each unit in the system 150 to realize the operation synchronized with the clock of the system. The PLL circuit 155 includes a conversion circuit 18 or 18A (see FIGS. 8 and 9) that converts the value of the control signal in accordance with a signal from the CPU 151.

  The PLL circuit 155 of the clock control circuit 154 is a frequency divider that divides at least one of the reference clock signal and the output clock signal by a frequency division ratio according to the frequency division setting signal from the CPU 151 (for example, N frequency division in FIG. 12). And 90 or M divider 91). In this case, the conversion circuit 18 converts the value of the control signal in accordance with the frequency division setting signal. The PLL circuit 155 may include the switch circuit 19 (see FIGS. 13, 14, 15, and 17).

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

The present application includes the following contents.
(Appendix 1)
A filter circuit for filtering the first clock signal to generate a second clock signal;
A phase comparison circuit for generating a control signal according to a phase comparison result between the second clock signal and the third clock signal;
Including at least a first delay circuit that causes a signal delay according to a value of the control signal, and an oscillation circuit that oscillates the third clock signal according to the signal delay,
The filter circuit includes a second delay circuit having the same configuration as the first delay circuit and providing a signal delay according to the value of the control signal, and the first delay signal is generated by the second delay circuit. A PLL circuit that performs filtering to generate the second clock signal.
(Appendix 2)
The PLL circuit according to claim 1, further comprising a conversion circuit that converts a value of the control signal, wherein the second delay circuit operates in accordance with the value of the control signal after the conversion of the value.
(Appendix 3)
A frequency divider that divides at least one of the second clock signal and the third clock signal by a frequency division ratio according to a frequency division setting signal; and a clock signal after frequency division by the frequency divider 3. The PLL circuit according to claim 2, wherein the phase comparison circuit inputs a signal as a phase comparison target signal, and the conversion circuit converts the value of the control signal in accordance with the frequency division setting signal.
(Appendix 4)
A first path for supplying the first clock signal to the phase comparison circuit as a signal for phase comparison without passing through the filter circuit; and the first path obtained from the first clock signal through the filter circuit. 4. The switch circuit according to claim 1, further comprising a switch circuit capable of selecting and switching a second path for supplying the second clock signal to the phase comparison circuit as a phase comparison target signal. PLL circuit.
(Appendix 5)
The counter further includes a counter that counts the number of pulses of the first clock signal and asserts an output when the count value reaches a predetermined value. 5. The PLL circuit according to appendix 4, wherein the PLL circuit is switched to a second path.
(Appendix 6)
A detection circuit that asserts an output when detecting a phase synchronization between the second clock signal and the third clock signal based on the control signal output from the phase comparison circuit; The PLL circuit according to appendix 4, wherein the switch circuit switches from the first path to the second path in response to assertion of an output.
(Appendix 7)
A clock control circuit for generating an output clock signal according to a reference clock signal;
A processing unit, and the clock control circuit includes:
A filter circuit that filters the reference clock signal to generate a first clock signal;
A phase comparison circuit that generates a control signal according to a phase comparison result between the first clock signal and the output clock signal;
An oscillation circuit that oscillates the output clock signal according to the signal delay, including at least a first delay circuit that causes a signal delay according to the value of the control signal;
A conversion circuit that converts the value of the control signal in accordance with a signal from the processing unit,
The filter circuit includes a second delay circuit having the same configuration as that of the first delay circuit and causing a signal delay corresponding to the value of the control signal after the value is converted, and the second delay circuit A system that filters the reference clock signal to generate the first clock signal.
(Appendix 8)
The clock control circuit further includes a frequency divider that divides at least one of the first clock signal and the output clock signal by a frequency division ratio according to a frequency division setting signal from the processing unit. The clock signal after frequency division by the comparator is input to the phase comparison circuit as a signal for phase comparison, and the conversion circuit converts the value of the control signal in accordance with the frequency division setting signal. The system described.
(Appendix 9)
The clock control circuit includes a first path for supplying the reference clock signal to the phase comparison circuit as a signal to be compared without passing through the filter circuit, and the first clock signal through the filter circuit. Additional switch 7 or 8 further comprising a switch circuit capable of selecting and switching a second path for supplying the obtained second clock signal to the phase comparison circuit as a signal for phase comparison. System.
(Appendix 10)
The clock control circuit further includes a counter that counts the number of pulses of the reference clock signal and asserts an output when the count value reaches a predetermined value, and the switch circuit responds to assertion of the output of the counter. The system according to appendix 9, wherein the system switches from a route to the second route.
(Appendix 11)
A detection circuit that asserts an output when detecting a phase synchronization between the first clock signal and the output clock signal based on the control signal output from the phase comparison circuit; The system according to claim 9, wherein the switch circuit switches from the first path to the second path in response to assertion.
(Appendix 12)
Filtering the first clock signal to generate a second clock signal;
Generating a control signal according to a phase comparison result between the second clock signal and the third clock signal;
Each step of oscillating the third clock signal according to the signal delay using a first delay circuit that causes a signal delay according to the value of the control signal;
The filtering process uses a second delay circuit that has the same configuration as the first delay circuit and provides a signal delay according to the value of the control signal, and the first delay signal is generated by the second delay circuit. A noise removal method for a PLL circuit, wherein the second clock signal is generated by filtering the signal.

DESCRIPTION OF SYMBOLS 10 Variable filter circuit 11 Phase comparator 12 Charge pump 13 Loop filter 14 Voltage controlled oscillator

Claims (4)

A filter circuit for filtering the first clock signal to generate a second clock signal;
A switch circuit that receives the first clock signal and the second clock signal and selectively outputs the first clock signal or the second clock signal based on a switch control signal;
A phase comparator circuit for generating a control voltage No. signal according to the phase comparison result between the third said of the selectively output clock signal from the switching circuit first clock signal or said second clock signal,
A detection circuit that compares the differential signal of the control voltage signal with a reference voltage signal and generates the switch control signal based on the comparison;
Including at least a first delay circuit that causes a signal delay according to a value of the control voltage signal , and an oscillation circuit that oscillates the third clock signal according to the signal delay,
The filter circuit includes a second delay circuit having the same configuration as the first delay circuit and providing a signal delay corresponding to the value of the control voltage signal , and the first clock signal is generated by the second delay circuit. To generate the second clock signal. Further comprising a conversion circuit for converting the value of the control voltage signal, according to claim 1, wherein said second delay circuit in accordance with the value of the control voltage signal after converting the value is characterized by operating PLL circuit. A frequency divider that divides at least one of the second clock signal and the third clock signal by a frequency division ratio according to a frequency division setting signal; and a clock signal after frequency division by the frequency divider 3. The PLL circuit according to claim 2, wherein the phase comparison circuit inputs a signal to be compared with the phase comparison circuit, and the conversion circuit converts the value of the control voltage signal in accordance with the frequency division setting signal.   The switch circuit selectively outputs the first clock signal according to a first path for supplying the first clock signal as a phase comparison target signal to the phase comparison circuit, and outputs the first clock signal from the first clock signal. The second clock signal is selectively output according to a second path for supplying the second clock signal obtained through the filter circuit as a phase comparison target signal to the phase comparison circuit. The PLL circuit according to claim 1.

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