JP2008227168A - Method for arranging via, and method for manufacturing wiring substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a factor which deteriorate substrate characteristics by securing a pattern width which becomes broad enough in a power supply system pattern. <P>SOLUTION: When in the process of arranging a via 4, a clearance 5 around the via 4 is divided into a clearance region continued by a predetermined number (6), the via 4 is arranged so that a power supply system pattern 6 of the width for one pitch is arranged continuously between the adjacent clearance regions. Moreover, the via 4 is arranged so that a signal wiring 3 does not cross the clearance region and is arranged in the region where the power supply system pattern 6 is arranged. Further, the via 4 is arranged in the center surrounded by a terminal 2 in a predetermined position in the terminal arrangement region where the terminal 2 of the semiconductor device is arranged with equal pitch in X direction and Y direction. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for arranging vias provided in a power supply system pattern facing a signal wiring layer and a dielectric layer in a wiring board, and a method for manufacturing a wiring board, and in particular, a via for optimizing the arrangement of vias. The present invention relates to a method for arranging a wiring board and a method for manufacturing a wiring board.

  2. Description of the Related Art In recent years, with increasing size and increasing the number of terminals due to functional integration and the like, an increasing number of semiconductor device terminals are arranged in an array. In many cases, the layout of the terminals of the semiconductor device is already determined before designing the wiring board for mounting the semiconductor device. Therefore, in designing the wiring board, the terminals are arranged in an array regardless of the terminal arrangement of the semiconductor device. However, since wiring from an arbitrary terminal is required, wiring through vias is also necessary.

  When two semiconductor devices having terminal arrangements regularly arranged in an array are mounted on a wiring board, and electrical connection between terminals of both semiconductor devices is considered, electrical connection is made using only signal wiring on the substrate surface layer. In this case, the terminal of one semiconductor device is in contact with the signal wiring on the substrate surface layer side, and the terminal of the other semiconductor device is in contact with the signal wiring on the substrate surface layer side in another position, so that the terminals of both semiconductor devices are connected. Electrically connected. In addition, in the case of electrical connection using the signal wiring of another layer (for example, inner layer) in the wiring board, the terminal of one semiconductor device is in contact with the signal wiring on the substrate surface layer side, and the signal wiring on the substrate surface layer side Is in contact with the via, the via is in contact with the signal wiring in the other layer, the signal wiring in the other layer is in contact with the via in another position, and the via in the other position is in the signal wiring on the substrate surface layer side in another position. And the signal wiring on the substrate surface side in another position is in contact with the terminal of the other semiconductor device, whereby the terminals of both semiconductor devices are electrically connected.

  In the wiring board using vias, as shown in FIG. 10, the via 104 electrically connected to the terminal 102 of the semiconductor device 101 through the signal wiring 103 on the substrate surface layer side is connected to the power supply system pattern 106 (GND or power supply). A clearance 105 is provided around the via 104 so as not to be connected to the solid layer. FIG. 10B is an image of the case where the power supply system pattern 106 is disposed on the inner layer of the substrate. However, the power supply pattern is disposed around the signal wiring 103 disposed on the surface of the wiring substrate 108 on the semiconductor device 101 side. Even when a system pattern (not shown) is spread, a power system pattern (not shown) is arranged in a state where it is hollowed out by a clearance (not shown) around the signal wiring 103 and the via 104.

  Here, the power supply system pattern 106 serves as a reference plane pattern for the signal wiring 103 (see FIG. 11). That is, in the portion where the signal wiring 103 is disposed on the power supply system pattern 106, when the signal current IS flows through the signal wiring 103, the return current IR flows in the direction opposite to the signal current IS in the power supply system pattern 106. The signal current IS generates an electromagnetic field in a direction perpendicular to the traveling direction. The signal current IS is also coupled to an electromagnetic field in which a return current IR is generated under the signal wiring 103, and the impedance is low under the signal wiring 103. Device malfunction can be suppressed.

Japanese Patent Laid-Open No. 10-303564

  However, in the conventional via arrangement method, the via is often easily arranged near the terminal of the semiconductor device, and there are some problems.

  The first problem is that the via clearances associated with the signal lines may be connected. In other words, with the narrowing of the pitch of the terminals of the semiconductor device, there is a situation where there is no power supply system pattern as a return current path, and in extreme cases, even between the terminals of the semiconductor device, the signal line It is becoming impossible to place such vias. In such a case, vias related to the signal lines are arranged away from the terminals of the semiconductor device, but vias related to the signal lines are concentrated to connect the clearances of the vias related to the signal lines. May end up. For example, when vias are arranged close to each other (with a narrow pitch), the clearances around the vias are closer together than before, and the power supply system pattern that remains between the clearances becomes gradually thinner. However, since the sharp corner pattern of the power supply system pattern is rounded at this time, the power supply system pattern 106 itself that should exist between the clearances 105 as shown in FIG. It can happen to disappear. Further, as shown in FIG. 12B, the clearances 105 may be connected even when the diameter of the via 104 itself is large according to the amount of current and the amount of heat generation. Also, as shown in FIG. 12C, the clearances 105 may be connected even when the clearance diameter of the via 104 is large according to the amount of current and the amount of heat generation. Further, as shown in FIGS. 12A to 12B, there are many places where the clearances 105 are connected to each other, and a direct return current path in a region where the power supply system pattern 106 is not present, that is, the direction in which the signal wiring 103 extends. There will be a wide area where there is no.

  The second problem is that the power supply system pattern does not serve as an ideal power supply path having a low impedance or a signal return current path. The cause of this problem is that the clearance between adjacent vias is close, making the power supply pattern narrower than the ideal power supply path or return current path, or in the worst case the clearances between This is because the power supply path or the return current path itself is lost. The power supply system pattern serves as a reference plane pattern for the signal. For example, if the power supply system pattern 106 between the clearances 105 exists with a sufficient width as shown in FIG. Although the power supply system impedance is low even if it is net-like, if the power supply system pattern 106 between the clearances 105 is narrowed as shown in FIG. 13B, the power supply system impedance of the narrow portion becomes high, and the ideal power supply path Or it is no longer a return current path. If the clearances 105 are not connected as shown in FIG. 11, the return current path IR with respect to the signal current path IS in the signal wiring 103 passes through the power supply system pattern 106 directly below the signal wiring 103. When the clearances 105 are connected as in (C), the return current path IR with respect to the signal current path IS bypasses. When the impedance of the power supply pattern 106 increases or the return current path IR with respect to the signal current path IS is detoured, electromagnetic radiation noise is generated from the wiring board, and signal disturbance, delay, etc. are particularly noticeable in high-speed operation. As a result, the semiconductor device may malfunction. Therefore, it is necessary to consider the layout of the vias that are the basis of the cause so as to avoid such a situation as much as possible in the design of the wiring board.

  The third problem is that when a semiconductor device having terminals arranged in an array shape, particularly in a circular shape, is mounted on a wiring board, a power supply system pattern existing directly under the semiconductor device and a semiconductor device originally prepared In the worst case, the power system pattern in the region directly under the semiconductor device and the power system pattern in the outer region Is completely cut off. The cause of this problem is that there are terminals that cannot be directly wired on the surface where the semiconductor device is mounted, and the number of signal wirings that can be passed between the terminals has been limited due to the narrow pitch of the semiconductor devices. For this reason, it is indispensable to use the vias 104 to connect the terminals 102 on the inner peripheral side of the semiconductor device, and more vias 104 are arranged in an array at a terminal pitch. Due to the connection, a frame-shaped region where the power supply system patterns 106a and 106b do not exist is formed, and as a result, the power supply system patterns 106a and 106b are divided (see FIG. 14). In a semiconductor device having a group of terminals arranged in an array, the number of wirings that can be passed between the terminals and the number of vias that can be arranged are reduced because the terminals are narrowed in pitch. Normally, when a via is required, as shown in FIG. 15, one via 104 is arranged in the center surrounded by the terminals 102 of the semiconductor device, and the array arrangement is the same as that of the terminals 102. If the number of wirings between the terminals is limited to one, particularly in the case of a semiconductor device having terminals in which a circular shape of three or more rounds is also arranged, usually from the terminal on the inner peripheral side from the third outer periphery. Wiring connection using vias is essential for this wiring. At this time, since the vias placed on the inner peripheral side are placed in the vicinity of the terminals of the semiconductor device in an array with a terminal pitch, the clearances between adjacent vias are connected in a wide range, and the clearance between them is accordingly increased. Thus, a frame-like region in which the power supply system pattern that should have been prepared does not exist near the terminal of the semiconductor device.

  As a means for avoiding the above clearances from being connected to each other, through holes (vias) for signal wiring connection are arranged in a staggered manner with respect to connection pads (terminals) of an array connection type IC (semiconductor device). Is disclosed (see Patent Document 1). In Patent Document 1, an example of wiring between two terminals is shown. However, in a situation where the number of wirings that can be passed between terminals is limited as the pitch of the terminals of the semiconductor device is reduced. The staggered arrangement of vias is not the fundamental solution.

  For example, as shown in FIG. 16, when the number of turns of the terminal 102 of the semiconductor device is three (three rows), if the number of signal wirings 103 that can be arranged between the terminals 102 is limited to one, the via 104 One is arranged in the center surrounded by the terminals 102 and is continuously arranged in the X direction, and the clearance 105 is continuously connected in the X direction. Therefore, the arrangement of the vias 104 is staggered as shown in FIG. In other words, since the vias 104 are not continuously arranged, it is avoided that the clearances 105 are connected to each other. However, this means is a case where the terminal arrangement of the semiconductor device can be changed according to the convenience when designing the board. Since the terminal arrangement of the semiconductor device is often determined before the board design, the terminal In general, the arrangement is not flexible and lacks usefulness.

  Further, when the power supply system pattern between the clearances becomes thin or the power supply system pattern is cut off due to the rounding of the sharp pattern, the power supply system reinforcement region (ST) with respect to the power supply system reinforcement unprocessed region (NR) in FIG. It is also conceivable to add the bridging pattern 109 to the power supply system pattern 106 as described above. However, since such a bridging pattern 109 can only be entered in a range that conforms to the board design rules, there is a limit to the power supply enhancement, and every time such processing takes board design man-hours, it is an appropriate means. Absent.

  A first problem of the present invention is to secure a sufficiently wide pattern width in a power supply system pattern and suppress factors that deteriorate substrate characteristics.

  A second problem of the present invention is to realize signal wiring from arbitrary terminals arranged in an array without depending on the terminal arrangement of the semiconductor device.

  According to a first aspect of the present invention, there is provided a method for arranging vias provided in a power supply system pattern facing a signal wiring layer and a dielectric layer, and in the step of arranging the vias, The clearance is divided into clearance areas that are continuously arranged in a predetermined number, and the vias are arranged so that the power supply system pattern having a predetermined width is continuously arranged between the adjacent clearance areas. To do.

  In the via arrangement method of the present invention, the signal wiring arranged in the signal wiring layer does not cross the clearance region and the power supply system pattern is arranged in the step of arranging the via. It is preferable to arrange the vias so as to be arranged in the region.

  In the via arrangement method of the present invention, at the time of the step of arranging the via, at least a terminal of the semiconductor device is arranged on the terminal at a predetermined position in a terminal arrangement region in which the terminals are arranged at equal pitches in the X direction and the Y direction. It is preferable to arrange the via in the center of the circle.

  In the via arrangement method of the present invention, in the step of arranging the vias, an array of three or more vias in the X direction and m (m ≧ 1) in the Y direction by the automatic arrangement of the vias. When the clearances are connected in the X direction, the vias are divided into three units in the X direction and m units in the Y direction. It is preferable that the vias are arranged so that two are arranged in the X direction and m + 1 in the Y direction, and the continuity is interrupted in the X direction.

  In the via arrangement method of the present invention, in the step of arranging the vias, the vias are arranged in an array of n (n ≧ 2) in the Y direction by the automatic arrangement of the vias, and the clearance If they are connected to each other in the Y direction, at most, the unit is divided into units with a limit of 3 consecutive vias in the Y direction, and one of the units is moved in the Y direction, and is continuous in the Y direction. It is preferable to arrange the vias so that the characteristics are interrupted.

  In the via arrangement method of the present invention, when the terminals of the semiconductor device are arranged in the order of the signal system terminal, the power supply system terminal, and the signal system terminal in the X direction, the power supply system terminal in the step of arranging the via Is electrically connected to the power supply system pattern via a power supply system wiring and a power supply system via, and the power supply system via is arranged in a region where the power supply system pattern is arranged between the clearances. It is preferable to arrange vias.

  In the via arrangement method of the present invention, when the terminals of the semiconductor device are arranged in the order of the signal system terminal, the dummy terminal, and the signal system terminal in the X direction, the dummy terminal is inserted into the via in the step of arranging the via. Preferably, the vias are arranged so that no other vias are arranged in a region where the power supply system pattern between the signal wiring layer and the power supply system plane is not electrically connected and between the clearances.

  In the via arrangement method of the present invention, during the step of arranging the via, the via is electrically connected to the via via the first signal wiring of the signal wiring layer among the outermost terminals of the semiconductor device. Preferably, the vias are arranged so that the first terminal and the second terminal electrically connected to the second signal wiring of the signal wiring layer drawn out from the inner periphery side are alternately arranged.

  According to a second aspect of the present invention, the method for manufacturing a wiring board includes a step of forming vias according to the via arrangement method.

  According to the present invention, it is possible to optimize the arrangement of wiring and vias from arbitrary terminals arranged in an array without depending on the terminal arrangement of the semiconductor device. In addition, by deliberately moving a part of the vias required for wiring according to a predetermined rule, a sufficiently wide pattern width is secured in the power supply system pattern, and the return current is bypassed for the signal current as the reference plane It is possible to simultaneously realize the minimization of the path and the reduction of the impedance of the power supply system pattern.

(Embodiment 1)
The via arrangement method according to the first embodiment of the present invention will be described in comparison with a comparative example. FIG. 1 is a partial plan view schematically showing an example of a wiring pattern of a wiring board formed by a via arrangement method according to Embodiment 1 of the present invention. FIG. 2 is a partial plan view schematically showing an example of a wiring pattern of a wiring board formed by the via arrangement method according to Comparative Example 1.

  Here, for the sake of convenience, a certain fixed direction in which the terminal arrays are arranged is defined as the X direction, and a direction orthogonal to the defined direction is defined as the Y direction. Further, the wiring shown in each drawing is an example in which it is confirmed that wiring from the terminal of the semiconductor device is possible with respect to the via arrangement method. Here, only the minimum necessary part when a semiconductor device having terminals arranged in an array is mounted on a wiring board is described. Furthermore, depending on the terminal layout of the semiconductor device and the wiring policy in the board design, the vias arranged closest to the terminals also change, so the via arrangement described here does not necessarily represent all, so the following This embodiment is merely an example when placing vias.

  As shown in FIG. 10, the wiring board that is the target of the via placement method is the wiring board (108) for surface mounting the semiconductor device (101). The wiring board (108) has a signal wiring (103) made of a conductor via a dielectric layer (107) on a power supply system pattern (106) made of a conductor, and is connected to the signal wiring (103) and also has a power supply. There is a via (104) that penetrates the system pattern (106), and a clearance (105) is provided around the via (104) so that the power system pattern (106) and the via (104) are not connected. . In the first embodiment, a plurality of vias 4 are arranged in the area of the clearance 5 as shown in FIG. One via 4 is arranged at a predetermined position in the center surrounded by the terminals 2 in the terminal arrangement area in which the terminals 2 of the semiconductor device are arranged at equal pitches in the X direction and the Y direction, and around the terminal arrangement area. One is arranged at a predetermined position shifted by a half pitch in each of the X direction and the Y direction. The signal wiring 3 may be arranged on the area of the clearance 5 from the via 4 to the terminal 2 of the corresponding semiconductor device, but is arranged so as not to cross the area of the clearance 5.

  In the via arrangement method according to the first embodiment, it is necessary to arrange the via 4 in the terminal arrangement area. When the signal wiring 3 and the via 4 are automatically arranged by the computer device for wiring design, the terminal arrangement is performed. In the region, a group of four vias arranged in an array of 3 or more in the X direction and m (m ≧ 1) in the Y direction is arranged, and the clearances 5 of the vias 4 are connected in the X direction. In this case, the unit is divided into three units in the X direction and m units in the Y direction, and any one of the vias 4 in one unit is moved around the terminal arrangement area, so that two in the X direction and Y The vias 4 are arranged in an array of m + 1 in the direction, and the continuity of the vias 4 is cut off in the X direction.

  For example, when automatic wiring design is performed by a computer device for wiring design, vias 4 used for wiring connection of terminals 2 of a semiconductor device are continuously arranged in the X direction as shown in FIG. When 5 are connected to each other in the X direction, the unit is divided into 3 units in the X direction and 2 units in the Y direction, and the arrangement of some vias 4 as shown in FIG. The vias 4 arranged continuously in the X direction are arranged for two vias, and the vias 4 arranged continuously in the Y direction are arranged for three, and the vias 4 are arranged in the X direction. Try to break the continuity once. That is, the arrangement of three vias arranged in an array in the X direction and two in the Y direction is changed to two in the X direction and three in the Y direction by moving some vias 4. By changing to a group of continuous vias 4, the width in the X direction of the power supply system pattern 6 between the clearances 5 becomes a width L corresponding to one (one pitch of the via 4) that is a difference in the number of consecutive vias 4. To form.

(Embodiment 2)
A via arrangement method according to Embodiment 2 of the present invention will be described in comparison with a comparative example. FIG. 3 is a partial plan view schematically showing an example of a wiring pattern of a wiring board formed by the via arrangement method according to the second embodiment of the present invention. FIG. 4 is a partial plan view schematically showing an example of a wiring pattern of a wiring board formed by the via arrangement method according to Comparative Example 2.

  In the via arrangement method according to the second embodiment, it is necessary to arrange the vias 4 in the terminal arrangement region and the periphery thereof, and when the signal wiring 3 and the vias 4 are automatically arranged by the computer device for wiring design, When the via arrangement method according to the first embodiment is applied, when the number of terminals 2 of the semiconductor device in the Y direction increases as shown in FIG. 4, the vias 4 are continuously arranged in the Y direction, The clearances 5 of the vias 4 are connected in the Y direction, and the connection of the power supply system pattern 6 in the X direction may be weakened. In this way, when the number of vias 4 arranged in an array of n (n ≧ 2) in the Y direction is arranged, the unit in which the number of continuous vias is limited to 3 in the Y direction at most is applied. One of the divided units (a unit near the periphery of the terminal arrangement region) is further moved by one pitch in the Y direction so that the continuity of the vias 4 is interrupted in the Y direction.

  For example, when automatic wiring design is performed by a computer device for wiring design, vias 4 used for wiring connection of terminals 2 of a semiconductor device are continuously arranged in the Y direction as shown in FIG. When 5 are connected in the Y direction, as shown in FIG. 3, the number of continuous vias in the Y direction is divided into two units, and the units near the divided terminal arrangement area are separated. Further, the arrangement is shifted in the Y direction by one pitch, and the width in the Y direction of the power supply system pattern 6 between the clearances 5 is formed to be a width L corresponding to one pitch of the via 4.

(Embodiment 3)
A via arrangement method according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 5 is a partial plan view schematically showing an example of a wiring pattern of a wiring board formed by the via arrangement method according to Embodiment 3 of the present invention. FIG. 6 is a partial plan view schematically showing an example of a wiring pattern of a wiring board formed by the via placement method according to the third embodiment of the present invention, and FIG. In this case, (B) is a case where the power supply vias are arranged in the Y direction. In FIG. 6, the wiring layer on the power supply pattern and the terminals of the semiconductor device are omitted.

  In the via arrangement method according to the third embodiment, in order to expand the return current path of the power supply system pattern in the wiring board of the first and second embodiments, the terminals of the semiconductor device are arranged in the X direction as shown in FIG. When the power supply terminal 10 and the signal system terminal 2 are arranged in this order, when the signal wiring 3, the power supply wiring 13, the power supply via 11 and the signal via 4 are automatically arranged in the computer device for wiring design, The power system terminal 10 is electrically connected to the power system pattern 6 through the power system wiring 13 and the power system via 11. Thereby, since the vias 4 are not continuously arranged, it is avoided that the clearances 5 are connected to each other. That is, there is no clearance with respect to the power supply system pattern 6 that matches the potential around the power supply system via 11 with respect to the position where the power supply system terminal 10 is disposed. Remains and is not connected to the clearance 5 of the adjacent signal via 4.

  Further, for example, when there are two rows of via 4 arrays, the first row and the second row of the terminals of the semiconductor device are arranged in the X direction in the order of signal system terminals, power system terminals, and signal system terminals. In the case where the power supply vias 11 corresponding to the two power supply system terminals are arranged obliquely, and both the power supply vias 11 and the power supply system pattern 6 are all of the same polarity (power supply or GND), When the signal wiring, the power system wiring, the power system via 11 and the signal via 4 are automatically arranged in the computer device for wiring design, the power system terminal is electrically connected to the power system pattern 6 via the power system wiring and the power system via 11. (See FIG. 6A). As a result, the power supply system pattern 6 remains around the power supply system via 11 and is not connected to the clearances 5 a and 5 b of the adjacent signal vias 4.

  Also, when there are two rows of via 4 arrays, the first row and the second row of the semiconductor device terminals are arranged in the X direction in the order of signal system terminals, power supply system terminals, and signal system terminals. If the power supply vias 11 corresponding to the two power supply system terminals are arranged in the Y direction and both the power supply vias 11 and the power supply system pattern 6 all have the same polarity (power supply or GND), When the signal wiring, the power system wiring, the power system via 11 and the signal via 4 are automatically arranged in the computer device for wiring design, the power system terminal is electrically connected to the power system pattern 6 via the power system wiring and the power system via 11. (See FIG. 6B). As a result, the power supply system pattern 6 remains around the power supply system via 11 and is not connected to the clearances 5 a and 5 b of the adjacent signal vias 4. Note that the case where the power supply vias 11 are arranged side by side in the Y direction as shown in FIG. 6B is more than the case where the power supply vias 11 are arranged obliquely as shown in FIG. Since the width of the power supply system pattern 6 between the clearances 5a and 5b becomes thicker, FIG. 6B is better in terms of arrangement.

(Embodiment 4)
A via arrangement method according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 7 is a partial plan view schematically showing an example of a wiring pattern of a wiring board formed by the via arranging method according to the fourth embodiment of the present invention. FIG. 8 is a partial plan view schematically showing an example of a wiring pattern of a wiring board formed by the via arrangement method according to the fourth embodiment of the present invention. FIG. (B) is a case where the dummy terminals of the semiconductor device are arranged side by side in the Y direction. In FIG. 8, the wiring layer on the power supply pattern and the terminals of the semiconductor device are omitted.

  In the via arrangement method according to the fourth embodiment, in order to expand the return current path of the power supply system pattern in the wiring boards of the first and second embodiments, the terminals of the semiconductor device are arranged in the X direction as shown in FIG. When the dummy terminals 12 (empty terminals not electrically connected to any of the wiring boards) and the signal system terminals 2 are arranged in this order, the signal wiring 3 and the signal via 4 are automatically arranged by a wiring design computer device. In doing so, the dummy terminals 12 are not electrically connected to any of the wiring boards. Thereby, since the vias 4 are not continuously arranged, it is avoided that the clearances 5 are connected to each other. That is, since no wiring or via is required for the dummy terminal 12 and there is no clearance, the power supply system pattern 6 remains between the clearances 5 and is not connected to the clearance 5 of the adjacent signal via 4.

  For example, when there are two rows of via 4 arrays, the first row and the second row of the semiconductor device terminals are arranged in the order of the signal system terminals, dummy terminals, and signal system terminals in the X direction. In the case where the two dummy terminals are arranged obliquely, the dummy terminal is electrically connected to any of the wiring boards when the signal wiring and the signal via 4 are automatically arranged by the computer device for wiring design. (See FIG. 8A). As a result, the power supply system pattern 6 remains in the portion corresponding to the dummy terminal and is not connected to the clearances 5a and 5b of the adjacent signal vias 4.

  In addition, when two arrays of vias 4 exist, the first row and the second row of the semiconductor device terminals are arranged in the order of the signal system terminals, dummy terminals, and signal system terminals in the X direction. When two dummy terminals are arranged side by side in the Y direction, the dummy terminals are electrically connected to any of the wiring boards when the signal wiring and the signal via 4 are automatically arranged by the computer device for wiring design. (See FIG. 8B). As a result, the power supply system pattern 6 remains in the portion corresponding to the dummy terminal and is not connected to the clearances 5a and 5b of the adjacent signal vias 4. In the case where the dummy terminals are arranged side by side in the Y direction, the width of the power supply system pattern 6 between the clearances 5a and 5b is larger than the case where the dummy terminals are arranged obliquely. 8 (B) is better in terms of arrangement.

(Embodiment 5)
A via arrangement method according to Embodiment 5 of the present invention will be described with reference to the drawings. FIG. 9 is a partial plan view schematically showing an example of a wiring pattern of a wiring board formed by the via arranging method according to the fifth embodiment of the present invention.

  In the via arrangement method according to the fifth embodiment, in order to expand the return current path of the power supply system pattern in the wiring board of the first and second embodiments, the signal wirings 3a and 3b and the signal via 4 are connected by a computer device for wiring design. During automatic placement, as shown in FIG. 9, among the outermost terminals of the semiconductor device, the terminal 2a electrically connected to the via 4 via the signal wiring 3a, and the signal wiring 3b drawn from the inner peripheral side The signal wirings 3a and 3b and the signal vias 4 are arranged so that the terminals 2b electrically connected to each other are alternately arranged. Thereby, since the vias 4 are not continuously arranged, it is avoided that the clearances 5 are connected to each other. As a result, even if the number of wirings 3b between the terminals 2 of the semiconductor device is limited to one, there is no need to use a via for the outermost peripheral terminal 2a, and the power supply system pattern 6 remains between the clearances 5 and is adjacent. It does not connect with the clearance 5 of the signal via 4. Further, since the signal wiring 3 b is arranged on the power supply system pattern 6, the signal wiring 3 b does not cross the clearance 5.

  According to Embodiment 1-5, there exist the following effects.

  The first effect is that the power supply system pattern is provided as an ideal power supply path having a low impedance. The reason is that a sufficient pattern width as a power supply system pattern is secured in both the X direction and the Y direction by moving the vias. For example, as shown in FIG. 17B, in the case of the staggered arrangement of the vias 104, the power supply system pattern 106 is formed between the clearances 105 at the diagonal interval (√2 times the pitch) of the vias 104. -5 (except for those related to FIGS. 6A and 8B), the pattern can be formed between the clearances of the two pitch intervals (W in FIG. 17B), so a wider pattern width is secured. In particular, this method is advantageous even when the terminals of the semiconductor device have a narrow pitch.

  The second effect is that the path can be secured in a state where the return current bypassing the signal current is sufficiently small. The reason is that the power supply system pattern between the clearances is arranged in both the X direction and the Y direction by arranging the vias to be minimized. By such arrangement of the power supply system pattern, it is possible to simultaneously realize the minimization of the detour path of the return current with respect to the signal current as the reference plane and the reduction of the impedance of the power supply system pattern.

  The third effect is that even when a semiconductor device having terminals arranged in a circular shape is mounted, the power supply system pattern that exists in the region immediately below the semiconductor device is disconnected from the power supply system pattern that exists in other portions. Without being connected. This is because the power supply system pattern is left between the clearances by arranging the vias in a predetermined unit and avoiding continuity.

  The fourth effect is that when examining the terminal arrangement of a semiconductor device, it can be freely examined without considering the substrate design that tends to be a subsequent process. That is, the arrangement of wirings and vias from arbitrary terminals arranged in an array can be optimized without depending on the terminal arrangement of the semiconductor device. The reason is that the arrangement of vias is devised so that wiring can be made between all terminals of the semiconductor device via the vias.

  The fifth effect is that the cost for substrate production can be reduced. The reason is that even if a basic laminated substrate or through via is used, the wiring can be realized without impairing the substrate characteristics. Use pad-on vias to avoid placing vias close to semiconductor device terminals, or use blind vias on build-up boards to prevent clearances around vias from affecting power system patterns. There is no need.

  The sixth effect is that the number of man-hours for board design can be reduced. The reason for this is that it is not necessary to grasp the portion where the power supply system pattern is weakened due to rounding of a sharp pattern and to spend time for inserting a bridging pattern (109 in FIG. 18) as a reinforcement of the power supply system pattern. This is because it solves the problem with the placement of vias that need to be done in any case. In Embodiment 1-5, a power system pattern that is thicker and stronger than the bridging pattern can be secured.

  The seventh effect is that the connection is possible even if the number of wirings between the terminals of the mounted semiconductor device becomes one.

It is the fragmentary top view which showed typically an example of the wiring pattern of the wiring board formed with the arrangement | positioning method of the via | veer concerning Embodiment 1 of this invention. 6 is a partial plan view schematically showing an example of a wiring pattern of a wiring board formed by a via arrangement method according to Comparative Example 1. FIG. It is the fragmentary top view which showed typically an example of the wiring pattern of the wiring board formed with the via | veer arrangement method which concerns on Embodiment 2 of this invention. 10 is a partial plan view schematically showing an example of a wiring pattern of a wiring board formed by a via arrangement method according to Comparative Example 2. FIG. It is the fragmentary top view which showed typically an example of the wiring pattern of the wiring board formed with the via arrangement | positioning method concerning Embodiment 3 of this invention. It is the fragmentary top view which showed typically an example of the wiring pattern of the wiring board formed with the arrangement | positioning method of the via | veer concerning Embodiment 3 of this invention, (A) is when the power supply system via is arrange | positioned diagonally, B) shows a case where the power supply vias are arranged in the Y direction. It is the fragmentary top view which showed typically an example of the wiring pattern of the wiring board formed with the arrangement | positioning method of the via | veer concerning Embodiment 4 of this invention. It is the fragmentary top view which showed typically an example of the wiring pattern of the wiring board formed with the arrangement | positioning method of the via | veer concerning Embodiment 4 of this invention, (A) is the dummy terminal of a semiconductor device arrange | positioned diagonally (B) shows a case where dummy terminals of the semiconductor device are arranged side by side in the Y direction. It is the fragmentary top view which showed typically an example of the wiring pattern of the wiring board formed with the arrangement | positioning method of the via | veer concerning Embodiment 5 of this invention. It is the (A) partial top view which showed typically the wiring structure of the wiring board which concerns on a prior art example, and (B) the fragmentary sectional view between XX '. It is a fragmentary top view for demonstrating the relationship between the signal current and return current in the wiring board which concerns on a prior art example. It is a partial top view for demonstrating the relationship between the signal current and return current in the wiring board which concerns on a prior art example, (A) When there is no power supply system pattern between clearances, (B) When the diameter of a via is large, (C ) When the clearance diameter is large. It is a partial top view for demonstrating the width | variety of the power supply system pattern between the clearances in the wiring board which concerns on a prior art example, (A) When a power supply system pattern is enough width, (B) When a power supply system pattern is thin. . It is a partial top view for demonstrating the relationship between the continuous clearance in the wiring board which concerns on a prior art example, and a power supply system pattern. It is the fragmentary top view which showed typically the positional relationship of the via | veer of the wiring board which concerns on a prior art example, and the terminal of a semiconductor device. It is the partial top view which showed typically the wiring structure when it is a wiring board which concerns on a prior art example, and the frequency | count of the circumference of the terminal of a semiconductor device exists three times. It is the (A) partial top view and (B) enlarged view which showed typically the wiring structure at the time of arrange | positioning the via | veer in the wiring board which concerns on a reference example in zigzag form. It is a partial top view for demonstrating the power supply system reinforcement | strengthening area | region (ST) with respect to the power supply system reinforcement | strengthening unprocessed area | region (NR) in the wiring board which concerns on a reference example.

Explanation of symbols

2, 2a, 2b, 102 Terminals 3, 3a, 3b, 103 Wiring (signal wiring)
4, 104, 104a, 104b Via (signal via)
5, 5a, 5b, 105, 105a, 105b Clearance 6, 106, 106a, 106b Power supply system pattern (power supply pattern, GND pattern)
7, 107 Dielectric layer 10 Power supply system terminal (power supply terminal, GND terminal)
11 Power supply via 12 Empty terminal (dummy terminal)
13 Power supply wiring (power supply wiring, GND wiring)
101 Semiconductor device 108 Wiring board 109 Power supply system bridging pattern X In the case of a terminal having a circular shape, in the column direction Y In the case of a terminal having a circular shape, in the circumferential direction (row direction)
F In the case of a terminal having a circular shape, the outer peripheral side in the circumferential direction B In the case of a terminal having a circular shape, the inner peripheral side in the circumferential direction IS signal current path IR return current path ST Power supply system reinforcement region by bridging pattern NR Power supply system Reinforced unprocessed area N Clearance distance by staggered via arrangement W Clearance distance by via pitch arrangement

Claims (9)

A method of arranging vias provided in a power supply system pattern facing a signal wiring layer and a dielectric layer,
In the step of arranging the vias, the clearance around the vias is divided into clearance regions that are continuously arranged in a predetermined number, and the power supply system pattern having a predetermined width is continuously provided between the adjacent clearance regions. A method for arranging vias, wherein the vias are arranged so as to be arranged.   In the step of arranging the vias, the vias are arranged so that signal wirings arranged in the signal wiring layer do not cross the clearance region and are arranged in a region where the power supply system pattern is arranged. 2. The method for arranging vias according to claim 1, wherein the vias are arranged.   In the step of arranging the via, the via is arranged at the center surrounded by the terminals at a predetermined position in a terminal arrangement region where at least the terminals of the semiconductor device are arranged at equal pitches in the X direction and the Y direction. 3. The via arrangement method according to claim 1, wherein the via arrangement method is performed.   In the step of arranging the vias, the vias are arranged automatically in an array of 3 or more vias in the X direction and m (m ≧ 1) in the Y direction. Are connected in the X direction, the vias are divided into 3 units in the X direction and m units in the Y direction, and one of the vias in one unit is moved to 2 in the X direction. The vias according to any one of claims 1 to 3, wherein the vias are arranged in an array of m + 1 in the Y direction and continuity is interrupted in the X direction. Placement method.   In the step of arranging the vias, when the vias are arranged in an array of n (n ≧ 2) in the Y direction by the automatic arrangement of the vias, and the clearances are connected in the Y direction, At most, the unit is divided into units with a limit of 3 continuous vias in the Y direction, and one of the units is moved in the Y direction, and the vias are arranged so that the continuity is interrupted in the Y direction. The method of arranging vias according to claim 4, wherein:   When the terminals of the semiconductor device are arranged in the order of the signal system terminal, the power system terminal, and the signal system terminal in the X direction, the power system terminal passes through the power system wiring and the power system via in the step of arranging the via. The power supply system pattern is electrically connected to the power supply system pattern, and the power supply system via is disposed in a region where the power supply system pattern between the clearances is disposed. Item 6. The via arrangement method according to any one of Items 1 to 5.   When the terminals of the semiconductor device are arranged in the order of signal system terminals, dummy terminals, and signal system terminals in the X direction, the dummy terminals are electrically connected to the signal wiring layer and the power system plane in the step of arranging the vias. The vias are arranged so that other vias are not arranged in a region where the power supply system pattern between the clearances is not arranged and the power supply system pattern is arranged. The via placement method described in 1.   A first terminal electrically connected to the via via the first signal wiring of the signal wiring layer among the outermost peripheral terminals of the semiconductor device during the step of arranging the via, from the inner peripheral side 8. The via according to claim 1, wherein the vias are arranged so that second terminals electrically connected to the second signal wiring of the signal wiring layer drawn out are alternately arranged. Arrangement method of via described.   A method for manufacturing a wiring board, comprising the step of forming a via according to the method of any one of claims 1 to 8.

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