JP2008226871A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having excellent high frequency characteristic and a method for manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device is provided, on the principal surface of a substrate, with a group III nitride semiconductor layer formed by epitaxial growth, an active element arranged on the group III nitride semiconductor layer, and an insulated region provided to include at least a part of the interface between the group III nitride semiconductor layer and the substrate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a compound semiconductor and a method for manufacturing the same.

  Active elements such as field effect transistors (hereinafter sometimes referred to as FETs) using compound semiconductors are known. FIG. 1 is a schematic cross-sectional view showing the structure of an FET using a GaAs compound semiconductor. In FIG. 1, 101 is a semi-insulating GaAs substrate, 102 is a buffer layer, 103 is a GaAs channel layer, and 104 is an AlGaAs electron supply layer formed on a part of the channel layer 103. The channel layer 104 and the electron supply layer 104 are compound semiconductor layers. Note that the buffer layer 102 is a base layer provided to obtain a desired crystal structure of the channel layer 104, and may be formed of a compound semiconductor or may be omitted. However, in this specification, the buffer layer 102 is not included in the compound semiconductor layer. On the electron supply layer 104, a gate electrode 111, a source electrode 112, and a drain electrode 113 are provided. A wiring layer 121 is provided over the electron supply layer 104 and the channel layer 103 where the electron supply layer 104 is not provided via an insulating film 106 (in FIG. 1, the wiring 121 on the electron supply layer 104 is provided). Is omitted). The wiring layer 121 is patterned so as to be connected to the gate electrode 112 and the drain electrode 113. The source electrode 112 is connected to a through electrode 131 provided so as to penetrate the substrate through the receiving electrode 130. The through electrode 131 is provided only when the electrical connection with the source electrode can be performed from the back side of the substrate, and is not always provided. Except for the region where the elements (the source electrode 112, the gate electrode 111, and the drain electrode 113) are provided, the electron supply 104 is removed so that parasitic capacitance is not generated between the wiring 121 and the 2DEG. It is inactivated. In order to inactivate 2DEG, a technique of performing ion implantation (see, for example, Patent Document 1, paragraph 0003) is also known.

  An FET using such a compound semiconductor is required to be miniaturized and have good high frequency characteristics. As a technique aiming at miniaturization, for example, a manufacturing method of a compound semiconductor device described in Patent Document 2 is cited. On the other hand, in order to operate the FET at a high frequency, it can be considered that the gate of the FET is miniaturized to the submicron order. However, when the gate is miniaturized, the high-frequency characteristics of the FET are greatly affected by the parasitic capacitance generated at the pad, the parasitic inductance due to the wiring and the wiring resistance (for example, see Non-Patent Document 1).

  By the way, as a compound semiconductor, in addition to the above-described GaAs-based compound semiconductor, a group III nitride semiconductor exemplified by GaN is known.

  FIG. 2 is a diagram schematically showing a cross-sectional structure of an FET using a group III nitride semiconductor. In FIG. 2, reference numeral 201 denotes a semi-insulating SiC substrate, on which a buffer layer 202, a channel layer 203 made of GaN, and an electron supply layer 204 (AlGaN electron supply layer) made of AlGaN are sequentially formed. Here, the channel layer 203 and the electron supply layer 204 are group III nitride semiconductor layers including a group III nitride semiconductor. The buffer layer 202 may be formed of a group III nitride semiconductor, as described in the GaAs compound semiconductor stage, but is not included in the group III nitride semiconductor layer in this specification. Shall. Similarly to the GaAs FET shown in FIG. 1, a gate electrode 211, a source electrode 212, a drain electrode 213, a through electrode 231, a wiring 221, and a receiving electrode 230 are arranged. In addition, two-dimensional electron gas (2DEG) is formed in the channel layer 203 due to piezoelectric charges generated by the lattice constant difference between the channel layer 203 and the electron supply layer 204. The 2DEG is inactivated in the channel layer 202 below the wiring 221 so that no parasitic capacitance is generated between the wiring 221 and the 2DEG.

  When an FET using a GaAs compound semiconductor as shown in FIG. 1 is used as a high frequency amplifier, a plurality of elements having a large gate width are prepared in order to obtain a high output at a high frequency (for example, 10 GHz or more). Therefore, it is necessary to provide a power combining circuit for arranging power in parallel and combining power obtained from each element. Since the power combining circuit is used, the line loss due to the power combining circuit increases as the operating frequency increases.

  On the other hand, the group III nitride semiconductor as shown in FIG. 2 has a large band gap, a high breakdown electric field, and a large electron saturation drift velocity compared to the GaAs compound semiconductor described above. ing. When an FET using a group III nitride semiconductor is used as a high frequency amplifier, an output several times higher than that when a conventional compound semiconductor is used can be obtained when compared with the same gate width. If the same output is obtained, the number of elements to be arranged can be reduced and the line length of the power combining circuit can be shortened as compared with the case of using a conventional compound semiconductor. Therefore, there is an expectation as an FET material which is advantageous for miniaturization and has high reliability and good high frequency characteristics.

  As an FET using such a group III nitride semiconductor, for example, a field effect transistor described in Patent Document 3 can be cited.

“Basics of GaAs Field Effect Transistor” Masumi Fukuda and Yasuhiro Hirachi, IEICE, p. 53 (February 1992) JP 2003-324199 A JP 2003-7725 A Japanese Patent Laid-Open No. 2004-200248

  However, when the present inventors measured the gain of the FET using the group 3 nitride semiconductor, the result as shown in FIG. 3 was obtained. 3 shows an FET provided with a through electrode connected to the source electrode as shown in FIG. 2 (dotted line; With VIA in FIG. 3) and an FET without a through electrode (solid line in FIG. 3; W / O VIA) is a graph showing the relationship between the frequency (horizontal axis; Frequency) and the maximum available gain (vertical axis; MSG / MAG). In addition, about the frequency area | region which does not satisfy the stabilization coefficient K> 1, since the maximum available gain (MAG; Maximum Available Gain) cannot be defined, it is shown by the maximum stabilization gain (MSG; Maximum Stable Gain). As shown in FIG. 3, when the through electrode is provided, the frequency at which the MSG is switched to MAG (conversion frequency) is lower than when no through electrode is provided, and the gain at a high frequency is deteriorated. .

  From the above results, the present inventors considered as follows. That is, when a group III nitride semiconductor is used, an unintended conductive layer is formed at the interface between the substrate and the group III nitride semiconductor layer when the group III nitride semiconductor is formed on the substrate. The formation of this conductive layer is due to the fact that crystal defects are easily introduced at the initial stage of growth when the group III nitride semiconductor layer is epitaxially grown on the substrate. The reason why the crystal defects are easily introduced is that the substrate 201 such as SiC and the group 3 nitride semiconductor are heterovalent materials and have different lattice constants.

  When the through electrode is present, the conductive layer formed as described above becomes a resistance connected to the through electrode and deteriorates the high frequency characteristics. Although not understood from the result of FIG. 3, it is considered that a parasitic capacitance is generated between the wiring 121 provided on the group 3 nitride semiconductor layer and the conductive layer even if there is no through electrode. This parasitic capacitance is considered to degrade the high frequency characteristics. Such a parasitic capacitance is not limited to the wiring part, but may be caused in the same manner in the pad part used for bonding and the lead-out wiring part of the source electrode and drain electrode part of the FET.

  On the other hand, when the relationship between the frequency and the gain was measured in the same manner for the FET using the GaAs compound semiconductor as shown in FIG. 1, the result shown in FIG. 4 was obtained. As can be seen from FIG. 4, in the FET using a GaAs compound semiconductor, a through electrode is provided (dotted line; With VIA in FIG. 4) and not provided (solid line in FIG. 4, W / O VIA). ) And there was no difference in gain. From this, it is considered that the conductive layer described above is formed more significantly when a group III nitride semiconductor is used than when a GaAs compound semiconductor is used.

  Accordingly, an object of the present invention is to provide a semiconductor device having excellent high frequency characteristics and a method for manufacturing the same.

  Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress the influence of the conductive layer formed at the interface between the substrate and the group III nitride semiconductor layer on the high-frequency characteristics.

  [Means for Solving the Problems] will be described below using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  The semiconductor device (30) according to the present invention includes a group 3 nitride semiconductor layer (12, 13) and a group 3 nitride semiconductor layer (12, 13) formed by epitaxial growth on the main surface of the substrate (10). Insulation provided so as to include at least a part of the interface between the active element (1 to 3) disposed above and the insulating element and the group 3 nitride semiconductor layer (12, 13) and the substrate (10) And a conversion region (15).

  According to the present invention, in the insulating region (15), the conductive layer formed at the interface between the substrate and the group 3 nitride semiconductor layer does not deteriorate the high frequency characteristics.

  When the semiconductor device (30) further includes a through electrode (18) provided so as to penetrate the substrate (10) and the group 3 nitride semiconductor layer (12 to 13), the insulating region (15) ) Is preferably provided so as to surround the through electrode (18) in a direction parallel to the substrate plane.

  When the through electrode (18) is present, the conductive layer formed at the interface of the substrate-3 group nitride semiconductor layer is electrically connected to the through electrode (18). Therefore, the conductive layer portion becomes a resistance and deteriorates the high frequency characteristics. By providing the insulating region (15) so as to surround the through electrode (18) in a direction parallel to the substrate plane, the through electrode (18) can be insulated from the conductive layer. As a result, the conductive layer does not become a resistance to the through electrode (18), and deterioration of high frequency characteristics can be suppressed.

  At this time, from one point of view, the insulating region (15) is a trench extending from the main surface side of the substrate (10) to the interface between the group III nitride semiconductor layers (12 to 13) and the substrate (10). Preferably, it is a trench (20) extending from the back side of the substrate to the interface between the group III nitride semiconductor layers (12 to 13) and the substrate (10) from another viewpoint. preferable.

  In another aspect of the semiconductor device (30), the insulating region (15) is preferably a region that has become insulating by being implanted with a dopant.

  In the semiconductor device (30), when the wiring layer (17) is further provided on the group 3 nitride semiconductor layer (12 to 13), the insulating region (15) is at least provided on the wiring layer (17). It is preferable to be provided at a position corresponding to the lower part. Thus, by providing the insulating region (15) at a position corresponding to the lower portion of the wiring layer (17), no parasitic capacitance is generated between the wiring layer (17) and the conductive layer. As a result, deterioration of the high frequency characteristics is suppressed.

  In the semiconductor device (30), the group III nitride semiconductor layers (12 to 13) are preferably provided on the substrate (10) via the buffer layer (11). At this time, the insulating region (15) includes an interface between the substrate (10) and the buffer layer (11), and an interface between the buffer layer (11) and the group III nitride semiconductor layer (12 to 13). Is preferably provided. The buffer layer (11) is an AlN layer, and the group 3 nitride semiconductor layers (12 to 13) are formed on the buffer layer (11) in contact with the buffer layer (11) (12 And an AlGaN layer (13) formed in contact with the GaN layer (12) on the GaN layer (12).

  The manufacturing method of a semiconductor device according to the present invention includes a group 3 nitride semiconductor layer forming step of forming a group 3 nitride semiconductor layer (12 to 13) by epitaxial growth on a main surface of a substrate (10), and a group 3 Insulating region forming step of forming an insulating region (15) by insulating a region including at least part of the interface between the nitride semiconductor layer (12-13) and the substrate (10), and a group III nitride semiconductor An electrode forming step of forming a gate electrode (2), a drain electrode (3), and a source electrode (1) on the layers (12 to 13).

  In the manufacturing method of the semiconductor device, when the through electrode (18) is formed so as to penetrate the substrate (10) and the compound semiconductor (12 to 13), the through electrode (18) is formed in the insulating region forming step. ) Or an insulating region (15) is preferably formed so as to surround a region where the through electrode (18) is to be formed in a direction parallel to the plane of the substrate. From one viewpoint, in the insulating region forming step, the trench (20) extending from the main surface side of the substrate (10) to the interface between the group III nitride semiconductor layers (12 to 13) and the substrate (10) is formed. By forming, it is preferable to form the insulating region (15). From another viewpoint, by forming a trench (20) extending from the back surface side of the substrate (10) to the interface between the group 3 nitride semiconductor layers (12 to 13) and the substrate (10), an insulating region ( 15) is preferably formed.

  In the semiconductor device manufacturing method, from another viewpoint, it is preferable that the insulating region (15) is formed by ion implantation of a dopant in the insulating region forming step.

  In the case where the method for manufacturing a semiconductor device further includes a step of forming a wiring layer (17) on the group 3 nitride semiconductor layer (12 to 13), at least the wiring layer is formed in the insulating region forming step. It is preferable to form the insulating region (15) by insulating the position corresponding to the lower part of (17).

  The method for manufacturing a semiconductor device further includes a step of forming a buffer layer (11) on the substrate (10). In the step of forming a group III nitride semiconductor layer, the group III nitride semiconductor layer (12 ˜13) are preferably formed on the substrate (10) via the buffer layer (11). At this time, in the insulating region forming step, the insulating region (15) includes the interface between the substrate (10) and the buffer layer (11), and the buffer layer (11) and the group III nitride semiconductor layer (12 to 13). It is preferably formed so as to include an interface with The buffer layer (11) is an AlN layer, and in the step of forming a group 3 nitride semiconductor layer, a step of forming a GaN layer (12) on the buffer layer (11) so as to be in contact with the buffer layer (11). And a step of forming an AlGaN layer on the GaN layer (12) so as to be in contact with the GaN layer (12).

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device excellent in a high frequency characteristic and its manufacturing method are provided.

  According to the present invention, there is further provided a semiconductor device capable of suppressing the influence of the conductive layer formed at the interface between the substrate and the group 3 nitride semiconductor layer on the high frequency characteristics and a method for manufacturing the same.

(First embodiment)
FIG. 5 is a schematic cross-sectional view showing the structure of the semiconductor device 30 according to the present embodiment. The semiconductor device 30 includes a substrate 10, a buffer layer 11 formed on the main surface of the substrate 10, a group III nitride semiconductor layer (12, 13) formed on the buffer layer 11, the source electrode 1, A gate electrode 2, a drain electrode 3, a through electrode 18 provided so as to penetrate the substrate 10 and the group 3 nitride semiconductor layer (12, 13), a wiring 17, and an insulating region 15. ing.

  As the substrate 10, a semi-insulating substrate is used. Examples of the substrate 10 include a c-plane SiC substrate and a sapphire substrate. This substrate 10 is a growth substrate for epitaxially growing the group 3 nitride semiconductor layer 10.

  The buffer layer 11 is provided for satisfactorily epitaxially growing the group 3 nitride semiconductor layers (12, 13) on the substrate 10, and may be omitted. In the present embodiment, the buffer layer 11 is an undoped AlN layer. The thickness of the buffer layer 11 is sufficiently thinner than the group 3 nitride semiconductor layers (12, 13), for example, 20 nm.

  The group III nitride semiconductor layer (12, 13) includes a channel layer 12 and an electron supply layer 13. The channel layer 12 is formed on the buffer layer 11 in contact with the buffer layer 11. In the present embodiment, the channel layer 12 is an undoped GaN layer. The thickness of the channel layer is, for example, 20 μm. On the other hand, the electron supply layer 13 is formed on the channel layer 12 in contact with the channel layer 12. The electron supply layer 13 is an undoped AlGaN layer. The electron supply layer 13 has a thickness of, for example, 25 nm. The channel layer 12 and the electron supply layer 13 are layers formed by epitaxial growth. The electron supply layer 13 and the channel layer 12 are joined by a heterojunction. By this heterojunction, a two-dimensional electron gas (2DEG) is distributed at the junction interface with the electron supply layer 13 in the channel layer 12.

  In addition, the electron supply layer 13 is removed in a part of the group 3 nitride semiconductor layers (12, 13) (hereinafter, element isolation mesa). Since there is no heterojunction in the element separation mesa portion, the two-dimensional electron gas (2DEG) is also deactivated.

  The source electrode 1, the gate electrode 2, and the drain electrode 3 are each disposed on the electron supply layer 13. The source electrode 1 and the drain electrode 3 are joined to the electron supply layer 13 through ohmic contact, and the gate electrode 2 is joined to the electron supply layer 13 through Schottky contact. On the electron supply layer 13, a portion where the gate electrode 2, the source electrode 1, and the drain electrode 3 are not provided is covered with an insulating film 21 (example: SiN film). The insulating film 21 is also provided on a part of the channel layer 12 exposed in the element isolation mesa.

  The wiring layer 17 is provided on the channel layer 12 via the insulating film 21 in the element isolation mesa. The wiring layer 17 is made of, for example, a metal having good conductivity such as gold. The wiring layer 17 is patterned so as to be connected to the gate electrode 2 and the drain electrode 3, respectively.

  The through electrode 18 is provided so as to penetrate the back surface side of the substrate 10 and the channel layer 12. In the present embodiment, it is provided in the region of the element isolation mesa and is connected to the receiving electrode 19 on the channel layer 12. The receiving electrode 19 is connected to the source electrode 1, whereby the through electrode 18 is electrically connected to the source electrode 18.

  The insulating region 15 is provided in a region including the lower interface of the channel layer 12 in a region corresponding to the element isolation mesa. In the present embodiment, the buffer layer 11 is provided, and the buffer layer 11 -channel layer 12 interface and the buffer layer 11 -substrate 10 interface are provided. Since the buffer layer 11 is sufficiently thin as compared with the channel layer 12, the buffer layer 11 can be regarded as substantially the interface between the channel layer 12 and the substrate 10. Therefore, in this specification, in the following description, the buffer layer 11 portion may be described as the channel layer 12-substrate 10 interface. By providing the insulating region 15 at such a position, the periphery of the through electrode 18 is surrounded by the insulating region 15 at the interface portion of the channel layer 12 and the substrate 10. Further, the insulating region 15 is also disposed in a region corresponding to the lower portion of the wiring 17 on the element isolation mesa.

  The semiconductor device 1 having the above-described configuration can be manufactured as follows, for example.

  First, a buffer layer 11 (film thickness) made of undoped AlN is formed on the substrate 10 by, for example, a molecular beam epitaxy (MBE) growth method or a metal organic vapor phase epitaxy (MOVPE) growth method. 20 nm), an undoped GaN channel layer 12 (film thickness 2 μm), and an AlGaN electron supply layer 13 (film thickness 25 nm) made of undoped AlGaN are deposited in this order.

  At this time, a crystal defect or the like occurs in the early stage of the growth of the channel layer 12, whereby an unintended conductive layer 16 (see FIG. 5) is formed at the lower interface portion of the channel layer 12.

  Next, an SiN film 21 (60 nm) as an insulating film 21 is formed on the AlGaN electron supply layer 13 by plasma CVD or the like.

  Subsequently, in the region where the element isolation mesa is to be formed, the insulating film 21 and the electron supply layer 13 are etched to expose the channel layer 12. Thereby, an element isolation mesa is formed. By forming the element isolation mesa, 2DEG of the channel layer 12 is inactivated.

  Next, dopant is ion-implanted in this region (interelement isolation mesa) to a depth that reaches the interface portion between the channel layer 12 and the substrate 10. As the dopant at this time, for example, nitrogen ions are used. By this ion implantation, an insulating region 15 is formed at a position corresponding to the element isolation mesa, and the conductive layer 16 disappears. The ion implantation range includes the interface between the substrate 10 and the channel layer 12 and is preferably 0.2 μm or more. This ion implantation may be performed from the surface of the group III nitride semiconductor because the high-frequency gain is improved if the conductive layer existing at least under the region having the wiring is insulated. More preferably, ion implantation is also performed from the substrate side to insulate the conductive layer under the active element (gate electrode, source electrode, drain electrode), thereby further improving the high frequency characteristics.

  Next, the source electrode 1 and the drain electrode 3 are formed. Specifically, in a region where the source electrode 1 and the drain electrode 3 are to be formed, a part of the insulating film 21 provided on the electron supply layer 13 is removed by a photolithography technique using a photoresist, and an electron The supply layer 13 is exposed. Then, the source electrode 1 and the drain electrode 3 are formed by evaporating a metal such as Ti / Al. Further, for example, annealing is performed at a temperature of 650 ° C., thereby bringing the source electrode 1 and the drain electrode 3 into ohmic contact with the group 3 nitride semiconductor layers (12, 13).

  Next, the gate electrode 2 is formed. Specifically, in the region where the gate electrode 2 is to be formed, a part of the insulating film 21 is removed by a photolithography technique using a photoresist to expose the electron supply layer 13. On the exposed AlGaN electron supply layer 13, a gate metal such as Ni / Au is deposited to form the gate electrode 2 in Schottky contact with the Group 3 nitride semiconductor layers (12, 13). In this embodiment, a rectangular gate electrode structure will be described. However, for example, a T-shaped, Y-shaped, or mushroom-shaped structure formed by using an electron beam drawing technique may be adopted.

  Next, the through electrode 18 is formed. Specifically, a through hole reaching the receiving electrode 19 is formed from the back side of the substrate 10 by a dry etching method or the like. Then, the back surface of the substrate and the side surfaces of the through holes are covered with a metal such as gold by sputtering or plating. Thereby, the through electrode 18 is formed.

  Also, the wiring layer 17 and the receiving electrode 19 can be formed by using a lithography technique as in the method of forming the source electrode 1, the gate electrode 2, and the drain electrode 3. In this way, the semiconductor device 1 shown in FIG. 5 is manufactured.

  As described above, according to the semiconductor device 1 according to the present embodiment, the conductive layer 16 around the through electrode 18 is insulated by the insulating region 15. Therefore, the conductive layer 16 is not electrically connected to the through electrode 18, and the conductive layer 16 becomes a resistance and does not deteriorate high frequency characteristics.

  Actually, for the semiconductor device 1 described in the present embodiment by the present inventors, the relationship between the maximum stabilization gain (MSG) and the operating frequency was measured between 100 MHz and 40 GHz, and the result shown in FIG. 6 was obtained. Obtained. In FIG. 6, the dotted line is the result when the through electrode 18 is provided (semiconductor device described in the present embodiment), and the solid line is the result when the through electrode 18 is not provided. As shown in FIG. 6, there was almost no difference in gain between when the through electrode 18 was provided and when it was not provided. That is, as in the conventional example of FIG. 3, when the through electrode 18 is provided, no behavior is shown in which the gain decreases in the high frequency band. From this, it was confirmed that the deterioration of the high frequency characteristics can be suppressed by providing the insulating region 15 around the through electrode 18.

  In the wiring layer 17, the conductive layer 16 below the wiring layer 17 is insulated by the insulating region 15 in the portion formed in the element isolation mesa. As a result, no parasitic capacitance is generated below the wiring layer 17. As a result, deterioration of the high frequency characteristics is suppressed. That is, in the present embodiment, an example in which the through electrode 18 is provided has been described. However, regardless of the presence or absence of the through electrode, if the insulating region 15 is provided in a part of the lower portion of the wiring layer 17, The effect of improving the high frequency characteristics can be achieved.

(Second Embodiment)
Next, the second embodiment will be described. FIG. 7 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. The semiconductor device 1 is different from the first embodiment in that an insulating region 15 is formed by a trench 20. Since the structure other than the insulating region 15 can be the same as that of the first embodiment, the description thereof is omitted.

  The trench 20 is provided so as to surround the through electrode 18 in a direction parallel to the substrate plane, and extends so as to reach the substrate 10 from the main surface side toward the back surface side. The inside of the trench may be a gap or an insulator may be embedded.

  Such a trench 20 can be formed by a dry etching method or the like after the element isolation mesa is formed.

  According to the present embodiment, the through electrode 18 is electrically isolated from the conductive layer 16 by the trench 20. Therefore, similarly to the first embodiment, the conductive layer 16 becomes a resistance, and it can be prevented that the high frequency characteristics are deteriorated.

(Third embodiment)
A third embodiment will be described with reference to FIG.

  As shown in FIG. 8, the semiconductor device 1 according to the present embodiment differs from the second embodiment in that the trench 20 extends from the back surface rather than from the main surface of the substrate. ing. Since points other than the position of the trench 20 are the same as those in the second embodiment, description thereof will be omitted.

  The trench 20 extends from the back side of the substrate 10 to reach the GaN channel layer 12 so as to surround the periphery of the through electrode 18. The trench can be formed by removing the substrate 10 and the buffer layer 11 from the back surface side of the substrate 10 to a depth reaching the channel layer 12 by a dry etching method or the like.

  According to the present embodiment, since the periphery of the through electrode 18 is surrounded by the trench 20, the deterioration of the high frequency characteristics is suppressed as in the described embodiment.

  Further, since the trench 20 extends from the back side of the substrate 10, it is possible to prevent the processing steps for the main surface side such as the source electrode 1 and the gate electrode 2 from becoming complicated. Further, there is no damage to the main surface side during dry etching. Therefore, it is easy to simplify the manufacturing process.

  Although the first to third embodiments have been described above, these may be combined within a consistent range. For example, when the insulating region 15 is formed, a trench 20 may be further provided after ion implantation. Even if it does in this way, it will be obvious for those skilled in the art that the improvement of the above-mentioned high frequency characteristic can be expected.

It is sectional drawing which shows typically the structure of the conventional GaAs type compound semiconductor FET. It is sectional drawing which shows typically the structure of the conventional group 3 nitride semiconductor FET. It is the graph which showed the relationship between the gain and frequency of the conventional group 3 nitride semiconductor FET. It is the graph which showed the relationship between the gain and frequency of the conventional GaAs type compound semiconductor FET. It is sectional drawing which shows typically the structure of the semiconductor device of 1st Embodiment. It is the graph which showed the relationship between the gain and frequency of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the semiconductor device of 2nd Embodiment typically. It is sectional drawing which shows the semiconductor device of 3rd Embodiment typically.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Source electrode 2 Gate electrode 3 Drain electrode 10 Substrate 11 Buffer layer 12 GaN channel layer 13 AlGaN electron supply layer 15 Insulating region 16 Conductive layer 17 Wiring 18 Through electrode 19 Receiving electrode 20 Trench 21 SiN film 111 Gate electrode 112 Source electrode 113 Drain electrode 101 Substrate 102 Buffer layer 103 GaN channel layer 104 AlGaN electron supply layer 106 SiN film 121 Wiring 130 Receiving electrode 131 Through electrode 211 Gate electrode 212 Source electrode 213 Drain electrode 201 Substrate 202 Buffer layer 203 GaN channel layer 204 AlGaN electron supply layer 206 SiN film 221 Wiring 230 Receiver electrode 231 Through electrode

Claims (19)

A group 3 nitride semiconductor layer formed by epitaxial growth on the main surface of the substrate;
An active device disposed on the group III nitride semiconductor layer;
An insulating region that is insulative and is provided to include at least a part of an interface between the group III nitride semiconductor layer and the substrate;
A semiconductor device comprising: A semiconductor device according to claim 1,
The active element is
A source electrode and a drain electrode disposed on the group 3 nitride semiconductor layer;
And a gate electrode disposed between the source electrode and the drain electrode. A semiconductor device according to claim 1 or 2,
Furthermore,
Comprising a through electrode provided so as to penetrate the substrate and the group 3 nitride semiconductor layer;
The insulating region is a semiconductor device provided so as to surround the through electrode in a direction parallel to a substrate plane. A semiconductor device according to any one of claims 1 to 3,
The insulating region is a semiconductor device that is a region that has become insulating by implantation of a dopant. A semiconductor device according to any one of claims 1 to 3,
The semiconductor device is a semiconductor device, wherein the insulating region is a trench extending from a main surface side to a back surface side of the substrate. A semiconductor device according to any one of claims 1 to 3,
The semiconductor device is a semiconductor device in which the insulating region is a trench extending from the back surface side to the main surface side of the substrate. A semiconductor device according to claim 1,
Furthermore,
A wiring is provided on the group 3 nitride semiconductor layer,
The semiconductor device is provided such that the insulating region includes a position corresponding to a lower portion of the wiring. A semiconductor device according to any one of claims 1 to 7,
A semiconductor device in which a buffer layer is provided between the group III nitride semiconductor layer and the substrate. A semiconductor device according to claim 8, wherein
The semiconductor device is provided so that the insulating region includes an interface between the substrate and the buffer layer and an interface between the buffer layer and the group III nitride semiconductor layer. A semiconductor device according to claim 8 or 9, wherein
The buffer layer is an AlN layer;
The group III nitride semiconductor layer is
A GaN layer formed on and in contact with the buffer layer;
A semiconductor device comprising: an AlGaN layer formed on and in contact with the GaN layer. A group 3 nitride semiconductor layer forming step of forming a group 3 nitride semiconductor layer on the main surface of the substrate by epitaxial growth;
An insulating region forming step of forming an insulating region by insulating a region including at least a part of an interface between the group III nitride semiconductor layer and the substrate;
An electrode forming step of forming a gate electrode, a drain electrode, and a source electrode on the group III nitride semiconductor layer;
A method for manufacturing a semiconductor device comprising: A method of manufacturing a semiconductor device according to claim 11,
Furthermore,
Forming a through electrode so as to penetrate the substrate and the group III nitride semiconductor layer;
Comprising
A method of manufacturing a semiconductor device, wherein in the insulating region forming step, the insulating region is formed so as to surround the through electrode or a region where the through electrode is to be formed in a direction parallel to a substrate plane. A method of manufacturing a semiconductor device according to claim 12,
A method of manufacturing a semiconductor device, wherein the insulating region is formed by forming a trench extending from a main surface side of the substrate to an interface between the group III nitride semiconductor layer and the substrate in the insulating region forming step. A method of manufacturing a semiconductor device according to claim 12,
A method of manufacturing a semiconductor device, wherein the insulating region is formed by forming a trench extending from the back surface side of the substrate to the interface between the group III nitride semiconductor layer and the substrate in the insulating region forming step. A method of manufacturing a semiconductor device according to claim 11 or 12,
A method of manufacturing a semiconductor device, wherein the insulating region is formed by ion implantation of a dopant in the insulating region forming step. A method of manufacturing a semiconductor device according to claim 11,
In addition,
Forming a wiring layer on the group III nitride semiconductor layer;
Comprising
A method of manufacturing a semiconductor device, wherein the insulating region is formed by insulating at least a region corresponding to a lower portion of the wiring layer in the insulating region forming step. A method for manufacturing a semiconductor device according to claim 11, comprising:
Furthermore,
Forming a buffer layer on the substrate;
Comprising
In the group III nitride semiconductor layer forming step, the group III nitride semiconductor layer is formed on the substrate via the buffer layer. A method of manufacturing a semiconductor device according to claim 17,
In the insulated region forming step, the insulated region is formed so as to include an interface between the substrate and the buffer layer and an interface between the buffer layer and the group III nitride semiconductor layer. Production method. A method of manufacturing a semiconductor device according to claim 17 or 18,
The buffer layer is an AlN layer;
The group III nitride semiconductor layer forming step includes:
Forming a GaN layer on the buffer layer so as to be in contact with the buffer layer;
Forming an AlGaN layer on the GaN layer so as to be in contact with the GaN layer.

Images