JP2008226199A - Timing analysis method, timing analysis device, and cell library - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve analysis accuracy of delay of a semiconductor integrated circuit. <P>SOLUTION: The timing analysis device calculates dispersion values for every logic cells referring to delay and its dispersion for every voltage values applied to a logic cell (S14), and performs analysis of delay of signal path of a semiconductor integrated circuit referring to the calculated dispersion values (S15). Thereby range of dispersion values of delay of the signal paths of the semiconductor integrated circuit can be limited by performing timing analysis considering dispersion values of delay about for every voltage values being changed by voltage drop and placement position of logic cells. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a timing analysis method, a timing analysis apparatus, and a cell library, and more particularly to a timing analysis method, a timing analysis apparatus, and a cell library for analyzing a signal path delay of a semiconductor integrated circuit including a logic cell.

  In recent years, logic circuits (logic cells) having a scale exceeding 1 million gates and LSIs (Large Scale Integration) having an operating frequency of several hundred MHz have been developed one after another. In such LSI design work, the ratio of the timing design for operating all the logic circuits on the chip at a desired speed is gradually increasing.

  In addition, the variation in the electrical characteristics of the transistors constituting the logic circuit occurs due to factors such as manufacturing variations and operating environments. Therefore, in an LSI configured by connecting logic circuits to each other by wiring, variation occurs in the delay of a signal propagating between a series of logic circuits.

For this reason, LSI was developed with a design margin (design margin) at the time of manufacture, and furthermore, by using a statistical method that can individually evaluate delay variations according to signal paths, design margin can be increased without excess or deficiency. An LSI can be designed by providing (see, for example, Patent Document 1).
JP 2004-252831 A

  However, since voltage drops occur in the chip, the voltage value differs depending on the logic cell and its arrangement position. Therefore, setting a design margin with a uniform variation value of the delay due to the voltage drop provides an excessive margin guarantee and is wasteful. There was a problem that it was a design.

  The present invention has been made in view of these points, and an object of the present invention is to provide a timing analysis method, a timing analysis apparatus, and a cell library that improve the delay analysis accuracy of a semiconductor integrated circuit.

  In the present invention, in order to solve the above problem, in the timing analysis method for analyzing the delay of the signal path of the semiconductor integrated circuit including the logic cell, the layout of the logic cell is determined from the layout data of the semiconductor integrated circuit as shown in FIG. A step of calculating logic cell information relating to the position and voltage range (S12), and for each operating voltage value applied to the logic cell, through information relating to the slew rate of the logic cell and load information relating to the wiring resistance and wiring capacitance of the logic cell are stored. A step of calculating a delay for each operation voltage value and a variation value of the delay with reference to the voltage condition parameter storage unit generated, and generating a cell library storing the delay and the variation value; A step of calculating a variation value for each logic cell with reference to the cell library (S14), and a step for each logic cell. Referring to per value, a step (S15) for analyzing the delay of the logic cell, timing analysis method characterized in that it comprises a are provided.

  According to such a timing analysis method, the delay for each operation voltage value applied to the logic cell and the variation value of the delay are referred to, the variation value for each logic cell is calculated, and the calculated variation value is referred to. The signal path delay of the semiconductor integrated circuit is analyzed.

  According to another aspect of the present invention, there is provided a timing analysis apparatus for analyzing a delay of a signal path of a semiconductor integrated circuit including a logic cell. A voltage condition parameter storage unit storing through information regarding the slew rate of the logic cell and load information regarding wiring resistance and wiring capacity of the logic cell for each operating voltage value applied to the logic cell, and for each operating voltage value A cell library in which the delay and a variation value of the delay are stored; a logic cell information calculating unit that calculates logic cell information related to an arrangement position and a voltage range of the logic cell with reference to the layout data storage unit; A cell library that generates the cell library with reference to a voltage condition parameter storage unit A timing variation value calculating unit that calculates the variation value for each logic cell with reference to the logic cell information and the cell library, and the logic value with reference to the variation value for each logic cell. And a timing analysis unit that analyzes the delay of the cell.

  According to such a timing analysis device, the delay for each operating voltage value applied to the logic cell and the variation value of the delay are referred to, the variation value for each logic cell is calculated, and the calculated variation value is referred to. The signal path delay of the semiconductor integrated circuit is analyzed.

  According to the present invention, in order to solve the above-mentioned problem, for each operating voltage value applied to the logic cell of the semiconductor integrated circuit, through information regarding the slew rate of the logic cell and load information regarding the wiring resistance and wiring capacitance of the logic cell; Is stored, the delay for each operating voltage value and the variation value of the delay are calculated, and a cell library in which the delay and the variation value are stored is provided.

  According to such a cell library, the delay for each operating voltage value applied to the logic cell and the delay variation value are referred to.

  In the present invention, referring to the delay for each voltage value applied to the logic cell and the variation value of the delay, the variation value for each logic cell is calculated, and referring to the calculated variation value, the signal path of the semiconductor integrated circuit is calculated. Delay analysis was performed. As a result, for each voltage value that fluctuates depending on the voltage drop or arrangement position of the logic cell, the timing analysis is performed in consideration of the delay variation value, thereby narrowing the range of the signal path delay variation value of the semiconductor integrated circuit. Can do.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments.
First, the form considered in the process leading to the present invention will be described, and the outline of the present invention and the embodiment will be described in order.

FIG. 7 is an analysis flow diagram of a timing analysis method considered in the process leading to the present invention.
The timing analysis of the delay of the signal path of the semiconductor integrated circuit considered in the process leading to the present invention will be described with reference to the analysis flowchart 500 below.

[Step S501] The layout design of the semiconductor integrated circuit is performed with reference to the logic circuit information.
[Step S502] The power consumption of each cell is calculated from the designed semiconductor integrated circuit.

  [Step S503] The power supply network analysis of the semiconductor integrated circuit whose power consumption is below the limit value is performed from the layout data designed in Step S501 and the power consumption of the cell, and the operation voltage value (= standard voltage value−voltage drop value). ) Is calculated. Then, it is determined whether or not the calculated operating voltage value satisfies a preset reference value. If the reference value is not satisfied, the process proceeds to step S501 again. If the reference value is satisfied, the process proceeds to step S504.

[Step S504] The variation value of the delay of the signal path of the designed semiconductor integrated circuit is calculated.
[Step S505] The delay variation value obtained in step S504 is referred to, and the timing analysis of the delay of the signal path of the semiconductor integrated circuit is performed. As a result of the analysis, if there is a timing error, the process proceeds to step S501 again. If there is no timing error, it is confirmed that the designed semiconductor integrated circuit operates in a normal range, and the timing analysis ends.

FIG. 8 is a graph showing the operating voltage dependence of the variation value.
In FIG. 8, the horizontal axis represents the operating voltage value (VDD [V]) of the logic cell, and the vertical axis represents the variation value (σ / μ [standard deviation / average value]) of the delay of the signal path with respect to the operating voltage value. ing. FIG. 8 shows that the delay variation value changes depending on the operating voltage value of the logic cell. As described above, since voltage drop occurs depending on the logic cell or its arrangement position, the operating voltage value is assumed to be a voltage value in which the voltage drop is considered in the standard voltage value in the logic cell.

  Therefore, in the timing analysis of the signal path delay of the semiconductor integrated circuit along the flow of the analysis flow diagram 500 of FIG. 7, the influence of the variation value of the delay that varies due to the voltage drop due to the logic cell and its arrangement position is considered. It is not analyzed, and the variation value is analyzed uniformly, and accurate timing analysis is not performed. For this reason, it is necessary to set an excessive design margin in the design of the semiconductor integrated circuit, resulting in a wasteful design.

On the other hand, the outline | summary of this invention is demonstrated.
FIG. 1 is an analysis flow schematic diagram showing an outline of the timing analysis method of the present invention.
Below, the outline | summary of the timing analysis method of this invention is demonstrated using this analysis flow outline figure 10. FIG.

[Step S11] With reference to the layout data, the layout design of the semiconductor integrated circuit is performed.
[Step S12] For the designed semiconductor integrated circuit, logic cell information relating to the arrangement position and voltage range of the logic cell is calculated.

  [Step S13] With reference to the voltage condition parameter in which the through information regarding the slew rate and the load information regarding the wiring resistance and the wiring capacitance are stored for each voltage value of the logic cell, the delay for each operating voltage value of the logic cell is determined. A delay variation value is calculated. Then, a cell library is generated in which the delay for each operating voltage value of the logic cell and the variation value of the delay are stored.

[Step S14] With reference to the cell library and the logic cell information, a delay variation value of the logic cell is calculated.
[Step S15] Timing analysis of the semiconductor integrated circuit is performed using the delay variation value of each logic cell calculated in Step S14.

  In the present invention, according to the above steps, the timing analysis is performed in consideration of the variation value of the delay for each operating voltage value that varies due to the voltage drop due to the logic cell and the arrangement position thereof, so that it is given uniformly in the past. The range of variation values of delay can be narrowed. Therefore, the timing analysis of the semiconductor integrated circuit can be accurately performed, and the obtained result can be close to the actual device of the semiconductor integrated circuit. Therefore, it is not necessary to guarantee an excessive design margin, and it becomes possible to design a semiconductor integrated circuit without waste.

Next, embodiments will be described.
In the present embodiment, the timing analysis is performed in consideration of a delay variation value that varies depending on the operating voltage value of the logic cell, which is configured by one timing analysis device.

FIG. 2 is a diagram illustrating a hardware configuration of the timing analysis apparatus according to the embodiment.
The timing analysis apparatus 100 is controlled by a CPU (Central Processing Unit) 101 as a whole. A random access memory (RAM) 102, a hard disk drive (HDD) 103, a graphic processing device 104, and an input interface 105 are connected to the CPU 101 via a bus 106.

  The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data necessary for processing by the CPU 101. The HDD 103 stores an OS program and application programs.

A monitor 21 is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 21 in accordance with a command from the CPU 101.
A keyboard 22 and a mouse 23 are connected to the input interface 105. The input interface 105 transmits a signal sent from the keyboard 22 or the mouse 23 to the CPU 101 via the bus 106.

With the hardware configuration as described above, the processing functions of the present embodiment can be realized.
FIG. 3 is a block diagram illustrating functions of the timing analysis apparatus according to the embodiment.

  The timing analysis apparatus 100 includes a layout data storage unit 110, a voltage condition parameter storage unit 120, a cell library 130, an initial setting unit 140, a logic cell information calculation unit 150, a cell library generation unit 160, a timing variation value calculation unit 170, and a timing analysis. Part 180.

The layout data storage unit 110 stores layout data.
The voltage condition parameter storage unit 120 stores through information on the slew rate of the logic cell and load information on wiring resistance and wiring capacitance for each operating voltage value applied to the logic cell. These pieces of information are managed and stored as a table or a function.

The cell library 130 describes the operating voltage value of the logic cell, the delay corresponding to the operating voltage value, and its variation value.
The initial setting unit 140 includes a layout design unit 140a, a power consumption calculation unit 140b, and a power supply network analysis unit 140c, and performs initial setting of a semiconductor integrated circuit to be analyzed.

The layout design unit 140a refers to the layout data storage unit 110 and performs layout wiring such as logic cells in the semiconductor integrated circuit by layout design.
The power consumption calculation unit 140b calculates the power consumption of the semiconductor integrated circuit designed by the layout design unit 140a. It is determined whether or not the calculated power consumption satisfies a predetermined reference value.

  The power supply network analysis unit 140c analyzes the power supply network of the semiconductor integrated circuit designed by the layout design unit 140a and calculates a voltage drop value. It is determined whether or not the calculated voltage drop value satisfies a predetermined reference value.

The logic cell information calculation unit 150 refers to the layout data storage unit 110 and calculates the arrangement position and voltage range of the logic cell.
FIG. 4 is an example of a list showing a net list and logic cell information. 4A, the cell “AAA” is connected to “net1” and “net2”, and in the list 161b, the cell “AAA” is connected to “net3” and “net4”. Is shown. The list 162a and 162b of the logic cell information list in FIG. 4B indicates “cell name, minimum operating voltage value, maximum operating voltage value, cell connection information”.

  For example, when the logic cell information calculation unit 150 calculates the arrangement position and voltage range of the logic cell from the net list shown in FIG. 4A, the logic cell information list shown in FIG. 4B is obtained.

  The cell library generation unit 160 refers to the voltage condition parameter storage unit 120 to generate an operation voltage value of the logic cell, a delay corresponding to each operation voltage value, and a variation value of the delay, and store the generated delay value in the cell library 130. .

FIG. 5 is an example table showing delay variation values with respect to operating voltage values of logic cells.
In the cell library 130, for example, as shown in FIG. 5, delay variation values for each operating voltage value are managed and stored as a table. In the cell library 130, in addition to the table, for example, the average value μ = f (VDD), the standard deviation σ = g (VDD) (f () is a function with respect to the voltage value of the average value, and g () is the voltage of the standard deviation. It is also possible to manage and store as a function such as a function for a value, VDD is an operating voltage value.

  The timing variation value calculation unit 170 recognizes a logic cell from the layout data, refers to the logic cell information and the cell library 130, and calculates a variation value of the delay of the logic cell. For example, referring to FIG. 5 again, when the operating voltage value is 1.1 V or more according to the result of the power supply network analysis, the variation value at 1.1 V (0.07 at 1σ) is applied.

  The timing analysis unit 180 refers to the variation value calculated by the timing variation value calculation unit 170, analyzes the signal path delay of the semiconductor integrated circuit, and determines whether there is a timing error.

  As described above, in the timing analysis device 100, the timing analysis unit 180 performs analysis in consideration of the signal path delay variation value of the operating voltage value applied to the logic cell generated by the timing variation value calculation unit 170. Is called.

Next, timing analysis using such a timing analysis apparatus 100 will be specifically described with reference to an analysis flowchart.
FIG. 6 is a flowchart of the timing analysis apparatus according to the embodiment.

Timing analysis of the semiconductor integrated circuit performed by the timing analysis apparatus 100 will be described below with reference to an analysis flowchart 20.
[Step S21] The layout design unit 140a of the initial setting unit 140 refers to the layout data storage unit 110 to design a semiconductor integrated circuit.

[Step S22] The power consumption calculation unit 140b of the initial setting unit 140 calculates the power consumption of each cell of the semiconductor integrated circuit designed in step S21.
[Step S23] The power supply network analysis unit 140c of the initial setting unit 140 performs a power supply network analysis of the semiconductor integrated circuit designed in step S21 and whose power consumption satisfies the reference value, and calculates an operating voltage value. The power supply network analysis unit 140c determines whether the calculated operating voltage value satisfies a preset reference value. If the reference value is not satisfied, the process proceeds to step S21 again. If the reference value is satisfied, the process proceeds to step S24.

[Step S24] The logic cell information calculation unit 150 refers to the layout data storage unit 110 to calculate the arrangement position and voltage range of the logic cell.
[Step S <b> 25] The cell library generation unit 160 refers to the voltage condition parameter storage unit 120 and calculates the operating voltage value of the logic cell, the delay corresponding to the operating voltage value, and the delay variation value. The cell library generation unit 160 generates a cell library 130 that holds the calculated operating voltage value of the logic cell, a delay corresponding to the operating voltage value, and a variation value of the delay.

  [Step S26] The timing variation value calculation unit 170 refers to the logic cell information and the cell library 130, and calculates the variation value of the delay of the logic cell using, for example, the Monte Carlo method.

  [Step S27] The timing analysis unit 180 uses the variation value calculated by the timing variation value calculation unit 170 to analyze the delay of the semiconductor integrated circuit. If there is a timing error as a result of the analysis, the process proceeds to step S21 again. If there is no timing error, it is confirmed that the designed semiconductor integrated circuit operates in a normal range, and the timing analysis is completed.

  As described above, for each operating voltage value that fluctuates due to a voltage drop due to a logic cell and its arrangement position, timing variation is considered in consideration of the delay variation value, so that the delay variation that was conventionally given uniformly can be obtained. The range of values can be narrowed. Therefore, the timing analysis of the semiconductor integrated circuit can be accurately performed, and the obtained result can be close to the actual device of the semiconductor integrated circuit. Therefore, it is not necessary to guarantee an excessive design margin, and it becomes possible to design a semiconductor integrated circuit without waste.

It is the analysis flow schematic which showed the outline | summary of the timing analysis method of this invention. It is a figure which shows the hardware constitutions of the timing analysis apparatus in embodiment. It is a block diagram which shows the function of the timing analysis apparatus in embodiment. It is an example of the list | wrist which shows a net list and logic cell information. It is an example of a table showing delay variation values with respect to operating voltage values of logic cells. It is a flowchart figure of the timing analysis device in an embodiment. It is an analysis flowchart of the timing analysis method considered in the process leading to the present invention. It is the graph which showed the operating voltage dependence of the variation value.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Timing analysis apparatus 110 Layout data storage part 120 Voltage condition parameter storage part 130 Cell library 140 Initial setting part 140a Layout design part 140b Power consumption calculation part 140c Power supply network analysis part 150 Logic cell information calculation part 160 Cell library generation part 170 Timing variation Value calculation unit 180 Timing analysis unit

Claims (7)

In a timing analysis method for analyzing a delay of a signal path of a semiconductor integrated circuit including a logic cell,
Calculating logic cell information relating to an arrangement position and a voltage range of the logic cell from layout data of the semiconductor integrated circuit;
For each operating voltage value applied to the logic cell, refer to the voltage condition parameter storage unit in which through information regarding the slew rate of the logic cell and load information regarding the wiring resistance and wiring capacitance of the logic cell are stored. Calculating the delay for each voltage value and the variation value of the delay, and generating a cell library storing the delay and the variation value;
Calculating the variation value for each logic cell with reference to the logic cell information and the cell library;
Analyzing the delay of the logic cell with reference to the variation value for each logic cell;
A timing analysis method characterized by comprising:   The timing analysis method according to claim 1, wherein the cell library manages the delay and the variation value by a table or a function.   The timing analysis method according to claim 1, wherein the variation value for each logic cell is calculated using a Monte Carlo method with reference to the logic cell information and the cell library. In a timing analysis device that analyzes a delay of a signal path of a semiconductor integrated circuit including a logic cell,
A layout data storage unit for holding layout data of the semiconductor integrated circuit;
For each operating voltage value applied to the logic cell, a voltage condition parameter storage unit storing slew information relating to the slew rate of the logic cell and load information relating to wiring resistance and wiring capacitance of the logic cell;
A cell library in which the delay for each operating voltage value and a variation value of the delay are stored;
Referring to the layout data storage unit, a logic cell information calculation unit for calculating logic cell information related to the arrangement position and voltage range of the logic cell;
A cell library generation unit that generates the cell library with reference to the voltage condition parameter storage unit;
Referring to the logic cell information and the cell library, a timing variation value calculating unit for calculating the variation value for each logic cell;
A timing analysis unit for analyzing the delay of the logic cell with reference to the variation value for each logic cell;
A timing analysis apparatus comprising:   The timing analysis apparatus according to claim 4, wherein the cell library manages the delay and the variation value by a table or a function.   6. The timing analysis apparatus according to claim 4, wherein the variation value for each logic cell is calculated using a Monte Carlo method with reference to the logic cell information and the cell library.   For each operating voltage value applied to the logic cell of the semiconductor integrated circuit, refer to the voltage condition parameter storage unit in which the slew information regarding the slew rate of the logic cell and the load information regarding the wiring resistance and wiring capacitance of the logic cell are stored. A cell library in which the delay and the variation value of the delay are calculated for each operating voltage value and the delay and the variation value are stored.

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