JP2008224400A - Semiconductor testing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor testing apparatus capable of reducing the footprint of the semiconductor testing apparatus inside a semiconductor clean area, and thereby, reducing installation cost and device testing cost and time that accompany installation. <P>SOLUTION: The semiconductor testing apparatus is provided with a first main frame 12A, arranged in a clean room and having a function other than those of a pattern generation section and a fail determination section 122; a second main frame 12B arranged outside the clean room and having the pattern generation section and the determination section 122; and a digital transmission line 132 of high-speed and low loss for performing signal transmission between a test head 11 and the first and second main frames 12A, 12B. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multi-pin semiconductor test apparatus for testing a large-scale LSI or the like such as a memory tester.

  FIG. 2 is a block diagram showing the configuration of a large-scale LSI tester for memory as an example of a conventional semiconductor test apparatus. The test head 1, the main frame 2, and power / signal wirings 31, 32 connecting the both and the cooling water pipe 4 are configured. The test head 1 stores a card for interfacing with a device under test (hereinafter referred to as a DUT (Device Under Test)) for measuring an LSI. The main frame 2 includes a tester body 21 having a pattern generation unit (ALPG) and a tester control unit (hereinafter referred to as TSC; TSC: Tester Controller) for measuring the DUT, and a fail determination unit that performs pass / fail determination from the test result. In addition to the fail memory 22 that constitutes, the water cooling control device 23 that cools the test head 1 with water via the cooling water pipe 4, the power supply device that generates power to be supplied to the test head 1, and the test program execution and test results Is composed of a workstation constituting the operation terminal 5 for displaying / storing.

  In the apparatus of FIG. 2, the pattern generation unit in the main frame 2 supplies a test pattern to the test head 1, the test head 1 applies the test pattern to the DUT, and based on the response signal read from the DUT, The fail memory 22 performs pass / fail determination.

  Prior art documents related to semiconductor test equipment include the following.

Japanese Patent Laid-Open No. 10-142298

  In general, the time required for signal transmission depends on the length of the communication line (approximately 5 to 10 ns / m). For example, when the distance is 1 km, 5 to 10 μs is required for one way. In the conventional apparatus shown in FIG. 2, the signal between the test head 1 and the main frame 2 is quite high speed of several hundred Mbps (megabit second) or more. It was necessary to reduce the distance, and as a result, both had to be installed in a clean room.

Since the conventional LSI tester is originally a huge device, the area occupied by each device tends to increase. In particular, because most of the semiconductor testers are installed in the clean room of a semiconductor factory due to the nature of the equipment, the installation area is limited. There was a problem that the cost and test time increased.

  SUMMARY OF THE INVENTION The present invention is intended to solve such problems, and a semiconductor that can reduce the occupation area of a semiconductor test apparatus in a semiconductor clean area, thereby reducing the installation cost and the associated device test cost and test time. An object is to provide a test apparatus.

In order to achieve such a problem, a semiconductor test apparatus according to the invention described in claim 1 is provided.
A pattern generator in the main frame supplies a test pattern to the test head, the test head applies the test pattern to the device under test, and a fail determination unit in the main frame is based on the response of the device under test. In semiconductor test equipment that performs pass / fail judgments,
A first main frame that is disposed in a clean room and has a function other than the pattern generation unit and the fail determination unit in the main frame;
A second main frame disposed outside the clean room and having the pattern generation unit and the fail determination unit;
And a high-speed and low-loss digital transmission line that performs signal transmission between the test head and the first and second main frames.

The invention according to claim 2
The semiconductor test apparatus according to claim 1,
The digital transmission path is composed of an optical fiber.

The invention described in claim 3
The semiconductor test apparatus according to claim 1 or 2,
The digital transmission path performs the signal transmission by a serial transmission method.

The invention according to claim 4
The semiconductor test apparatus according to claim 1 or 2,
The digital transmission path performs signal transmission with the test head by a packet communication method in which at least a plurality of instructions and a plurality of execution results are collected and communicated in packets.

The invention according to claim 5
The semiconductor test apparatus according to claim 1 or 2,
The digital transmission line performs signal transmission by a wavelength division multiplexing transmission system.

The invention described in claim 6
The semiconductor test apparatus according to any one of claims 1 to 5,
The first main frame and the second main frame include operation terminals,
At least one of the operation terminals includes a storage device or a terminal to which the storage device can be connected.

The invention described in claim 7
The semiconductor test apparatus according to claim 6,
When each operation terminal includes the storage device,
The operation terminals share information via a dedicated communication line or a general-purpose network.

The invention described in claim 8
The semiconductor test apparatus according to claim 1,
The digital transmission path is configured by wireless communication.

The invention according to claim 9
The semiconductor test apparatus according to claim 1, wherein:
The fail determination unit includes a fail memory.

  As is apparent from the above description, according to the present invention, the pattern generation unit in the in-frame supplies the test pattern to the test head, the test head applies the test pattern to the device under test, and the main pattern In a semiconductor test apparatus in which a fail determination unit in a frame performs a pass / fail determination based on a response of the device under test, the fail determination unit is disposed in a clean room and has functions other than the pattern generation unit and the fail determination unit in the main frame. A signal between the first main frame having the first main frame, the second main frame disposed outside the clean room and having the pattern generation unit and the fail determination unit, and the test head and the first and second main frames. High-speed, low-loss digital transmission line for transmission It is possible to provide a semiconductor testing apparatus having a reduced occupied area of the conductor test device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing the configuration of a memory tester as an example of a semiconductor test apparatus according to an embodiment of the present invention.

The test head 11 and the first main frame 12A are arranged in the clean area (area inside the clean room), and the second main frame 12B is arranged in the external area (area outside the clean room). Functions are assigned to the first main frame 12A and the second main frame 12B so that the main frame 2 of FIG.

The test head 11 houses a card that interfaces with the DUT for measuring the LSI that is the DUT.

The first main frame 12A is a collection of functions that are advantageous in terms of system configuration when installed in the vicinity of the test head 11 in the main frame 2 of FIG. 2, and is a workstation constituting the first operation terminal 15A. In addition to the water cooling control device 123, the first tester main body 121A includes a portion that requires wiring for analog signals, such as the aforementioned power supply device, TSC1 that is a part of the TSC, and an alarm device. It does not include parts that require digital signal wiring, such as pattern generators and fail determination units. The water cooling control device 123 cools the test head 11 with water via the cooling water pipe 14. Normally, water pipes are provided in the clean room, and these can be utilized. Therefore, by installing the water cooling control device 123 in the clean room, an increase in piping cost can be prevented. The power supply device generates power to be supplied to the test head 11.

The second main frame 12B is a portion of the main frame 2 shown in FIG. 2 that is not required to be installed in the vicinity of the test head 11 by a high-speed and low-loss digital transmission path, which will be described later. 2 has a workstation constituting the operation terminal 15B. In addition, the second tester main body 121B includes a pattern generator (ALPG) for measuring the DUT and a part TSC2 of the TSC that is an interface device with the operation terminal 15B. A fail memory 122 constituting a fail determination unit is included.

The power supply / alarm / analog signal wiring 131 is a metal wiring that may cause problems such as loss in the characteristics of the LSI tester unless it is installed in the immediate vicinity of the test head 11. In this case, an alarm signal line to the protection device for shutting down the power supply is included. If a DC measurement module or the like is installed outside the test head 11 due to the configuration of the test head 11, a signal line for measurement analog measurement may be added to the signal line of the signal wiring 131. Further, if possible, a power supply device or an alarm device may be built in the test head 11.

The high-speed low-loss signal wiring 132 is connected between the test head 11, the main frame 12A (connected to the tester main body 121A) and 12B (connected to the tester main body 121B and the fail memory 122), the tester main body 121A, the operation terminal 15A, and the star main body 121B. This is a high-speed and low-loss digital signal wiring for connecting the operation terminals 15B. For example, when a signal is transmitted by a single mode fiber (SMF) as the high-speed low-loss signal wiring 132, a loss of about 0.2 dB / km in a 1.55 μm band with a small chromatic dispersion and a few Gbps. Signal transmission is possible at a transmission rate. However, transmission lines other than optical fibers are possible if the wiring has a sufficiently low loss.

The data communication line 133 is a dedicated communication path that connects the operation terminal 15A and the operation terminal 15B. However, when already laid, this may be replaced with a general-purpose network system line 134.

The operation of the semiconductor test apparatus configured as shown in FIG. 1 will now be described.
The signal transmission between the test head 11 and the second tester main body 121B by the high-speed and low-loss signal wiring 132 requires the following measures in order to prevent an increase in test time due to an increase in communication time due to the physical distance. It is.

That is, in the case of a handshake type communication signal such as a command signal for controlling the test head, a packet communication method is used in which a plurality of command signals (commands) and readback signals (execution results) are communicated in one packet. As a result, the communication time can be shortened.

Also, for high-speed and large-capacity signals such as pattern data and fail data, the influence of the test time due to the communication path length can be reduced by pipeline processing or the like.

In addition, as a transmission method, the number of signal lines is reduced as much as possible by fully utilizing the transmission bandwidth of the communication line by technologies such as high-speed serial communication and wavelength multiplexing, and the installation labor and installation space when extending the signal line are reduced. Can be reduced.

The operation terminal 15 </ b> A performs a test and displays a test result from the vicinity of the test head 11 as an operation end. The operation terminal 15B as a main body stores a test program and saves test results.

  For debugging, the operation terminal 15B may be provided with an operation / display terminal, and the operation terminal 15A may be provided with a storage device for storage. However, since the operation terminals 15A and 15B are for controlling the same LSI tester, it is necessary to share the information of the LSI tester to be controlled. For this purpose, the operation terminals 15A and 15B are connected by a data communication line 133 and share information such as screen display, measurement status, and DUT pass / fail determination result.

According to the semiconductor test apparatus configured as described above, a large-scale pattern generator, fail determination unit, and the like can be obtained by transmitting a signal between the second main frame 12B and the tester head 11 through the high-speed low-loss signal wiring 132. The second main frame 12B configured by hardware can be physically moved away from the tester head 11. As a result, it is not necessary to install the second main frame 12B in the vicinity of the test head in the clean room. For example, when signal transmission of the high-speed and low-loss signal wiring 132 is performed using a single mode fiber (SMF), the mainframe 12B can be installed and operated at a location several tens to several kilometers away without using a relay device. It is.

  As a result, by occupying most of the mainframe that was previously installed in the clean room in an empty space outside the clean room, the area occupied by the LSI tester in the clean room is greatly reduced (about 1/2). be able to. In particular, it is effective because there are few restrictions on the installation when it is necessary to increase the number of installed LSI testers in order to increase the productivity of an existing semiconductor factory.

  In addition, noise in the clean room (due to air-cooled fines) can be reduced, and there are secondary effects that the tester can be easily installed in the clean room.

  Also, by using an optical fiber as a high-speed signal transmission means, the signal between the main frame and the test head is electrically insulated, making it less susceptible to noise and reducing the weight of the signal line. The stress on the wiring portion is reduced, and the test head can be easily handled. Furthermore, crosstalk characteristics between signal lines are improved.

  The main frame function is divided and placed inside and outside the clean room, and the second main frame 12B that exchanges digital signals is installed outside the clean room. The first main frame 12A that exchanges analog signals is installed inside the clean room. As a result, the loss of the power source, the voltage / current force / measurement minute signal does not increase, and the wiring cost does not increase. Also, the cost of water cooling piping does not increase. If all the mainframes are installed outside the clean room, these become major problems.

  In addition, since the information of the LSI tester that is the control target of the operation terminals 15A and 15B is shared, the entire state of the LSI tester can be always grasped even when the user is on either side of the main frames 12A and 12B. .

When the semiconductor test apparatus is other than the memory tester, the fail determination unit can omit the fail memory.

  Further, the operation terminals 15A and 15B may include a terminal to which the storage device can be connected instead of incorporating the storage device, and may be connected to the external storage device via the connection terminal.

  Further, the digital transmission path 132 may be configured by wireless communication (radio waves). In this case, since the wiring itself is lost, handling of the test head becomes very simple.

1 is a configuration block diagram showing a configuration of a memory tester in an example of a semiconductor test apparatus according to an embodiment of the present invention. It is a block diagram which shows the structure of the large sized memory tester as an example of the conventional semiconductor test apparatus.

Explanation of symbols

11 Test head 12A First main frame 12B Second main frame 15A, 15B Operation terminal 122 Fail judgment unit 132 Digital transmission line 133 Dedicated communication line 134 General-purpose network

Claims (9)

A pattern generator in the main frame supplies a test pattern to the test head, the test head applies the test pattern to the device under test, and a fail determination unit in the main frame is based on the response of the device under test. In semiconductor test equipment that performs pass / fail judgments,
A first main frame that is disposed in a clean room and has a function other than the pattern generation unit and the fail determination unit in the main frame;
A second main frame disposed outside the clean room and having the pattern generation unit and the fail determination unit;
A semiconductor test apparatus comprising: the test head; and a high-speed, low-loss digital transmission line that performs signal transmission between the first and second main frames. 2. The semiconductor test apparatus according to claim 1, wherein the digital transmission line is constituted by an optical fiber. The semiconductor test apparatus according to claim 1, wherein the digital transmission path performs the signal transmission by a serial transmission method. 3. The digital transmission path performs signal transmission with a packet communication method in which at least a plurality of instructions and a plurality of execution results are communicated together in a packet with the test head. Semiconductor test equipment. 3. The semiconductor test apparatus according to claim 1, wherein the digital transmission line performs signal transmission by a wavelength division multiplexing transmission system. The first main frame and the second main frame include operation terminals,
The semiconductor test apparatus according to claim 1, wherein at least one of the operation terminals includes a storage device or a terminal to which the storage device can be connected. When each operation terminal includes the storage device,
The semiconductor test apparatus according to claim 6, wherein the operation terminals share information via a dedicated communication line or a general-purpose network. 2. The semiconductor test apparatus according to claim 1, wherein the digital transmission path is configured by wireless communication. 9. The semiconductor test apparatus according to claim 1, wherein the fail determination unit includes a fail memory.

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