JP2008219964A - Power storage module - Google Patents
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- 210000004027 cell Anatomy 0.000 claims abstract description 214
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Abstract
Description
本発明は、電気二重層キャパシタ及び二次電池に代表される電源用蓄電セルを用いて構成される蓄電モジュールにおいて、各蓄電セルの電圧を均等化する方法及びその装置に関する。 The present invention relates to a method and an apparatus for equalizing the voltage of each power storage cell in a power storage module configured using a power storage cell represented by an electric double layer capacitor and a secondary battery.
キャパシタモジュールや二次電池モジュール等の蓄電モジュールは用途に応じた所望の電圧及び容量を実現するために複数個のセルを直列及び並列に接続して構成されている。
上述した蓄電モジュールにおいては繰り返し充放電を行ううちに、各セルの容量、内部抵抗、環境温度、自己放電率等のばらつきに起因するセル電圧のばらつきが発生する。そして、ばらつきが発生すると電圧の高くなったセルの劣化は加速され、最終的にそのセルは過充電及び過放電状態に陥り蓄電モジュール全体の寿命を著しく短縮させてしまう。
上述したモジュール内の各セルの電圧を均等化し、モジュールとしての劣化を防ぐ手法が種々提案されている。均等化手法の代表的なものとして、バイパス回路方式、インダクタを用いた均等化方式、トランスを用いた均等化方式、コンデンサを用いた均等化方式等が考案されている。
A power storage module such as a capacitor module or a secondary battery module is configured by connecting a plurality of cells in series and in parallel in order to achieve a desired voltage and capacity according to the application.
In the above-described power storage module, variations in cell voltage due to variations in the capacity, internal resistance, environmental temperature, self-discharge rate, etc. of each cell occur during repeated charge / discharge. When the variation occurs, the deterioration of the cell having a high voltage is accelerated, and eventually the cell falls into an overcharge and overdischarge state, thereby significantly shortening the life of the entire power storage module.
Various methods have been proposed for equalizing the voltages of the cells in the module and preventing deterioration as a module. As a typical equalization method, a bypass circuit method, an equalization method using an inductor, an equalization method using a transformer, an equalization method using a capacitor, and the like have been devised.
図1に示す回路は直列/並列切り替え式均等化機能付き蓄電モジュールであり、このモジュールの構成は3直列/3並列である。B1A〜B4A、B1B〜B3B、B0C〜B3Cはセル、Sa1〜Sa8、Sb1〜Sb8は半導体スイッチを示しており、Sa系統とSb系統で示される2系統の半導体スイッチをドライバを用いて交互にオン/オフすることにより図2と図3に示すように、モジュール内において並列接続されるセルの組み合わせは切り替えられ、モジュール内の各セルはそれぞれの間において相互充放電を行いセル電圧を均等化することが可能である。 The circuit shown in FIG. 1 is a power storage module with a serial / parallel switching type equalization function, and the configuration of this module is 3 series / 3 parallel. B1A to B4A, B1B to B3B, B0C to B3C are cells, Sa1 to Sa8, Sb1 to Sb8 are semiconductor switches, and two semiconductor switches indicated by the Sa system and Sb system are alternately turned on using a driver. By turning off / off, the combination of cells connected in parallel in the module is switched as shown in FIG. 2 and FIG. 3, and the cells in the module are mutually charged and discharged to equalize the cell voltage. It is possible.
しかしながら上述の回路による場合、図2においてはB4AとB0C、図3においてはB1AとB3Cのように、それぞれの接続状態において電気的に開放状態となるセルが存在するため、開放状態となる期間においてはそれらのセルは使用されないためセルの使用率は低くなる。 However, in the case of the above-described circuit, there are cells that are electrically open in each connection state, such as B4A and B0C in FIG. 2 and B1A and B3C in FIG. Since those cells are not used, the usage rate of the cells is low.
また上述のスイッチのオン/オフ動作を行う場合、Sa系統とSb系統の両方がオンするとセルがショート状態に陥ってしまうので、両系統のスイッチが同時にオンしないように図4中のt2およびt4に示すように両系統のスイッチ駆動信号が共にオフとなるデッドタイムを設ける必要がある。 Further, when the above-described switch on / off operation is performed, if both the Sa system and the Sb system are turned on, the cell falls into a short-circuit state. Therefore, t2 and t4 in FIG. As shown in FIG. 2, it is necessary to provide a dead time during which both switch drive signals of both systems are turned off.
このようなスイッチ駆動制御を行った場合、図2に示すSa系統オン/Sb系統オフの状態と図3に示すSa系統オフ/Sb系統オンの状態以外にデッドタイム時(t2およびt4)において図5に示す両系統のスイッチがオフとなる接続状態が存在する。図2と図3の状態においては3直列/3並列の構成であるが、図5の状態においては1並列(その容量はx)の3直列構成となる。この状態においてはB1A〜B4AとB0C〜B3Cが切り離されており、蓄電モジュールに流れる電流はB1B〜B3Bに集中するため、B1B〜B3Bのセルにストレスがかかってしまう。またセルの容量に対する電流の比が大きくなるため、セルの内部抵抗に起因する電圧降下(IRドロップ)も大きくなってしまう。このIRドロップは接続状態を切り替える度に発生するため、接続状態の切り替え周期に応じた大きなノイズが発生することになる。 When such switch drive control is performed, there is a diagram at the time of dead time (t2 and t4) in addition to the Sa system on / Sb system off state shown in FIG. 2 and the Sa system off / Sb system on state shown in FIG. There exists a connection state in which the switches of both systems shown in FIG. 2 and 3, the configuration is 3 series / 3 parallel, but in the state of FIG. 5, the configuration is 1 parallel (capacity is x). In this state, B1A to B4A and B0C to B3C are disconnected, and the current flowing through the power storage module is concentrated on B1B to B3B, so that the cells B1B to B3B are stressed. Further, since the ratio of the current to the cell capacity increases, the voltage drop (IR drop) due to the internal resistance of the cell also increases. Since this IR drop occurs every time the connection state is switched, a large noise is generated according to the switching cycle of the connection state.
上述のスイッチオン/オフ動作を行う場合、並列に接続されるセルとセルの電圧差が大きな場合、セル間に大きな横流れ電流が流れてセルやスイッチを損傷してしまう恐れがある。例えば、二つのセルが並列に接続された状態の等価回路を示した図6の場合、電圧がBaとBbのセルaとセルbの間にはセルの内部抵抗ra、rbとスイッチのオン抵抗rA、rBにより制限される横流れ電流I=(Ba―Bb)/(ra+rb+rA+rB)が流れる。 When the above-described switch on / off operation is performed, if the voltage difference between the cells connected in parallel is large, a large lateral current may flow between the cells, which may damage the cells and the switches. For example, in the case of FIG. 6 showing an equivalent circuit in which two cells are connected in parallel, the internal resistances ra and rb of the cell and the on-resistance of the switch are between the cells a and b whose voltages are Ba and Bb. A transverse current I = (Ba−Bb) / (ra + rb + rA + rB) limited by rA and rB flows.
本発明に係る蓄電モジュールは、n個(nは2以上の整数)の蓄電セル及び/又は蓄電セル群を直列にしたm個の直列回路と、n−1個の蓄電セル及び蓄電セル群を直列にしたm個又はm±1個の複数個(ただし並列数が4L−2個の場合は除く。Lは自然数)の直列回路をそれぞれ交互に並列接続して構成したモジュールであり、各直列回路のセル及びセル群を異なる直列回路のセル及びセル群とを並列接続させる第1の接続状態と、前記第1の並列状態とは異なる組み合わせで各直列回路のセル及びセル群を異なる直列回路のセル及びセル群とを並列接続させる第2の接続状態を切り替えるスイッチ群を備え、前記の第1と第2の接続状態を繰り返し切り替えることが出来ることを特徴とする。 The power storage module according to the present invention includes n (n is an integer greater than or equal to 2) power storage cells and / or power storage cell groups, m serial circuits, and (n-1) power storage cells and power storage cell groups. This is a module that consists of m or m ± 1 series (except when the number of parallels is 4L-2, except that L is a natural number) in series connected alternately in parallel. A first connection state in which cells and cell groups in a circuit are connected in parallel to cells and cell groups in different series circuits, and a series circuit in which cells and cell groups in each series circuit are different in a combination different from the first parallel state A switch group for switching a second connection state that connects the cells and the cell group in parallel, and the first and second connection states can be switched repeatedly.
上記において、第1の接続状態と第2の接続状態との間の切り替え前後においてモジュールを構成する各並列回路の合成容量値が変化しないよう、前記蓄電セル及び/又は蓄電セル群の容量値を選択することが望ましい。 In the above, the capacity value of the storage cell and / or storage cell group is set so that the combined capacity value of each parallel circuit constituting the module does not change before and after switching between the first connection state and the second connection state. It is desirable to choose.
前記蓄電セルはキャパシタ、二次電池、あるいはキャパシタと二次電池を混在させたハイブリッド型とすることができる。この場合、いずれの並列回路においてもその並列回路を構成するキャパシタセルと二次電池セルの容量比及び総容量が等しくなることが望ましい。 The storage cell may be a capacitor, a secondary battery, or a hybrid type in which a capacitor and a secondary battery are mixed. In this case, it is desirable that the capacity ratio and the total capacity of the capacitor cell and the secondary battery cell constituting the parallel circuit are equal in any parallel circuit.
前記スイッチ群は、半導体スイッチから構成されるもの、あるいは機械式スイッチから構成されるものとすることができる。 The switch group can be composed of a semiconductor switch or a mechanical switch.
前記蓄電モジュールにおいて、蓄電モジュールの接続状態を切り替える際に少なくとも2つ以上の直列回路が並列に接続された状態を維持するようにスイッチ群の駆動タイミングをずらしたスイッチ駆動手段を備えるようにすることができる。 The power storage module includes switch drive means that shifts the drive timing of the switch group so as to maintain a state in which at least two or more series circuits are connected in parallel when switching the connection state of the power storage modules. Can do.
さらに、本発明に係る蓄電モジュールは、n個(nは2以上の整数)の蓄電セル及び/又は蓄電セル群を直列にしたm個の直列回路と、n−1個の蓄電セル及び蓄電セル群を直列にしたm個又はm±1個の複数個(ただし並列数が4L−2個の場合は除く。Lは自然数)の直列回路をそれぞれ交互に並列接続して構成したモジュールであり、各直列回路のセル及びセル群を異なる直列回路のセル及びセル群とを並列接続させる第1の接続状態と、前記第1の並列状態とは異なる組み合わせで各直列回路のセル及びセル群を異なる直列回路のセル及びセル群とを並列接続させる第2の接続状態を切り替えるスイッチ群を備え、前記の第1と第2の接続状態を繰り返し切り替えることが出来るよう前記スイッチ群を切り替えるスイッチ制御手段と、各蓄電セルの電圧を検出する電圧検出手段と、前記電圧検出回路からの電圧の検出結果に基づいて、前記スイッチ制御手段の動作を制御する制御手段を含むことを特徴とする。 Furthermore, the power storage module according to the present invention includes n (n is an integer greater than or equal to 2) power storage cells and / or power storage cell groups, m serial circuits, and (n-1) power storage cells and power storage cells. A module composed of m or m ± 1 groups (except when the number of parallels is 4L-2, where L is a natural number) series circuits alternately connected in parallel. A first connection state in which cells and cell groups in each series circuit are connected in parallel to cells and cell groups in different series circuits, and cells and cell groups in each series circuit are different in a combination different from the first parallel state. A switch control means for switching the switch group so that the first connection state and the second connection state can be repeatedly switched, comprising a switch group for switching a second connection state for connecting cells and cell groups of a series circuit in parallel; Voltage detecting means for detecting the voltage of each storage cell, based on a detection result of the voltage from the voltage detection circuit, it characterized in that it comprises a control means for controlling the operation of said switch control means.
上述の本発明の蓄電セルモジュールによれば、電気エネルギー貯蔵を目的とした電源用蓄電セルを複数個直列及び並列に接続して構成された蓄電モジュール内の各セルをFET、サイリスタ、フォトMOSリレー等の半導体スイッチ(以下、「半導体スイッチ」という)を用いて均等化する方法であって、蓄電モジュール内において直列及び並列接続されるセルの組み合わせを半導体スイッチを用いて切り替えることにより蓄電モジュール内の各セル間で相互充放電を行い、各セル電圧を均等化することができる。 According to the above-described power storage cell module of the present invention, each cell in the power storage module configured by connecting a plurality of power storage cells for power storage purpose in series and in parallel is connected to an FET, a thyristor, and a photo MOS relay. Is a method of equalization using a semiconductor switch (hereinafter referred to as “semiconductor switch”), and by switching a combination of cells connected in series and in parallel in a power storage module using a semiconductor switch, Mutual charge / discharge can be performed between the cells to equalize the cell voltages.
さらに、本発明に係る蓄電モジュールは、二次電池セルと電気エネルギー貯蔵を目的とした電源用キャパシタセルから成る蓄電モジュール内の各セル電圧を半導体スイッチを用いて均等化する蓄電モジュールであって、蓄電モジュール内において直列及び並列接続されるセルの組み合わせを半導体スイッチを用いて切り替えることにより蓄電モジュール内の各セル間で相互充放電を行い、各セル電圧を均等化する蓄電モジュールであり、2つの接続状態のうちいずれの接続状態においてもモジュール内のいずれの並列回路においてもその並列回路を構成するキャパシタセルと二次電池セルの容量比及び総容量が等しい蓄電モジュールである。 Furthermore, the power storage module according to the present invention is a power storage module that equalizes each cell voltage in a power storage module consisting of a secondary battery cell and a power source capacitor cell for electrical energy storage using a semiconductor switch, A power storage module that performs mutual charge / discharge between cells in a power storage module by switching a combination of cells connected in series and in parallel in the power storage module using a semiconductor switch, and equalizes each cell voltage. It is a power storage module in which the capacity ratio and the total capacity of the capacitor cell and the secondary battery cell constituting the parallel circuit are equal in any of the connected states in any of the connected states.
この蓄電モジュールによれば、蓄電モジュール内における各セルの直列及び並列接続される組み合わせは2系統の半導体スイッチにより切り替えられ、各セルはいずれかのセルを介して間接的に全てのセルに並列接続されることになる。並列接続されるセル間に電圧ばらつきが生じている場合、互いのセル間において相互充放電が行われ、電圧ばらつきは均等化される。また、2つの接続状態のうちいずれの接続状態においてもモジュール内の全ての並列段が二次電池セルとキャパシタセルの両方を含むため、二次電池セルとキャパシタセルを並列に接続したハイブリッド蓄電モジュールを構成することが可能である。なお、上記各並列段において、いずれの並列段においてもその並列段を構成するキャパシタセルと二次電池セルの容量比及び総容量が等しいこととする。 According to this power storage module, combinations of cells connected in series and in parallel in the power storage module are switched by two systems of semiconductor switches, and each cell is indirectly connected in parallel to all cells via one of the cells. Will be. When voltage variation occurs between cells connected in parallel, mutual charge / discharge is performed between the cells, and the voltage variation is equalized. Moreover, since all the parallel stages in the module include both the secondary battery cell and the capacitor cell in any of the two connection states, the hybrid power storage module in which the secondary battery cell and the capacitor cell are connected in parallel Can be configured. In each of the parallel stages, the capacity ratio and the total capacity of the capacitor cell and the secondary battery cell constituting the parallel stage are equal in any parallel stage.
本発明は前記蓄電モジュールの接続状態を切り替える際に少なくとも2つ以上の直列回路が並列に接続された状態を維持するようにスイッチ群の駆動タイミングをずらすことにより、蓄電モジュール内のある直列回路に電流が集中するのを防ぐことができる。これによりセルにかかるストレスを低減し、且つ、セルの内部抵抗に起因するIRドロップを小さくすることにより、接続状態を切り替える際に発生するノイズを低減することが可能となる。 According to the present invention, when the connection state of the power storage module is switched, the drive timing of the switch group is shifted so as to maintain a state where at least two series circuits are connected in parallel. Current concentration can be prevented. As a result, it is possible to reduce the stress applied to the cell and reduce the IR drop caused by the internal resistance of the cell, thereby reducing the noise generated when the connection state is switched.
また本発明は、各蓄電セルの電圧を計測する電圧検出回路からの電圧の検出結果に基づいて、前記スイッチ群への入力信号を制御することにより、蓄電モジュール内の各セル間に流れる横流れ電流を制御することが可能となる。 The present invention also provides a lateral flow current that flows between cells in a power storage module by controlling an input signal to the switch group based on a voltage detection result from a voltage detection circuit that measures the voltage of each power storage cell. Can be controlled.
また本発明は、蓄電モジュールを構成する半導体スイッチのうち、いずれかの1つの半導体スイッチがオープン故障しても均等化機能を維持することを特徴とする。前記蓄電モジュールにおいて蓄電モジュール内のある半導体スイッチがオープン故障した場合、その半導体スイッチを介して並列接続されるセル間においては相互充放電による均等化は行えない。しかし別系統のスイッチ動作時には上記セルは別のセルに並列接続されるため相互充放電による均等化が可能となる。 Further, the present invention is characterized in that the equalization function is maintained even if any one of the semiconductor switches constituting the power storage module is opened. When a semiconductor switch in the power storage module has an open failure in the power storage module, equalization by mutual charge / discharge cannot be performed between cells connected in parallel via the semiconductor switch. However, since the above cells are connected in parallel to another cell during switching operation of another system, equalization by mutual charge / discharge is possible.
さらに、本発明は、蓄電モジュール内のいずれか1つのセルがオープン故障しても均等化機能を維持することを特徴とする。前記蓄電モジュールにおいて蓄電モジュール内のあるセルがオープン故障した場合、そのセルを含む並列段においてセルの並列接続数は減少するが並列接続内における相互充放電は可能であり、また半導体スイッチにより直列/並列接続が切り替えられた後においても相互充放電による均等化は可能である。 Furthermore, the present invention is characterized in that the equalization function is maintained even if any one cell in the power storage module is open. When a certain cell in the power storage module has an open failure in the power storage module, the number of parallel connections of the cells in the parallel stage including the cell is reduced, but mutual charge / discharge in the parallel connection is possible. Even after the parallel connection is switched, equalization by mutual charge / discharge is possible.
電気エネルギー貯蔵を目的とした電源用セルを複数個直列及び並列に接続して構成された蓄電モジュール内の各セルを半導体スイッチのみを用いて均等化することが可能である。 It is possible to equalize each cell in a power storage module configured by connecting a plurality of power source cells for electrical energy storage in series and in parallel using only a semiconductor switch.
接続状態に応じて回路から開放状態となるセルが存在しないため、セルの使用率を高くすることが可能となる。また、開放状態となるセルが存在するような回路構成の場合と比較して、セル数やスイッチ数を削減することが出来る。 Since there is no cell that is open from the circuit according to the connection state, the cell usage rate can be increased. In addition, the number of cells and the number of switches can be reduced as compared with the case of a circuit configuration in which there are open cells.
接続状態を切り替える際においても1並列構成の状態になることがないため、電流が集中することにより発生するセルへのストレスを軽減することが可能となる。また、電流の集中を防ぐことによりセルの内部抵抗に起因するIRドロップを小さくすることができるので、接続状態の切り替えの際に発生するノイズを低減することが可能となる。 Even when the connection state is switched, the state of one parallel configuration does not occur, so that it is possible to reduce the stress on the cell caused by the concentration of current. In addition, since the IR drop caused by the internal resistance of the cell can be reduced by preventing the current concentration, noise generated when switching the connection state can be reduced.
接続状態を切り替える際にセル間に流れる横流れ電流を制御することにより、電圧ばらつきの大きな状態においても接続状態の切り替えを行うことが可能となり、セルやスイッチの損傷を防止することができる。 By controlling the cross current flowing between the cells when switching the connection state, the connection state can be switched even in a state where the voltage variation is large, and damage to the cell and the switch can be prevented.
図7は本発明のセル電圧均等化回路の第1の実施形態を示す回路図である。これは、蓄電セルとしての二次電池セルを用い、3つの直列回路を並列に接続した2並列−3並列−2並列の並列段より構成される3直列構成である。B1A〜B2A、B1B〜B3B、B2C〜B3Cはセルであり、B1BとB3Bは容量が2xであるセルであり、他のセルの容量はxである。Sa1〜Sa6、Sb1〜Sb6は半導体スイッチを示す。Sa系統とSb系統で示される2系統の半導体スイッチをドライバを用いて交互にオン/オフすることによりモジュール内において並列接続されるセルの組み合わせは切り替えられ、モジュール内の各セルはそれぞれのセル間において相互充放電を行いセル電圧を均等化することが可能である。なお、ドライバを用いたオン/オフ動作は、一定周期でオンとオフを切り替えるよう動作させることができる他、経時変化や負荷変動などに応じてこの周期を変えるようにしてもよい。 FIG. 7 is a circuit diagram showing a first embodiment of the cell voltage equalizing circuit of the present invention. This is a three-series configuration composed of parallel stages of 2 parallels, 3 parallels, and 2 parallels, using secondary battery cells as power storage cells and connecting three series circuits in parallel. B1A to B2A, B1B to B3B, B2C to B3C are cells, B1B and B3B are cells having a capacity of 2x, and the capacity of other cells is x. Sa1 to Sa6 and Sb1 to Sb6 indicate semiconductor switches. The combination of cells connected in parallel in the module is switched by alternately turning on and off the two systems of semiconductor switches indicated by the Sa system and Sb system using a driver, and each cell in the module is connected between each cell. It is possible to equalize the cell voltage by performing mutual charging and discharging in FIG. The on / off operation using the driver can be switched between on and off at a constant cycle, and the cycle may be changed according to a change with time, a load variation, or the like.
図8にSa系統のスイッチがオン、Sb系統のスイッチがオフの状態の回路図を示す。この状態においてはB1AとB2BとB3C、B2AとB3B、B1BとB2Cがそれぞれ並列に接続されており、2並列−3並列−2並列の並列段より構成される3直列構成のモジュールを構成している。この接続状態においてはいずれの並列段の合成容量も3xであり等しい。並列接続されているセル間において電圧ばらつきが発生している場合はセル間で相互充放電が行われ、電圧ばらつきは解消される方向に向かう。 FIG. 8 is a circuit diagram showing a state where the Sa system switch is on and the Sb system switch is off. In this state, B1A and B2B and B3C, B2A and B3B, B1B and B2C are connected in parallel, and a three-series module composed of 2 parallels, 3 parallels, and 2 parallel stages is configured. Yes. In this connected state, the combined capacity of all the parallel stages is 3x and is equal. When voltage variation occurs between cells connected in parallel, mutual charge / discharge is performed between the cells, and the voltage variation is resolved.
図9にSa系統のスイッチがオフ、Sb系統のスイッチがオンの状態の回路図を示す。この状態においてはB1AとB1B、B2AとB2BとB2C、B3BとB3Cがそれぞれ並列に接続されており、2並列−3並列−2並列の並列段より構成される3直列構成のモジュールを構成している。この接続状態においてはいずれの並列段の合成容量も3xであり等しい。並列接続されているセル間において電圧ばらつきが発生している場合はセル間で相互充放電が行われ、電圧ばらつきは解消される方向に向かう。 FIG. 9 shows a circuit diagram in which the Sa system switch is off and the Sb system switch is on. In this state, B1A and B1B, B2A and B2B and B2C, B3B and B3C are connected in parallel, respectively, and a 3-series module composed of 2 parallel-3 parallel-2 parallel stages is configured. Yes. In this connected state, the combined capacity of all the parallel stages is 3x and is equal. When voltage variation occurs between cells connected in parallel, mutual charge / discharge is performed between the cells, and the voltage variation is resolved.
上述のスイッチのオンオフ動作の繰り返しにより、常に2並列−3並列−2並列の並列段より構成される3直列構成を維持しつつ、且つ、いずれの並列段の合成容量も等しい(3x)まま直列及び並列接続の組み合わせは切り替えられ、モジュール内の各セルはいずれかのセルを介して全てのセルに並列接続されることになり、並列接続されるセル間において相互充放電が行われ各セルの電圧は均等化される。 By repeating the on / off operation of the above-described switch, a three-series configuration composed of 2 parallel-3 parallel-2 parallel parallel stages is always maintained, and the combined capacity of all the parallel stages is the same (3x) in series. The combination of the parallel connection is switched, and each cell in the module is connected in parallel to all the cells via any one of the cells. Mutual charge / discharge is performed between the cells connected in parallel to each other. The voltage is equalized.
図10は本発明のセル電圧均等化回路の第1の実施形態において、4つの直列回路を並列に接続して構成される場合の回路図である。図11にSa系統のスイッチがオン、Sb系統のスイッチがオフの状態、図12にSa系統のスイッチがオフ、Sb系統のスイッチがオンの状態の回路図をそれぞれ示す。図13は本発明のセル電圧均等化回路の第1の実施形態において、5つの直列回路を並列に接続して構成される場合の回路図である。図14にSa系統のスイッチがオン、Sb系統のスイッチがオフの状態、図15にSa系統のスイッチがオフ、Sb系統のスイッチがオンの状態の回路図をそれぞれ示す。 FIG. 10 is a circuit diagram in the case where the cell voltage equalizing circuit according to the first embodiment of the present invention is configured by connecting four series circuits in parallel. FIG. 11 is a circuit diagram in which the Sa system switch is on and the Sb system switch is off, and FIG. 12 is a circuit diagram in which the Sa system switch is off and the Sb system switch is on. FIG. 13 is a circuit diagram in the case where the cell voltage equalization circuit according to the first embodiment of the present invention is configured by connecting five series circuits in parallel. FIG. 14 is a circuit diagram in which the Sa system switch is on and the Sb system switch is off, and FIG. 15 is a circuit diagram in which the Sa system switch is off and the Sb system switch is on.
いずれの構成のモジュールにおいても上述と同様のスイッチのオンオフ動作の繰り返しにより、常に同じ構成を維持しつつ、且つ、いずれの並列段の合成容量も等しいまま直列及び並列接続の組み合わせは切り替えられ、モジュール内の各セルはいずれかのセルを介して全てのセルに並列接続されることになり、並列接続されるセル間において相互充放電が行われ各セルの電圧は均等化される。 In any module, by repeating the same switch ON / OFF operation as described above, the combination of series and parallel connection is switched while maintaining the same structure at the same time, and the combined capacity of any parallel stage is the same. Each of the cells is connected in parallel to all the cells via any one of the cells, and mutual charging / discharging is performed between the cells connected in parallel to equalize the voltage of each cell.
上記の第1の実施形態の構成を一般化すると、n個(nは2以上の整数)の蓄電セル及び蓄電セル群を直列にしたm個の直列回路と、n−1個の蓄電セル及び蓄電セル群を直列にしたm個又はm±1個の複数個(ただし並列数が4L−2個の場合は除く。Lは自然数)の直列回路をそれぞれ交互に並列接続したものということができる。例えば、図7の回路はn=3、m=1の場合の例であり、図10の回路はn=3、m=2の場合の例であり、図13はn=3、m=3の場合の例である。 Generalizing the configuration of the first embodiment described above, n (n is an integer of 2 or more) power storage cells and m power storage cell groups in series, m-1 series power storage cells, It can be said that a plurality of m or m ± 1 series circuits (with the exception of a parallel number of 4L-2, where L is a natural number) are alternately connected in parallel. . For example, the circuit of FIG. 7 is an example when n = 3 and m = 1, the circuit of FIG. 10 is an example when n = 3 and m = 2, and FIG. 13 shows n = 3 and m = 3. This is an example.
図16は本発明のセル電圧均等化回路の第2の実施形態を示す回路図である。これは、蓄電セルとしてキャパシタセルと二次電池セルが混在するハイブリッド型であり、二次電池セル×2セルとキャパシタセル×1セルから成る並列段が3つ直列接続された構成である。B1A〜B2A、B1BとB3B、B2C〜B3Cは容量xの二次電池セル、C1B〜C3Bは容量yのキャパシタセル、Sa1〜Sa6、Sb1〜Sb6は半導体スイッチを示す。また、この例では、C1BとB1Bが一つのセル群、C3BとB3Bが一つのセル群となる。 FIG. 16 is a circuit diagram showing a second embodiment of the cell voltage equalizing circuit of the present invention. This is a hybrid type in which capacitor cells and secondary battery cells are mixed as power storage cells, and has a configuration in which three parallel stages of secondary battery cells × 2 cells and capacitor cells × 1 cell are connected in series. B1A to B2A, B1B and B3B, B2C to B3C are secondary battery cells having a capacity x, C1B to C3B are capacitor cells having a capacity y, and Sa1 to Sa6 and Sb1 to Sb6 are semiconductor switches. In this example, C1B and B1B are one cell group, and C3B and B3B are one cell group.
図16において、Sa系統とSb系統で示される2系統の半導体スイッチをドライバを用いて交互にオン/オフすることによりモジュール内において並列接続されるセルの組み合わせは切り替えられ、モジュール内の各セルはそれぞれのセル間において相互充放電を行いセル電圧を均等化することが可能である。なお、ドライバを用いたオン/オフ動作は、一定周期でオンとオフを切り替えるよう動作させることができる他、経時変化や負荷変動などに応じてこの周期を変えるようにしてもよい。 In FIG. 16, the combination of cells connected in parallel in the module is switched by alternately turning on / off the two systems of semiconductor switches represented by the Sa system and Sb system using a driver, and each cell in the module is It is possible to equalize cell voltages by performing mutual charging / discharging between cells. The on / off operation using the driver can be switched between on and off at a constant cycle, and the cycle may be changed according to a change with time, a load variation, or the like.
図17にSa系統のスイッチがオン、Sb系統のスイッチがオフの状態の回路図を示す。この状態においてはB1AとC2BとB3C、B2AとC3BとB3B、C1BとB1BとB2Cがそれぞれ並列に接続されており、いずれの並列段も二次電池セル×2セルとキャパシタセル×1セルから成る3直列構成である。この接続状態においてはいずれの並列段の合成容量も2x+yであり等しい。並列接続されているセル間において電圧ばらつきが発生している場合はセル間で相互充放電が行われ、電圧ばらつきは解消される方向に向かう。 FIG. 17 shows a circuit diagram in a state where the Sa system switch is on and the Sb system switch is off. In this state, B1A and C2B and B3C, B2A and C3B and B3B, and C1B, B1B and B2C are connected in parallel, respectively, and each parallel stage is composed of secondary battery cells × 2 cells and capacitor cells × 1 cell. 3 series configuration. In this connected state, the combined capacity of any parallel stage is 2x + y, which is equal. When voltage variation occurs between cells connected in parallel, mutual charge / discharge is performed between the cells, and the voltage variation is resolved.
図18にSa系統のスイッチがオフ、Sb系統のスイッチがオンの状態の回路図を示す。この状態においてはB1AとC1BとB1B、B2AとC2BとB2C、C3BとB3BとB3Cがそれぞれ並列に接続されており、いずれの並列段も二次電池セル×2セルとキャパシタセル×1セルから成る3直列構成である。この接続状態においてはいずれの並列段の合成容量も2x+yであり等しい。並列接続されているセル間において電圧ばらつきが発生している場合はセル間で相互充放電が行われ、電圧ばらつきは解消される方向に向かう。 FIG. 18 is a circuit diagram showing a state where the Sa system switch is off and the Sb system switch is on. In this state, B1A and C1B and B1B, B2A and C2B and B2C, and C3B, B3B, and B3C are connected in parallel, respectively, and each parallel stage is composed of secondary battery cells × 2 cells and capacitor cells × 1 cell. 3 series configuration. In this connected state, the combined capacity of any parallel stage is 2x + y, which is equal. When voltage variation occurs between cells connected in parallel, mutual charge / discharge is performed between the cells, and the voltage variation is resolved.
上述のスイッチのオンオフ動作の繰り返しにより、いずれの並列段も二次電池セル×2セルとキャパシタセル×1セルから成る3直列構成を維持しつつ、且つ、全ての並列段の合成容量は等しい(2x+y)まま直列及び並列接続の組み合わせは切り替えられ、モジュール内の各セルはいずれかのセルを介して全てのセルに並列接続されることになり、並列接続されるセル間において相互充放電が行われ各セルの電圧は均等化される。 By repeating the above-described switch ON / OFF operation, all the parallel stages maintain the three series configuration including the secondary battery cells × 2 cells and the capacitor cells × 1 cell, and the combined capacities of all the parallel stages are equal ( 2x + y) The combination of series and parallel connection is switched, and each cell in the module is connected in parallel to all cells via any cell, and mutual charge / discharge is performed between the cells connected in parallel. The voltage of each cell is equalized.
なお、図16の回路は、n個(nは2以上の整数)の蓄電セル及び蓄電セル群を直列にしたm個の直列回路と、n−1個の蓄電セル及び蓄電セル群を直列にしたm個又はm±1個の複数個(ただし並列数が4L−2個の場合は除く。Lは自然数)の直列回路をそれぞれ交互に並列接続するという条件を満たしていれば、図10や図13に示すようなより多くのセルを含む回路に容易に拡張することができる。 Note that the circuit of FIG. 16 includes m series circuits in which n (n is an integer of 2 or more) storage cells and storage cell groups are connected in series, and n−1 storage cells and storage cell groups are connected in series. As long as the condition that m or m ± 1 plural (where the parallel number is 4L-2, except that L is a natural number) series circuits are alternately connected in parallel is satisfied, FIG. It can be easily extended to a circuit including more cells as shown in FIG.
図19は本発明のスイッチ駆動制御方式の一実施形態を示す図である。蓄電モジュール内のスイッチ群をSa系統とSb系統に分類する他、B1A〜B2AとB1B〜B3Bを並列接続するスイッチ群をA系統、B1B〜B3BとB2C〜B3Cを並列接続するスイッチ群をB系統とする。蓄電モジュール内のスイッチ群は合計4系統に分類されている。そしてこれらのスイッチ群をドライバを用いて図20に示すタイミングチャートのように駆動する。このタイミングチャートに従ってスイッチ群を駆動させた場合、スイッチの駆動状態に応じて図21−1及び図21−2にC1〜C8で示すの8つの接続状態が存在する。 FIG. 19 is a diagram showing an embodiment of the switch drive control system of the present invention. In addition to classifying the switch group in the power storage module into the Sa system and the Sb system, the switch group that connects B1A to B2A and B1B to B3B in parallel is the A system, and the switch group that connects B1B to B3B and B2C to B3C in parallel is the B system And The switch group in the power storage module is classified into a total of four systems. These switch groups are driven using a driver as shown in the timing chart of FIG. When the switch group is driven according to this timing chart, there are eight connection states indicated by C1 to C8 in FIGS. 21-1 and 21-2 according to the drive state of the switch.
C1の接続状態ではa―A系統とa−B系統のスイッチ群が共にオンで、2並列−3並列−2並列の3直列構成であり、いずれの並列段の合成容量も3xであり等しい。次に、C1の状態からa−B系統のスイッチ群をオフにするとC2の接続状態へと移行する。この場合、上段と中段の合成容量は2xであり下段の合成容量は3xである。次に、C2の状態からb−B系統のスイッチ群をオンにするとC3の接続状態へと移行する。この場合、上段の合成容量は2x、中段の合成容量は3x、下段の合成容量は4xである。次に、C3の状態からa−A系統のスイッチ群をオフにするとC4の接続状態へと移行する。この場合、上段と中段の合成容量は2x、下段の合成容量は3xである。 In the connection state of C1, the switch groups of the aA system and the aB system are both turned on, and it has a 3 series configuration of 2 parallels-3 parallels-2 parallels, and the combined capacity of any parallel stage is 3x and equal. Next, when the switch group of the aB system is turned off from the state of C1, the state shifts to the connection state of C2. In this case, the combined capacity of the upper and middle stages is 2x, and the combined capacity of the lower stage is 3x. Next, when the switch group of the b-B system is turned on from the state of C2, the state shifts to the connection state of C3. In this case, the combined capacity of the upper stage is 2x, the combined capacity of the middle stage is 3x, and the combined capacity of the lower stage is 4x. Next, when the aA system switch group is turned off from the state of C3, the state shifts to the connection state of C4. In this case, the combined capacity of the upper and middle stages is 2x, and the combined capacity of the lower stage is 3x.
次に、C4の状態からb−A系統のスイッチ群をオンにするとC5の接続状態へと移行する。この場合、いずれの並列段の合成容量も3xであり等しい。次に、C5の状態からb−B系統のスイッチ群をオフにするとC6の接続状態へと移行する。この場合、上段の合成容量は3x、中段と下段の合成容量は2xである。次に、C6の状態からa−B系統のスイッチ群をオンにするとC7の接続状態へと移行する。この場合、上段の合成容量は4x、中段の合成容量は3x、下段の合成容量は2xである。次に、C7の状態からb−A系統のスイッチ群をオフにするとC8の接続状態へと移行する。この場合、上段の合成容量は3x、中段と下段の合成容量は2xである。次に、C8の状態からa−A系統のスイッチ群をオンにするとC1の接続状態へと再び戻る。 Next, when the b-A system switch group is turned on from the state of C4, the state shifts to the connection state of C5. In this case, the combined capacity of any parallel stage is 3x, which is equal. Next, when the switch group of the b-B system is turned off from the state of C5, the state shifts to the connection state of C6. In this case, the combined capacity of the upper stage is 3x, and the combined capacity of the middle stage and the lower stage is 2x. Next, when the switch group of the aB system is turned on from the state of C6, the state shifts to the connection state of C7. In this case, the combined capacity of the upper stage is 4x, the combined capacity of the middle stage is 3x, and the combined capacity of the lower stage is 2x. Next, when the b-A system switch group is turned off from the state of C7, the state shifts to the connection state of C8. In this case, the combined capacity of the upper stage is 3x, and the combined capacity of the middle stage and the lower stage is 2x. Next, when the aA system switch group is turned on from the state of C8, the state returns to the connection state of C1 again.
上述の図4のタイミングチャートを用いた場合、その期間t2において、前述のように3直列を構成する各1並列の合成容量がxとなる並列段が存在したが(図5参照)、上記の図20のタイミングチャートを用いた場合は図21のC1〜C8に示すように一連の接続状態切り替え動作の中で合成容量がxとなる並列段が存在しないことからセルにかかるストレスを低減することが可能となる。またセルに対する電流の大きさの比が図8の場合よりも小さいため、セルの内部抵抗に起因するIRドロップを小さくすることができるので、接続状態の切り替えの際に発生するノイズを低減することが可能となる。 When the above timing chart of FIG. 4 is used, in the period t2, as described above, there are parallel stages in which each of the three parallel combined capacities constituting x series is x (see FIG. 5). When the timing chart of FIG. 20 is used, as shown in C1 to C8 of FIG. 21, there is no parallel stage where the combined capacity is x in a series of connection state switching operations, so that the stress on the cell is reduced. Is possible. In addition, since the ratio of the magnitude of the current to the cell is smaller than in the case of FIG. 8, the IR drop caused by the internal resistance of the cell can be reduced, so that noise generated when switching the connection state is reduced. Is possible.
なお、図19、図20に示したスイッチ駆動制御方式は、図10や図13に示した回路にも適用できる。その場合は、例えば中央の直列回路よりも左側のスイッチ群をA系統、右側のスイッチ群をB系統というように分類すればよく、このようにすれば並列数が増えてもこのようにA系統、B系統という2系統について図19、図20に示したスイッチ駆動制御方式を適用できる。 Note that the switch drive control method shown in FIGS. 19 and 20 can also be applied to the circuits shown in FIGS. In that case, for example, the left switch group from the central series circuit may be classified as A system, and the right switch group may be classified as B system. The switch drive control system shown in FIG. 19 and FIG. 20 can be applied to the two systems called B system.
図22は図7に示した回路に、電圧検出回路、平均回路、減算回路、振幅調整回路を付加した実施形態を示しており、接続状態切り替えの際に並列に接続されるセル間に流れる横流れ電流を制御させる方法の一例である。 FIG. 22 shows an embodiment in which a voltage detection circuit, an average circuit, a subtraction circuit, and an amplitude adjustment circuit are added to the circuit shown in FIG. 7, and a lateral flow that flows between cells connected in parallel when the connection state is switched. It is an example of the method of controlling an electric current.
図22の回路は、前述の2並列−3並列−2並列の並列段より構成される3直列構成の蓄電モジュールであり、モジュール内の各セルは電圧検出回路及び平均回路に接続されており、電圧検出回路は各セル電圧に応じた電圧信号を出力し、平均回路は各セル電圧の平均電圧に応じた電圧信号を出力する。電圧検出回路及び平均回路からの出力信号は減算回路に入力され、各セル電圧とセル電圧の平均電圧との差、つまり電圧ばらつきに応じた電圧信号が減算回路から出力される。減算回路からの出力信号は振幅調整回路に入力され、振幅調整回路は半導体スイッチを駆動させるドライバの出力信号の振幅を制御する。 The circuit in FIG. 22 is a power storage module having a three-series configuration including the above-described two parallel-three parallel-parallel parallel stages, and each cell in the module is connected to a voltage detection circuit and an average circuit. The voltage detection circuit outputs a voltage signal corresponding to each cell voltage, and the averaging circuit outputs a voltage signal corresponding to the average voltage of each cell voltage. Output signals from the voltage detection circuit and the average circuit are input to the subtraction circuit, and a voltage signal corresponding to a difference between each cell voltage and the average voltage of the cell voltages, that is, a voltage variation is output from the subtraction circuit. The output signal from the subtraction circuit is input to the amplitude adjustment circuit, and the amplitude adjustment circuit controls the amplitude of the output signal of the driver that drives the semiconductor switch.
図23に示すように、半導体スイッチに流れる電流は半導体スイッチへの入力信号に依存する。つまり半導体スイッチへの入力信号を制御することにより、半導体スイッチに流れる電流を制御することができる。減算回路からの出力信号の大きさ、つまり各セル電圧のばらつき度合いに応じて半導体スイッチを駆動させるドライバの出力信号の振幅を調節することにより、半導体スイッチに流れる電流を制限する。以上の動作により、各セル間の電圧ばらつきが大きな場合は半導体スイッチに流れる横流れ電流を制御し、セルやスイッチが損傷するのを防ぐことが出来る。 As shown in FIG. 23, the current flowing through the semiconductor switch depends on the input signal to the semiconductor switch. That is, the current flowing through the semiconductor switch can be controlled by controlling the input signal to the semiconductor switch. The current flowing through the semiconductor switch is limited by adjusting the amplitude of the output signal of the driver that drives the semiconductor switch according to the magnitude of the output signal from the subtracting circuit, that is, the degree of variation of each cell voltage. With the above operation, when the voltage variation between the cells is large, the lateral current flowing through the semiconductor switch can be controlled to prevent the cell or the switch from being damaged.
本発明の蓄電モジュールにおいて用いられるセルは全て電気エネルギー貯蔵を目的とした電源用蓄電セルであり、複数個の蓄電セルを用いて蓄電モジュールを構成する。よってモジュール内のあるセルがオープン故障した場合やモジュール内のある半導体スイッチが故障した場合においても蓄電モジュールとしての機能は失われない。 All the cells used in the power storage module of the present invention are power storage cells for the purpose of storing electrical energy, and a plurality of power storage cells are used to form a power storage module. Therefore, even when a certain cell in the module has an open failure or a certain semiconductor switch in the module fails, the function as the power storage module is not lost.
本発明の蓄電モジュールを構成する半導体スイッチのうち、いずれかの1つの半導体スイッチがオープン故障した場合、その半導体スイッチを介して並列接続されるセル間では相互充放電による均等化は行えなくなる。しかし別系統のスイッチ動作時には上記セルは別のセルに並列接続されるため相互充放電による均等化が可能となる。ただし、2つ以上のスイッチが故障した場合などはモジュールから電気的に切り離されるセルが発生するケースがある。 If any one of the semiconductor switches constituting the power storage module of the present invention has an open failure, equalization by mutual charge / discharge cannot be performed between cells connected in parallel via the semiconductor switch. However, since the above cells are connected in parallel to another cell during switching operation of another system, equalization by mutual charge / discharge is possible. However, when two or more switches fail, a cell that is electrically disconnected from the module may occur.
図24は、蓄電モジュール内のあるセルがオープン故障した場合について説明するための図である。モジュール内のあるセルがオープン故障した場合であっても、並列状態を切り替えることによって、すべてのセルの均等化を行うことが可能である。 FIG. 24 is a diagram for describing a case where a certain cell in the power storage module has an open failure. Even if a certain cell in the module has an open failure, it is possible to equalize all the cells by switching the parallel state.
本発明の蓄電モジュールにおいて蓄電モジュール内のある1つのセルがオープン故障した場合、その故障したセルを含む並列段の合成容量は小さくなってしまう。しかし他のセルとの電気的な接続を阻害する故障ではないため、モジュール内の各セルは必ず1つ以上のその他のセルと並列接続されることになるので均等化機能は失われない。ただし、2つ以上のセルが故障した場合などは並列に接続される相手のいないセルが発生、もしくは故障セルのみにより構成される並列段などが発生するケースがある。 In the power storage module of the present invention, when one cell in the power storage module has an open failure, the combined capacity of the parallel stages including the failed cell becomes small. However, since this is not a failure that hinders electrical connection with other cells, each cell in the module is always connected in parallel with one or more other cells, so that the equalization function is not lost. However, when two or more cells have failed, there are cases in which there is a cell that does not have a partner connected in parallel, or a parallel stage that includes only failed cells.
図25乃至図26は、半導体スイッチがオープン故障した場合について説明するための図であり、図25はSa系統、図26はSb系統のあるスイッチが故障した場合を示す。いずれの場合においても接続状態を切り替えることにより、すべての蓄電セルの均等化を行うことが可能である。 FIGS. 25 to 26 are diagrams for explaining a case where a semiconductor switch has an open failure, in which FIG. 25 shows a case where a switch in the Sa system and FIG. In any case, it is possible to equalize all the storage cells by switching the connection state.
本発明の蓄電モジュールにおいて蓄電モジュール内のある1つの半導体スイッチがオープン故障した場合、その故障したスイッチを介して接続されるセルは均等化を行うことが出来ない。しかし別系統のスイッチ動作時には上記セルは別のセルに並列接続されるため相互充放電による均等化が可能となる。ただし、2つ以上のスイッチが故障した場合などはモジュールから電気的に切り離されるセルが発生するケースがある。 In the power storage module of the present invention, when one semiconductor switch in the power storage module has an open failure, cells connected through the failed switch cannot be equalized. However, since the above cells are connected in parallel to another cell during switching operation of another system, equalization by mutual charge / discharge is possible. However, when two or more switches fail, a cell that is electrically disconnected from the module may occur.
上記においてはセルという語句を用いて説明してきたが、単一のセルを意味する他に複数個のセルから構成されるセル群であっても適用可能である。
また上記においては半導体スイッチを用いることを前提として説明してきたが、図22に示す横流れ電流を制御させる方法以外においては、スイッチの切り替え周期を十分遅くした場合などにおいてはパワーリレー等の応答速度の遅い機械式スイッチを用いて均等化を行うことも可能である。
In the above description, the term “cell” has been used. However, the present invention can be applied to a cell group including a plurality of cells in addition to a single cell.
Although the above description has been made on the assumption that a semiconductor switch is used, except for the method of controlling the lateral flow current shown in FIG. 22, the response speed of a power relay or the like is reduced when the switch switching cycle is sufficiently slow. It is also possible to equalize using a slow mechanical switch.
本発明は、電気自動車用電源,UPS電源,パソコン用電源,モバイル機器用電源,飛行機を含む移動体用電源,家庭用電源,非常時用電源等に広く適用できる。 The present invention is widely applicable to electric vehicle power supplies, UPS power supplies, personal computer power supplies, mobile device power supplies, mobile power supplies including airplanes, household power supplies, emergency power supplies, and the like.
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