JP2008219528A - Device and program for detecting ldpc code - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device and programs for detecting LDPC code, which do not degrade error rate feature while greatly reducing the computational complexity of a sum-product algorithm. <P>SOLUTION: A bit node having the reliability β lower than a specified threshold θ, is row and column processed to be updated. On the other hand, for a bit node having the reliability β equal or higher than the specified threshold θ, the previous reliability β is used also in next time and the reliability β is not updated, so that the computational complexity can be reduced. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a code detection technique for decoding a code using an LDPC (low density parity check) code.

In recent years, LDPC codes have attracted attention in communication / broadcast / recording systems as error correction codes that achieve excellent characteristics approaching the theoretical limit. The LDPC code is achieved by using a sum product algorithm that is a repetitive operation (see, for example, Patent Document 1).
JP 2006-279396 A

  However, the sum product algorithm includes operations of nonlinear functions and has a large amount of calculation, and it is difficult to implement as it is.

  In view of the above problems, an object of the present invention is to provide an LDPC code detection apparatus and program that can significantly reduce the amount of calculation of the sum product algorithm without substantially deteriorating error rate characteristics.

  The LDPC code detection device of the present invention is connected to a check node from a plurality of check nodes set corresponding to a Tanner graph of a parity check matrix of (1). Low density parity check (hereinafter referred to as “LDPC”) code. Propagating the reliability α toward the plurality of bit nodes, and (2) propagating the reliability β toward the plurality of check nodes from the plurality of bit nodes, repeating (1) and (2), In the process, the code from the received value is determined using a sum product algorithm that determines the convergence by determining the posterior value hard decision value calculated from the reliability β by parity check using the parity check matrix and determining the estimated value of the transmitted code. In an LDPC code detection apparatus that performs detection, bit node selection means for selecting a bit node having a bit node reliability β smaller than a predetermined threshold θ, and the bit node selection For each check node connected to the bit node selected by a stage, based on the reliability β propagated from the bit node connected to the check node to the check node, the check node A reliability α to be propagated toward the bit node selected by the bit node selection means is calculated, and the row processing calculation means to be propagated and each bit node selected by the bit node selection means are connected to the bit node. Each bit that is not selected by the bit node selection means is calculated and updated based on the reliability α that is propagated from each check node and the reliability β that is propagated from the bit node toward each check node. Column processing operations and bits with the previous posterior value of the iteration as the next posterior value for the node Node updating means.

  In addition, a decoding repetition number counting means for counting the number of repetitions is further provided, and when the decoding repetition number exceeds a predetermined value, the bit node selection means selects all the bit nodes. By doing so, decoding can be achieved even in a poor communication environment.

  The present invention is a program for causing a computer to function as the LDPC code detection apparatus.

  According to the present invention, since the amount of decoding operation is greatly reduced, the implementation is facilitated, the power consumption is reduced, and the processing can be performed at high speed.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram illustrating a configuration of an LDPC code detection apparatus according to an embodiment of the present invention. The LDPC code detection apparatus according to the present embodiment includes an initial likelihood calculation means 10, an update processing reduction bit node selection means 11, an unupdated bit node information storage means 12, a row processing calculation means 13, a column processing calculation and a bit node update means 14. , Hard decision means 15, parity decision means 16, decoding repetition number counting means 17, and decoding process switching means 18.

  FIG. 2 is a diagram for explaining the LDPC code. First, the LDPC code will be described. The LDPC code is a code defined by a Tanner graph at the same time as a linear code defined by a very sparse check matrix, that is, a check matrix having a very small number of non-zero elements in the matrix. An excellent error rate characteristic is achieved by exchanging and updating the locally inferred result on the Tanner graph. FIG. 2 shows an example of a parity check matrix H with a row weight dc = 3 and a column weight dv = 2 for the (6,2) LDPC code. The check matrix H can also be shown by a Tanner graph as shown in the figure. A check node corresponds to a row, a bit node corresponds to a column, and an edge connecting between them corresponds to an element 1 in the matrix. For example, 1 with a circle in the second row and the fifth column of the parity check matrix H corresponds to an edge indicated by a thick line in the Tanner graph.

  SPA (Sum Product Algorithm) is a decoding algorithm that performs iterative decoding while passing information between check nodes and bit nodes and updating information of each node.

First, a conventional SPA will be described. In the parity check matrix H, a set of indexes of columns having “1” in the m-th row is N (m) = {n: Hm, n = 1}, and a set of indexes of rows having “1” in the n-th column is M. (N) = {m: Hm, n = 1}. The first update process for each node is shown below. The initial value β (0) mn is the initial likelihood β (0) mn = λn = (2 / σ ² ) rnyn. Here, σ ² is noise variance, rn is received power, and yn is a received symbol.
(1) Check node update: Update of an LLR (log likelihood ratio) value αmn passed from the mth check node to each nth bit node is expressed by the following equation.

ここで、ｎ'∈Ｎ(ｍ)＼ｎは、ｍに接続するビットノードｎ'の内ｎ番目のビットノードを含まない集合を表す。また、sign(・)は(・)の符号を返す関数である。

Here, n′εN (m) \ n represents a set not including the nth bit node among the bit nodes n ′ connected to m. Also, sign (•) is a function that returns the sign of (•).

集合Ａの要素ａ,ｂに関して、演算（＋を○で囲う記号）を以下のように定義する。

For the elements a and b of the set A, an operation (a symbol in which + is enclosed by ◯) is defined as follows.

（２）ビットノードの更新：ｎ番目ビットノードから、各ｍ番目チェックノードへ渡すＬＬＲ値βmnの更新を以下のように表す。

(2) Bit node update: Update of the LLR value βmn passed from the nth bit node to each mth check node is expressed as follows.

ここで、ｍ'∈Ｍ(ｎ)＼ｍは、ｎに接続するチェックノードｍ'の内ｍ番目のチェックノードを含まない集合を表す。各ビットの事後ＬＬＲを次式で更新する。

Here, m′εM (n) \ m represents a set not including the mth check node among the check nodes m ′ connected to n. The posterior LLR of each bit is updated by the following formula.

（３）硬判定とパリティチェック
（ａ）硬判定により復号系列を推定する。

(3) Hard decision and parity check (a) A decoded sequence is estimated by hard decision.

（ｂ）Ｈω＾＝０もしくは最大繰返数ｌ＝ｌmaxに達したときは、復号結果としてω＾を出力。Ｈω＾≠０の場合、ｌ＝ｌ＋１として再び各ノードの更新処理を行う。

(B) When Hω ^ = 0 or the maximum number of repetitions l = lmax, ω ^ is output as a decoding result. If Hω ^ ≠ 0, update processing of each node is performed again with l = 1 + 1.

  Next, the δ-min decoding algorithm will be described. The update expression for the check node shown in Expression (3) is a nonlinear function and is difficult to implement. A δ-min decoding algorithm has been proposed as a decoding algorithm that simplifies Equation (3). In the δ-min decoding algorithm, the deterioration of the block error rate (BLER) characteristic is small (about 0.05 dB) compared to SPA. Since the δ-min decoding algorithm does not require a correction factor by the density evolution method, it can be easily used in combination with the present invention.

  In order to approximate the equation (3) linearly, a Taylor series expansion is performed on the logarithmic function ln (1 + exp (−x)).

実装を考慮すると演算量の小さい１次項までを用い，定数項はｘ＞０の領域で関数ln(１＋exp(−ｘ))との誤差を補正した値（＝０．９）を用いる。関数ln(１＋exp(−ｘ))の線形近似式を以下に示す。

In consideration of implementation, the first order term with a small amount of calculation is used, and the constant term uses a value (= 0.9) obtained by correcting an error from the function ln (1 + exp (−x)) in the region of x> 0. A linear approximate expression of the function ln (1 + exp (−x)) is shown below.

本発明は，ＳＰＡや低演算量アルゴリズム（δ−ｍｉｎ復号アルゴリズム）と併用することでＬＤＰＣ符号の復号に必要なメモリー量及び消費電力を削減する。本発明は，２種類の閾値（ＬＬＲ閾値θLLR，繰返閾値θiter）を用いて更新処理を削減し，従来の復号アルゴリズムとほぼ等しい誤り率特性を達成する。本発明アルゴリズムは，ｌ−１回目の繰返処理のｎ番目のビットに対応するビットノードの事後ＬＬＲβ^{（ｌ−１）}nがＬＬＲの閾値θLLRより大きい場合（β^{（ｌ−１）}n≧θLLR），ｌ回目の更新処理を行わないことによって更新処理数を削減する。繰返閾値θiterは，ある回数θiter［回］以上繰返復号を行っても復号処理が終了しない場合，すべてのノードに対して更新処理を行うための閾値である。

The present invention reduces the amount of memory and power consumption required for decoding LDPC codes by using together with SPA and a low computational complexity algorithm (δ-min decoding algorithm). The present invention reduces update processing using two types of threshold values (LLR threshold value θLLR, repetition threshold value θiter), and achieves an error rate characteristic substantially equal to that of a conventional decoding algorithm. In the algorithm of the present invention, when the a posteriori LLRβ ^(l−1) n of the bit node corresponding to the n-th bit of the ^l− 1th iteration is larger than the LLR threshold θLLR (β ^(l−1) n ≧ θLLR ), The number of update processes is reduced by not performing the first update process. The repeat threshold θiter is a threshold for performing update processing on all nodes when the decoding process does not end even if repeated decoding is performed more than a certain number of times θiter [times].

The algorithm of the present invention is shown below.
(1) Comparison of LLR threshold θLLR and bit node LLRβn:
(A) The number of repetitions l-1 <θiter: The a posteriori LLRβ ⁽ 1-1 ⁾ n of the ^l− 1th bit node is compared with the LLR threshold θLLR.
^{· | Β (l-1)} n | ≧ θLLR the bits n set the N _ = {n: | β (l-1) n | ≧ θLLR} index expressed as.
^{· | Β (l-1)} n | <N¯ a set of index columns with "1" in m-th row with respect θLLR the bits n (m) = {n: Hm, n = 1∩ | β (l ⁻¹⁾ n | <θLLR}, and the set of indexes of the row having “1” in the nth column is M￣ (n) = {m: Hm, n = 1∩ | β ^(l−1) n | <θLLR }.
(B) Number of repetitions l−1 ≧ θiter: All update processes are performed.
(2) Check node update: The update of the LLR value αmn passed from the mth check node to each nth bit node is performed when each nth bit node is | β ^(l−1) n | <θLLR. It is expressed as the following formula.

一方、ビットノードの事後ＬＬＲ値が｜β^{（ｌ−１）}n｜≧θLLRである各ビットノードに渡すＬＬＲ値αmnの更新、すなわち、行処理演算は行わない。
（３）ビットノードの更新：ｎ番目ビットノードから，各ｍ番目チェックノードに渡すＬＬＲ値βmnの更新を以下のように表す。
（ａ）｜β^{（ｌ−１）}n｜＜θLLRの場合。

On the other hand, the update of the LLR value αmn to be passed to each bit node for which the a posteriori LLR value of the bit node is | β ^(l−1) n | ≧ θLLR, that is, the row processing operation is not performed.
(3) Bit node update: The update of the LLR value βmn passed from the nth bit node to each mth check node is expressed as follows.
(A) | β ⁽ 1-1 ⁾ n | <θLLR.

｜β^{（ｌ−１）}n｜＜θLLRのビットの事後ＬＬＲを次式で更新する。

Update the a posteriori LLR of the bit of | β ^(l−1) n | <θLLR by the following equation.

（ｂ）｜β^{（ｌ−１）}n｜≧θLLRの場合。ｌ−１回目のビットノードの事後ＬＬＲ値β^{（ｌ−１）}nをｌ回目のビットノードの事後ＬＬＲ値β^（ｌ）nとする。

(B) | β ⁽ 1-1 ⁾ n | ≧ θLLR. The posterior LLR value β ^(l−1) n of the ^(l−1) th bit node is set as the posterior LLR value β ^(l) n of the lth bit node.

（４）硬判定とパリティチェック
従来ＳＰＡと同様。

(4) Hard decision and parity check Same as conventional SPA.

Next, returning to FIG. 1, a specific configuration for realizing the present embodiment will be described. First, the initial likelihood calculating means 10 receives the received signal, calculates the initial likelihood β (0) mn = λn = (2 / σ ² ) rnyn, and sets it as the initial likelihood of each bit node. Next, the update processing reduction bit node selection unit 11 compares the LLR threshold θLLR with the bit node LLRβn, and performs an operation for updating for a bit node satisfying | β ^(l−1) n | ≧ θLLR. First, the previous posterior LLR is used as it is (Formula 12). In order to update a bit node satisfying | β ^(l−1) n | <θLLR, a row processing operation is performed from the connected check node to the bit node. The unupdated bit node information storage means 12 stores the a posteriori LLR value of the bit node that is not updated as it is, and stores it as unupdated bit node information. The row processing calculation means 13 updates the row processing calculation passed from the check node connected to the bit node to be updated to the bit node (Equation 9). The column processing calculation and bit node update means 14 updates the bit node to be updated by column processing calculation. The hard decision means 15 makes a hard decision based on the posterior LLR value of each bit node to obtain a temporary estimated value (Formula 6). The parity determination means 16 calculates the parity of the temporary estimated value from the temporary estimated value of the hard decision result and the check matrix H, and determines whether the parity is 0 or 1. If the parity is 0, the temporary estimated value is output as a decoded word and the operation is terminated. When the parity is 1, the decoding repetition number counting unit 17 counts the number of repetitions l, and the decoding process switching unit 18 compares l−1 with a predetermined threshold θiter, and l−1 <θiter. In this case, the bit node to be updated and the bit node not to be updated are selected, and when l−1 ≧ θiter, the signal processing is switched so as to update all the bit nodes.

  FIG. 3 is a diagram comparing the error rates of the present invention and the conventional example. FIG. 3 shows an AWGN (Additive White Gaussian Noise) communication path, BPSK (Bi-Phase Shift) of the present invention SPA and a conventional SPA for various LDPC codes such as a coding rate R = 1/2 and (3,6) regular LDPC. BER (Bit Error Rate) characteristics with respect to Eb / No (signal-to-noise ratio) in keying modulation. It can be seen that the BER is hardly deteriorated in the present invention.

  FIG. 4 is a diagram comparing the block error rates of the present invention and the conventional example. FIG. 4 shows BLER (BLock Error Rate) characteristics for Eb / No in AWGN communication channels and BPSK modulation of the present invention SPA and the conventional SPA for various LDPC codes. It can be seen that BLER is hardly deteriorated in the present invention.

  FIG. 5 is a diagram for comparing the amount of calculation between the present invention and the conventional example. FIG. 5 shows calculation amounts for Eb / No of the present invention SPA and the conventional SPA for various LDPC codes. It can be seen that the calculation amount of the present invention is reduced to about 80 to 10% as compared with the prior art. If the environment is good, the amount of calculation can be reduced to about 1/10 compared with the conventional case.

  In addition, this invention is not limited to the said Example.

  Even without using the δ-min decoding algorithm, the present invention has the effect of sufficiently reducing the amount of calculation.

  The LLR may be a parameter indicating the reliability of the check node or the bit node, and is not limited to the LLR.

  The LDPC code detection apparatus of the present invention is also realized by a program for causing a computer to function as the LDPC code detection apparatus. This program may be stored in a computer-readable recording medium.

  The recording medium on which this program is recorded may be the ROM itself of the LDPC code detection device shown in FIG. 1, or a program reading device such as a CD-ROM drive is provided as an external storage device, and recorded there. It may be a CD-ROM or the like that can be read by inserting a medium.

  The recording medium may be a magnetic tape, a cassette tape, a flexible disk, a hard disk, an MO / MD / DVD, or a semiconductor memory.

It is a figure which shows the structure of the LDPC code detection apparatus by one Example of this invention. It is a figure explaining an LDPC code. It is a figure which compares the error rate of this invention and a prior art example. It is a figure which compares the block error rate of this invention and a prior art example. It is a figure which compares the computational complexity of this invention and a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Initial likelihood calculation means 11 Update process reduction bit node selection means 12 Unupdated bit node information storage means 13 Row processing calculation means 14 Column processing calculation and bit node update means 15 Hard decision means 16 Parity decision means 17 Decoding repeat count count Means 18 Decoding process switching means

Claims (3)

(1). From a plurality of check nodes set corresponding to a Tanner graph of a parity check matrix of a low density parity check (hereinafter referred to as “LDPC”) code to a plurality of bit nodes connected to the check node Propagate reliability α,
(2) Propagating reliability β from the plurality of bit nodes to the plurality of check nodes,
A sum product that repeats (1) and (2), and determines the estimated value of the transmitted code by determining the convergence by performing a parity check on the hard decision value of the posterior value calculated from the reliability β in the process using the parity check matrix. In an LDPC code detection device that performs code detection from a received value using an algorithm,
A bit node selection means for selecting a bit node whose bit node reliability β is smaller than a predetermined threshold θ;
For each check node connected to the bit node selected by the bit node selection means, based on the reliability β propagated from the bit node connected to the check node toward the check node, Calculating a reliability α to be propagated from the check node toward the bit node selected by the bit node selection means, and a row processing calculation means to propagate;
For each bit node selected by the bit node selection means, the reliability propagated from the bit node toward each check node based on the reliability α propagated from each check node connected to the bit node calculating and updating β, and for each bit node not selected by the bit node selection means, a column processing operation and a bit node update means with the previous posterior value of the repetition as the next posterior value;
An LDPC code detection apparatus comprising:   Decoding repetition number counting means for counting the number of repetitions is further provided, and when the decoding repetition number exceeds a predetermined value, the bit node selection means selects all bit nodes. LDPC code detection apparatus characterized by the above. A program for causing a computer to function as the LDPC code detection device according to claim 1.

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