JP2008218883A - Method of manufacturing semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor wafer wherein the entire fabrication volume is reduced. <P>SOLUTION: In the method of manufacturing the semiconductor wafer, a wafer surface is mirror polished (S3) immediately after the sliced wafer fabricated by slicing (S1) a semiconductor crystal ingot is chamfered. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer manufacturing method capable of reducing the overall processing amount.

  Compound semiconductors are used to manufacture electronic devices such as Schottky gate field effect transistors (MESFETs), high mobility transistors (HEMTs), and hetero-coupled bipolar transistors (HBTs), and light receiving and emitting devices such as LEDs, LDs, and PDs. .

  The active layer of these devices is formed on the surface of a mirror wafer, which is a semiconductor wafer having a mirror surface, by molecular beam epitaxy (MBE), metal organic vapor phase epitaxy (MOVPE), or ion implantation. .

  The mirror surface wafer is manufactured by the following procedure.

  As shown in FIG. 3, first, the semiconductor crystal ingot is sliced to cut a slice wafer (S31). Next, the slice wafer is chamfered (S32), and then lapping or surface grinding is performed (S33). Next, etching is performed (S34), and then mirror processing (= polishing) is performed (S35). Next, cleaning is performed and drying is performed to obtain a final mirror wafer (S36).

  Lapping is performed with an # 800 to # 3000 alumina grindstone. Surface grinding is performed with a grindstone. Lapping or surface grinding is performed to remove slice damage and improve flatness.

  Mirror finishing is a mechanochemical that uses a hypozinc acid aqueous solution as a polishing liquid, a mixed solution of a hypozinc acid aqueous solution and abrasive grains (silica, alumina, zirconium), or a polishing cloth having a porous layer on the surface as a polishing cloth. Polishing. Thereby, the surface of the semiconductor wafer is finished to a mirror surface.

  In the cleaning process, degreasing cleaning, cleaning with a cleaning solution having a slight etching action, and ultrapure water cleaning are sequentially performed.

  Further, as shown in FIG. 4, the lapping process or the surface grinding process is omitted, and the slicing process (S41), the chamfering process (S42), the etching process (S43), the mirror surface process (S44), and the cleaning process (S45). A procedural manufacturing method is also known.

JP 2004-165484 A

  In the manufacturing method of FIG. 3, slice damage is removed by lapping or surface grinding (S34). However, in the manufacturing method of FIG. 4, since there is no step, the polishing amount (= processing amount) in mirror surface processing (S44). Needs to be added to the amount of processing in the mirror surface processing (S35) of the manufacturing method of FIG. 3 by omitting lapping or surface grinding.

  For this reason, the whole processing amount does not change in the manufacturing method of FIG. 3 and the manufacturing method of FIG. Therefore, although the manufacturing method of FIG. 4 aims to reduce the manufacturing cost, a significant reduction in manufacturing cost cannot be expected as compared with the manufacturing method of FIG.

  If the slice damage can be reduced by improving the slice processing, the amount of processing in the subsequent process for removing the slice damage can be reduced. However, it is not easy to improve the slice processing.

  Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor wafer that can solve the above-described problems and reduce the overall processing amount.

  In order to achieve the above object, according to the present invention, a slice wafer obtained by slicing a semiconductor crystal ingot is chamfered and then mirror-finished immediately.

  It is good also considering the processing amount of the said mirror surface processing as 17 micrometers-20 micrometers.

  The semiconductor may be a III-V group compound semiconductor.

  The III-V group compound semiconductor may be GaAs.

  The III-V compound semiconductor may be semi-insulating GaAs.

  The semiconductor may be a II-VI group compound semiconductor.

  The present invention exhibits the following excellent effects.

  (1) The total processing amount can be reduced.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

  As shown in FIG. 1, the semiconductor wafer manufacturing method according to the present invention removes slice damage by chamfering a slice wafer obtained by slicing a semiconductor crystal ingot and then mirror-finishing it immediately. is there.

  More specifically, first, the semiconductor crystal ingot is sliced to cut a slice wafer (S1). Next, the slice wafer is chamfered (S2). Next, mirror processing (= polishing) is performed (S3). Next, cleaning is performed and drying is performed to obtain a final mirror surface wafer (S4).

  As described above, the reason why the total processing amount cannot be reduced is that the processing amount necessary for removing the slice damage does not change because the slice damage is not reduced. Therefore, the present inventor has considered eliminating the etching process. As will be discussed in detail later, the etching process causes a large slice damage. Therefore, the idea is that if the etching process is eliminated, slice damage can be reduced and the amount of processing can be reduced.

  As shown in FIG. 2, the damage depth is shallow when the etching amount is 35 μm, and the damage depth becomes deep as the etching amount is reduced. However, when the etching amount is 12 μm, the damage depth reaches the maximum peak, and when the etching amount is smaller than that, the damage depth becomes shallower, and the etching depth is 0 and the damage depth is the shallowest. Therefore, in order to reduce the slice damage as much as possible, the etching process may be eliminated. Conventionally, the etching amount is 10 μm.

  The etching process contributes to increase / decrease in slice damage for the following reason. That is, it is assumed that, for example, a slice damage having a depth of 0.5 μm is present on the wafer surface after the slice processing.

  When this wafer is etched, the wafer surface is lost and lowered, and at the same time, slice damage is etched and becomes deeper and wider. As shown in FIG. 2, the slice damage increases when the etching amount is 0 to about 15 μm. If the etching process is further continued, the lowering of the wafer surface eventually catches up with the bottom of the slice damage and becomes flat (the slice damage disappears). In the experiment, the slice damage remained even when the etching amount (descent of the wafer surface) was 35 μm. Therefore, it seems that the etching amount with which the descent of the wafer surface catches up with the bottom of the slice damage is considerably larger than 35 μm.

  On the other hand, when the wafer is polished, that is, mirror-finished (= polished), there is an etching action, so that the slice damage becomes deeper and wider as in the etching process. However, since the mechanical action is large, the lowering of the wafer surface quickly catches up with the bottom of the slice damage. In the experiment, if the amount of mirror processing is 17 μm on one side, the lowering of the wafer surface catches up with the bottom of the slice damage.

  As described above, in the present invention, since the etching process is not performed, the slice damage is reduced, and therefore, the entire processing amount (mirror processing amount) can be reduced. As a result, a great effect can be obtained in reducing the manufacturing cost of the semiconductor wafer.

  In the present invention, slice damage can be completely removed if the amount of mirror surface processing is 17 μm to 20 μm on one side.

  A semiconductor of the semiconductor wafer to which the present invention is applied includes a III-V group compound semiconductor. As the III-V compound semiconductor, there is GaAs or semi-insulating GaAs.

  As a semiconductor of the semiconductor wafer to which the present invention is applied, there is a II-VI group compound semiconductor.

(Example)
After the sliced wafer was chamfered, the surface (front surface) of the sliced wafer was mirror-finished to a processing amount of 17 μm by a polishing apparatus. The polishing apparatus used was a speed femme polisher, the polishing solution was a mixture of a hypozinc acid aqueous solution and silica, and the polishing cloth was made of polyurethane. A carrier formed of glass fiber and epoxy resin was used. After completion of the mirror finishing, when the residual slice damage was evaluated, no residual slice damage was observed in the outer periphery of the semiconductor wafer.
(Reference example)
The sliced slice wafer was mirror-finished to a processing amount of 15 μm by the same procedure as in the example. After the mirror finish, when the remaining slice damage was evaluated, the remaining slice damage was observed.

  As a result, it was found that the processing amount is preferably 17 μm or more.

It is a flowchart of the manufacturing process of the semiconductor wafer which shows one Embodiment of this invention. It is an etching amount versus damage depth characteristic view. It is a flowchart of the manufacturing process of the conventional semiconductor wafer. It is a flowchart of the manufacturing process of the conventional semiconductor wafer.

Explanation of symbols

S1 Slicing S3 Mirror finish

Claims (6)

  A method for producing a semiconductor wafer, comprising: chamfering a slice wafer obtained by slicing a semiconductor crystal ingot, and then immediately mirror-finishing the slice wafer.   2. The method of manufacturing a semiconductor wafer according to claim 1, wherein a processing amount of the mirror finishing is set to 17 to 20 [mu] m.   3. The method of manufacturing a semiconductor wafer according to claim 1, wherein the semiconductor is a III-V compound semiconductor.   4. The method of manufacturing a semiconductor wafer according to claim 3, wherein the III-V compound semiconductor is GaAs.   4. The method of manufacturing a semiconductor wafer according to claim 3, wherein the III-V group compound semiconductor is semi-insulating GaAs.   3. The method for producing a semiconductor wafer according to claim 1, wherein the semiconductor is a II-VI group compound semiconductor.

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