JP2008218758A5 - - Google Patents
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- Publication number
- JP2008218758A5 JP2008218758A5 JP2007054957A JP2007054957A JP2008218758A5 JP 2008218758 A5 JP2008218758 A5 JP 2008218758A5 JP 2007054957 A JP2007054957 A JP 2007054957A JP 2007054957 A JP2007054957 A JP 2007054957A JP 2008218758 A5 JP2008218758 A5 JP 2008218758A5
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- semiconductor elements
- substrate
- rows
- resin adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims 29
- 239000011347 resin Substances 0.000 claims 15
- 229920005989 resin Polymers 0.000 claims 15
- 239000000758 substrate Substances 0.000 claims 15
- 239000012790 adhesive layer Substances 0.000 claims 11
- 230000002093 peripheral effect Effects 0.000 claims 4
- 229920001187 thermosetting polymer Polymers 0.000 claims 2
- 230000005611 electricity Effects 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 claims 1
Claims (9)
前記各半導体素子の前記バンプに対応する位置に設けられた電極端子を有する基板と、
前記半導体素子ごとに設けられ、前記各半導体素子の前記バンプと前記基板の前記電極端子とを電気的に接続した状態で前記各半導体素子を前記基板上に接着する各樹脂接着層と、を備え、
前記各樹脂接着層は、前記各半導体素子の前記所定の辺部からのはみ出し量が、前記他の辺部からのはみ出し量よりも小さく、
前記各半導体素子は、前記樹脂接着層のはみ出し量が小さい前記所定の辺部同士が隣接する配置で実装されている
ことを特徴とする電子回路実装構造体。 It has bumps formed in an array configuration of one or more rows on each side part constituting the peripheral part of the main surface, and the bumps formed on at least one predetermined side part of each of the side parts, a plurality of semiconductor element and the were found provided with more columns than columns of the bumps formed on the other side portion of the respective side portions,
A substrate having electrode terminals provided at positions corresponding to the bumps of the semiconductor elements;
A resin adhesive layer that is provided for each of the semiconductor elements and that bonds the semiconductor elements onto the substrate in a state where the bumps of the semiconductor elements and the electrode terminals of the substrate are electrically connected to each other; ,
Each of the resin adhesive layers has an amount of protrusion from the predetermined side of each semiconductor element smaller than an amount of protrusion from the other side,
Each of the semiconductor elements is mounted in an arrangement in which the predetermined side portions where the protruding amount of the resin adhesive layer is small are adjacent to each other.
前記各半導体素子の前記バンプに対応する位置に設けられた電極端子を有する基板と、
前記半導体素子ごとに設けられ、前記各半導体素子の前記バンプと前記基板の前記電極端子とを電気的に接続した状態で前記各半導体素子を前記基板上に接着する各樹脂接着層と、を備え、
前記各樹脂接着層は、前記各半導体素子の前記所定の辺部からのはみ出し量が、前記他の辺部からのはみ出し量よりも小さく、
前記各半導体素子は、前記樹脂接着層のはみ出し量が小さい前記所定の辺部同士が隣接する配置で実装されている
ことを特徴とする電子回路実装構造体。 It has bumps formed in an array configuration of one or more rows on each side part constituting the peripheral part of the main surface, and the bumps formed on at least one predetermined side part of each of the side parts, A plurality of semiconductor elements provided at an arrangement pitch shorter than the arrangement pitch of the bumps formed on the other side of each of the sides;
A substrate having electrode terminals provided at positions corresponding to the bumps of the semiconductor elements;
A resin adhesive layer that is provided for each of the semiconductor elements and that bonds the semiconductor elements onto the substrate in a state where the bumps of the semiconductor elements and the electrode terminals of the substrate are electrically connected to each other; ,
Each of the resin adhesive layers has an amount of protrusion from the predetermined side of each semiconductor element smaller than an amount of protrusion from the other side,
Wherein each of the semiconductor element, the resin adhesive layer in the outside electricity quantity is less the predetermined side portions you wherein <br/> that are mounted in an arrangement that neighboring sub-circuit mounting structure.
前記基板の前記電極端子は、前記ダミーバンプ以外の前記バンプに対応する位置に設けられている
ことを特徴とする請求項１もしくは２のいずれかに記載の電子回路実装構造体。 In at least one of the semiconductor elements, a dummy bump is included in the bump formed on the predetermined side where the protruding amount of the resin adhesive layer is small, and the bump including the dummy bump is in two or more rows, and Arranged in a staggered pattern,
The electronic circuit mounting structure according to any one of claims 1 and 2 , wherein the electrode terminal of the substrate is provided at a position corresponding to the bump other than the dummy bump .
前記各半導体素子の前記バンプに対応する位置に設けられた電極端子を有する基板と、
前記半導体素子ごとに設けられ、前記各半導体素子の前記バンプと前記基板の前記電極端子とを電気的に接続した状態で前記各半導体素子を前記基板上に接着する各樹脂接着層と、を備え、
前記各半導体素子は、前記バンプが他の辺部よりも多い列数で設けられた辺部同士が隣接する配置で実装されている
ことを特徴とする電子回路実装構造体。 It has bumps formed in an array configuration of one or more rows on each side part constituting the peripheral part of the main surface, and the bumps formed on at least one predetermined side part of each of the side parts, A plurality of semiconductor elements provided with a larger number of rows than the number of rows of the bumps formed on the other sides of the sides;
A substrate having electrode terminals provided at positions corresponding to the bumps of the semiconductor elements;
A resin adhesive layer that is provided for each of the semiconductor elements and that bonds the semiconductor elements onto the substrate in a state where the bumps of the semiconductor elements and the electrode terminals of the substrate are electrically connected to each other; ,
Each of the semiconductor elements is mounted in an arrangement in which the side portions where the bumps are provided in more rows than the other side portions are adjacent to each other.
An electronic circuit mounting structure characterized by that.
前記基板の前記電極端子は、前記ダミーバンプ以外の前記バンプに対応する位置に設けられているThe electrode terminal of the substrate is provided at a position corresponding to the bump other than the dummy bump.
ことを特徴とする請求項５記載の電子回路実装構造体。6. An electronic circuit mounting structure according to claim 5, wherein
前記各半導体素子の前記バンプに対応する位置に設けられた電極端子を有する基板と、
前記半導体素子ごとに設けられ、前記各半導体素子の前記バンプと前記基板の前記電極端子とを電気的に接続した状態で前記各半導体素子を前記基板上に接着する各樹脂接着層と、を備え、
前記各半導体素子は、前記バンプが他の辺部よりも短い配列ピッチで設けられた辺部同士が隣接する配置で実装されている
ことを特徴とする電子回路実装構造体。 It has bumps formed in an array configuration of one or more rows on each side part constituting the peripheral part of the main surface, and the bumps formed on at least one predetermined side part of each of the side parts, A plurality of semiconductor elements provided at an arrangement pitch shorter than the arrangement pitch of the bumps formed on the other side of each of the sides;
A substrate having electrode terminals provided at positions corresponding to the bumps of the semiconductor elements;
A resin adhesive layer that is provided for each of the semiconductor elements and that bonds the semiconductor elements onto the substrate in a state where the bumps of the semiconductor elements and the electrode terminals of the substrate are electrically connected to each other; ,
Each of the semiconductor elements is mounted in such a manner that the side portions where the bumps are provided at an arrangement pitch shorter than the other side portions are adjacent to each other.
An electronic circuit mounting structure characterized by that.
前記基板の前記電極端子は、前記ダミーバンプ以外の前記バンプに対応する位置に設けられているThe electrode terminal of the substrate is provided at a position corresponding to the bump other than the dummy bump.
ことを特徴とする請求項７記載の電子回路実装構造体。The electronic circuit mounting structure according to claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007054957A JP2008218758A (en) | 2007-03-06 | 2007-03-06 | Electronic circuit mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007054957A JP2008218758A (en) | 2007-03-06 | 2007-03-06 | Electronic circuit mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2008218758A JP2008218758A (en) | 2008-09-18 |
| JP2008218758A5 true JP2008218758A5 (en) | 2009-11-12 |
Family
ID=39838433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007054957A Withdrawn JP2008218758A (en) | 2007-03-06 | 2007-03-06 | Electronic circuit mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2008218758A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010278318A (en) | 2009-05-29 | 2010-12-09 | Renesas Electronics Corp | Semiconductor device |
| WO2015056430A1 (en) * | 2013-10-16 | 2015-04-23 | パナソニック株式会社 | Semiconductor device |
| JP5770258B2 (en) * | 2013-12-20 | 2015-08-26 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| JP6394021B2 (en) * | 2014-03-20 | 2018-09-26 | 富士通株式会社 | Electronic device, method for manufacturing electronic device, and method for manufacturing electronic component |
| KR20210051535A (en) | 2019-10-30 | 2021-05-10 | 삼성전자주식회사 | Semiconductor package and method for fabricating the same |
-
2007
- 2007-03-06 JP JP2007054957A patent/JP2008218758A/en not_active Withdrawn
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