JP2008217880A - Built-in memory test circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory BIST circuit capable of performing testing at accurtate timing without extending test time. <P>SOLUTION: An expectation value EXP generated based on step information STP output from a test step count part 11A is compared with test data TDO output from a circuit to be tested 1 according to a test pattern generated based on the step information STP. If unmatched, a failure information output unit 15A fetches the step information STP or the like in a failure information storage register to output it as failure disgnostic information DIAG in parallel with a BIST operation. During use of the failure information storage register, the BIST operation is stopped to output the failure diagnostic information DIAG. When the output is completed, step information of one step before the failure step is provided as test resume information RST to the test step count part 11A. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an embedded memory test circuit incorporated in a memory for performing a test.

FIG. 2 is a configuration diagram of a conventional memory BIST (Build In Self Test) circuit.
This memory BIST circuit is incorporated in a semiconductor memory device for testing at the time of memory manufacture, and includes a test step count unit 11, a test pattern generation unit 12, an expected value generation unit 13, a comparison unit 14, and a failure information output unit. 15 and a selector 16.

  The test step count unit 11 tests step information STP such as an address for specifying the storage area of the circuit under test 1 in a predetermined order based on the clock signal CLK in order to test the quality of the memory as the circuit under test 1. Is generated and output. Further, the test step count unit 11 has a function of stopping or changing the step information STP according to the comparison result signal RES given from the comparison unit 14. Further, when a series of test steps is completed, an end signal FIN is output.

  The test pattern generator 12 generates an address signal ADR, write test data TDI for the circuit under test 1 and a control signal CON designating operations such as reading and writing in accordance with the step information STP given from the test step count unit 11. It is. The address signal ADR, test data TDI, and control signal CON are supplied as a test pattern to the failure information output unit 15 and to the circuit under test 1 via the selector 16.

  When the test mode is designated by the mode signal MOD, the selector 16 outputs the test pattern given from the test pattern generation unit 12 to the circuit under test 1. When the normal operation mode is designated by the mode signal MOD, An address signal ADR, write data DI, and control signal CON given from a system bus (not shown) are output to the circuit under test 1.

  The expected value generator 13 generates an expected value EXP to be output when the circuit under test 1 is normal according to the step information STP given from the test step count unit 11. The comparison unit 14 compares the expected value EXP generated by the expected value generation unit 13 with the test data TDO actually output from the circuit under test 1 and outputs a comparison result signal RES as to whether or not they match. To do. The comparison result signal RES is given to the test step count unit 11 and the failure information output unit 15.

  The failure information output unit 15 outputs the step information STP, the address signal ADR, the write data DI, and the control signal CON at that time, and the circuit under test 1 when the comparison result signal RES outputs a mismatch. The test data TDO is serially output as failure diagnosis information DIAG.

3A to 3C are explanatory diagrams illustrating an operation example during the test of FIG.
FIG. 3A shows a case where the BIST operation (test) is temporarily stopped and the failure diagnosis information DIAG is output when a mismatch is detected by the comparison unit 14 in the memory BIST circuit. In this case, when a mismatch occurs at the address AD1, the test is interrupted and output of the failure diagnosis information DIAG is started. When the output of the failure diagnosis information DIAG is completed, the test is restarted from the address AD2 next to the address AD1 where the mismatch has occurred.

  3B and 3C, when a mismatch is detected by the comparison unit 14 in the BIST circuit, the test is continued without stopping the BIST operation, and the fault diagnosis information DIAG is output in parallel with the test. Shows when to do. In this case, as shown in FIG. 3B, if the next mismatch does not occur while the failure diagnosis information DIAG generated at the address AD1 is output, there is no problem in executing the test. Continued. However, if a mismatch occurs again at the address AD3 while the failure diagnosis information DIAG generated at the address AD1 is being output, the failure diagnosis information at the address AD3 cannot be taken into the failure information output unit 15. For this reason, when the output of the failure diagnosis information DIAG generated at the address AD1 is completed, the test is started again from the beginning. However, since the failure diagnosis information DIAG up to the step corresponding to the address AD3 has already been output from the failure information output unit 15, the comparison determination processing up to the address AD3 is skipped. When all the test steps are completed, an end signal FIN is output from the test step counting unit 11, and the BIST is terminated.

  In the normal operation mode, the selector 16 is switched to the system bus side by the mode signal MOD, and the memory BIST circuit is disconnected from the memory which is the circuit under test 1.

Japanese Patent Laid-Open No. 2001-266592 “Set Controller Debug” MBISTArchitect Reference Manual, V8.2006-1, Feb 2006 p.2-169 to p.2-173

  However, as shown in FIG. 3A, the memory BIST circuit temporarily stops the test when the mismatch is detected at the address AD1, outputs the fault diagnosis information DIAG, and then restarts the test from the next address AD2. In this case, the timing of the control signal CON or the like given from the test pattern generation unit 12 to the circuit under test 1 for the address AD2 is different from that for other addresses. For this reason, there is a problem that the test time is extended in order to output the failure diagnosis information DIAG, and the test for the address AD2 cannot be performed at an accurate timing.

  On the other hand, as shown in FIG. 3C, when the failure diagnosis information DIAG is output and then the test is repeated after returning to the beginning, there is no problem due to the difference in timing, but the test time becomes extreme as the number of failure points increases. There was a problem of increasing.

  An object of the present invention is to provide a memory BIST circuit capable of performing a test at an accurate timing without increasing a test time.

  A built-in memory test circuit according to the present invention includes a test step count unit that generates step information according to a comparison result signal, test resumption information, and diagnostic state information, and a test that generates a test pattern to be applied to a circuit under test according to the step information. A pattern generator, an expected value generator for generating an expected value to be output from the circuit under test according to the step information, and comparing the expected value with output data output from the circuit under test. A comparison unit that outputs a result signal, and captures failure information of the circuit under test based on the step information, the test pattern, the comparison result signal, and the output data, and outputs the failure information as failure diagnosis information. Output as the diagnostic status information, and the test resumption information after the completion of the output of the fault diagnostic information Is characterized in that a failure information output unit for outputting.

  In the present invention, the state at the time when a failure is found by the comparison result signal is temporarily held and output as failure diagnosis information, and at the time when the output of the failure diagnosis information is completed, the address before the failure detection time is set. A failure information output unit is provided for outputting test resumption information for returning and restarting the test to the test step count unit. As a result, the operation of the BIST and the output of the fault diagnosis information discovered in this test can be performed at the same time, and an increase in test time can be suppressed.

  Furthermore, even if a fault is found during the output of fault diagnosis information, the test can be resumed by returning to the address before the fault detection without returning to the initial state, thus avoiding a duplicate test, There is an effect that the test can be performed at an accurate timing.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

  FIG. 1 is a configuration diagram of a memory BIST circuit showing Embodiment 1 of the present invention. Elements common to those in FIG. 2 are denoted by common reference numerals.

  The memory BIST circuit includes a test step count unit 11A, a test pattern generation unit 12, an expected value generation unit 13, a comparison unit 14, a failure information output unit 15A, a selector 16, and a diagnosis state flag 17.

  The test step count section 11A tests step information STP such as an address for designating the storage area of the circuit under test 1 in a predetermined order based on the clock signal CLK in order to test the quality of the memory as the circuit under test 1. Is generated and output. Further, the test step count unit 11A performs a step in accordance with the comparison result signal RES given from the comparison unit 14, the test resumption information RST given from the failure information output unit 15A, and the diagnosis state flag FLG set in the diagnosis state flag 17. It has a function of stopping and changing information STP. Further, the test step counting unit 11A outputs an end signal FIN when a series of test steps is completed.

  The test pattern generator 12 generates an address signal ADR, write and test data TDI for the circuit under test 1 and a control signal CON for designating a read / write operation in accordance with step information STP given from the test step count unit 11A. It is. These address signal ADR, test data TDI, and control signal CON are given as a test pattern to the failure information output unit 15A, and also to the circuit under test 1 via the selector 16.

  When the test mode is designated by the mode signal MOD, the selector 16 outputs the test pattern given from the test pattern generation unit 12 to the circuit under test 1. When the normal operation mode is designated by the mode signal MOD, An address signal ADR, write data DI, and control signal CON given from a system bus (not shown) are output to the circuit under test 1.

  The expected value generator 13 generates an expected value EXP to be output when the circuit under test 1 is normal, in accordance with the step information STP given from the test step count unit 11A. The comparison unit 14 compares the expected value EXP generated by the expected value generation unit 13 with the test data TDO actually output from the circuit under test 1 and outputs a comparison result signal RES as to whether or not they match. To do. The comparison result signal RES is given to the test step count unit 11A and the failure information output unit 15A.

  The failure information output unit 15A has step information STP, an address signal ADR, write data DI, a control signal CON, and a failure information storage register for storing the test data TDO output from the circuit under test 1. The failure information output unit 15A is configured to serially output information stored in the failure information storage register as failure diagnosis information DIAG when it is output that there is a mismatch by the comparison result signal RES. . Further, the failure information output unit 15A has a function of outputting the test resumption information RST to the test step count unit 11A and outputting the diagnosis state update information STS to the diagnosis state flag 17. Note that the test resumption information RST indicates the step immediately before the step determined to be inconsistent by the comparison result signal RES.

  The diagnosis state flag 17 sets a flag FLG based on the diagnosis state update information STS given from the failure information output unit 15A, and outputs this flag FLG to the test step count unit 11A.

  FIG. 4 is a flowchart showing the processing flow of FIG. The processing of the memory BIST shown in FIG. 1 will be described below with reference to FIG.

  When the test operation by the memory BIST circuit is started, in the process P1, the step information STP of the test step count unit 11A and the diagnosis state flag 17 are initialized, and the process proceeds to the step update process of the process P2.

  In the process P2, the test step count unit 11A updates the step information STP as follows according to the flag FLG set in the diagnosis state flag 17. That is, when the flag FLG set in the diagnosis state flag 17 is in the diagnosis state 1 set by initialization, the step information STP is advanced by one. When in the diagnosis state 2, the step is continued until the output of the failure diagnosis information DIAG is completed. Update of information STP is stopped. In the diagnosis state 3, the step information STP is returned to the state of the previous step of the step information STP stored in the failure information storage register. After process P2, the process proceeds to process P3.

  In the process P3, the comparison unit 14 compares the expected value EXP output from the expected value generation unit 13 with the test data TDO actually output from the circuit under test 1, and compares the comparison result signal RES as to whether or not they match. Is output. If the comparison result signal RES indicates that they match, the process proceeds to process P4. If they do not match, the process proceeds to process P5.

  In process P4, the test step count unit 11A determines whether or not the test is completed. If all the test steps are finished, the operation of the memory BIST is finished. If not completed, return to process 2.

  On the other hand, when the comparison result signal RES indicates a mismatch, the failure information output unit 15A determines whether or not the failure diagnosis information DIAG being output exists in the process P5. If there is no failure diagnosis information DIAG being output, the process proceeds to process P6. If the failure diagnosis information DIAG is being output, the process proceeds to process P7.

  In the process P6, output of the failure diagnosis information DIAG is started, and the process immediately proceeds to the process P4 without waiting for the completion of the output. On the other hand, in process P7, step information STP of the mismatched test step is added to the fault information storage register of the fault information output unit 15A, and the process proceeds to process P8.

  In the process P8, the diagnosis state 2 is set in the flag FLG of the diagnosis state flag 17, and the process waits until the output of the previous mismatch diagnosis information DIAG is completed. Then, when the output of the previous mismatch diagnostic information DIAG is completed, the diagnosis state 3 is set in the flag FLG, and the process proceeds to process P2. Such a process is continued until all test steps are completed.

FIG. 5 is an explanatory diagram showing the operation during the test of FIG.
When the test execution causes a mismatch between the expected value EXP and the test data TDO output from the circuit under test 1 at the address AD1, the fault information output unit 15A starts serial output of the fault diagnosis information DIAG at the address AD1. . On the other hand, in the test step count unit 11A, the step information STP is continuously updated to the address AD2, and the test is continued.

  If the mismatch between the expected value EXP and the test data TDO output from the circuit under test 1 occurs at the address AD3 while the failure diagnosis information DIAG at the address AD1 is being output, the test execution is interrupted. Then, when the output of the failure diagnosis information DIAG at the address AD1 is completed, the test resumption information RST specifying the address AD3 is output from the failure information output unit 15A to the test step count unit 11A. Thereby, the step information STP becomes a test step immediately before the test step stored in the failure information storage register, and the test operation is resumed.

  As described above, the memory BIST circuit according to the first embodiment includes the failure information output unit 15A including the failure information storage register for temporarily holding the state when the failure is found and outputting the failure diagnosis information DIAG. Have. Further, the failure information output unit 15A returns to the previous address and restarts the test when the output of the failure diagnosis information DIAG is completed when the next failure is found during the output of the failure diagnosis information DIAG. Test resumption information RST is output to the test step count unit 11A. As a result, the operation of the BIST and the output of the failure diagnosis information DIAG found in this test can be performed simultaneously, and there is an advantage that an increase in test time due to the output of the failure diagnosis information DIAG can be suppressed.

  Furthermore, even when a failure is detected during the output of the failure diagnosis information DIAG, the test can be resumed by returning to the address immediately before the failure detection without returning to the initial state. Thus, there are advantages that a duplicate test can be avoided and a test can be performed at an accurate timing.

  FIG. 6 is a configuration diagram of a memory BIST circuit showing Embodiment 2 of the present invention. Elements common to those in FIG. 1 are denoted by common reference numerals.

  This memory BIST circuit is provided with a failure information output unit 15B using a FIFO (First In First Out) buffer for storing failure information in place of the failure information output unit 15A in FIG. This is the same as FIG. The FIFO buffer is a buffer memory configured to be read in order from the previously written data, and has a feature that a plurality of data (in this case, data of a plurality of failure points) can be stored.

  FIG. 7 is a flowchart showing the processing flow of FIG. 6. Elements common to those in FIG. 4 are denoted by common reference numerals.

Processes P1 to P4 are the same as those in FIG.
In process P3, when the expected value EXP output from the expected value generating unit 13 and the test data TDO actually output from the circuit under test 1 are determined to be inconsistent by the comparing unit 14, the process proceeds to process P10, and failure information output is performed. Step information STP and the like of the test step determined to be inconsistent are written in the FIFO buffer in the unit 15B. After process P10, the process proceeds to process P11.

  In process P11, the state of the FIFO buffer is checked. If there is no free area, the process proceeds to process P12, and if there is a free area, the process proceeds to process P14.

  In process P12, step information STP and the like stored in the FIFO buffer are read out and serially output as failure diagnosis information DIAG. The output of the failure diagnosis information DIAG is repeated until the FIFO buffer becomes empty by the loop of process P13. When the FIFO buffer becomes empty, the process returns to process P2.

  On the other hand, when the process P11 proceeds to the process P14, the fault information output unit 15B is activated in the process P14, and the process immediately proceeds to the process P4. When the failure information output unit 15B is activated, the failure diagnosis information DIAG is output in parallel with the execution of the test operation by the BIST by the process P15. The output of the failure diagnosis information DIAG is repeated until the FIFO buffer becomes empty by the loop of process P16.

FIG. 8 is an explanatory diagram showing the operation during the test of FIG.
When the test execution causes a mismatch between the expected value EXP and the test data TDO output from the circuit under test 1 at the address AD1, the step information STP and the like of the address AD1 is written in the FIFO buffer of the failure information output unit 15B. On the other hand, in the test step count unit 11A, the step information STP is continuously updated to the address AD2, and the test is continued.

  The failure information output unit 15B reads the step information STP and the like written in the FIFO buffer by writing the step information STP and the like of the address AD1 in the FIFO buffer, and serially outputs the failure diagnosis information DIAG of the address AD1. Is started.

  If the mismatch between the expected value EXP and the test data TDO output from the circuit under test 1 occurs at the address AD3 while the failure diagnosis information DIAG at the address AD1 is being output, the step information STP and the like of the address AD3 is written to the FIFO buffer. It is. Here, the test execution is interrupted when there is no more free space in the FIFO buffer. When the failure diagnosis information DIAG at the address AD1 and the failure diagnosis information DIAG at the address AD3 are completely output, the test restart information RST specifying the address AD3 is output from the failure information output unit 15B to the test step count unit 11A. Is done. Thereby, the step information STP becomes a test step immediately before the test step stored in the failure information storage register, and the test operation is resumed.

  As described above, the memory BIST circuit of the second embodiment stores the step information STP corresponding to a plurality of addresses in order to temporarily hold the state when the failure is found and output it as the failure diagnosis information DIAG. It has a failure information output unit 15B having a FIFO buffer. As a result, in addition to the same advantages as in the first embodiment, even if a failure occurs at a plurality of addresses, as long as there is an empty area in the FIFO buffer, the test can be continued without interruption, and the failure diagnosis information DIAG There is an advantage that an increase in test time due to output can be further suppressed.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) The configuration of the memory BIST circuit is not limited to the block configuration illustrated in FIGS. 1 and 6.
(B) The flow of processing by the memory BIST circuit is not limited to that illustrated in FIGS. For example, in FIG. 7, after adding a test step to the FIFO buffer in process P10, the buffer state is checked in P11. Also good.
(C) The test resumption information RST output from the failure information output unit 15A to the test step count unit 11A specifies the test step immediately before the test step stored in the failure information storage register. Instead of the previous test step, the second or third previous test step may be designated. That is, the test resumption information RST may be an address before the failure detection address.

1 is a configuration diagram of a memory BIST circuit showing Embodiment 1 of the present invention. FIG. It is a block diagram of the conventional memory BIST circuit. FIG. 3 is an explanatory diagram illustrating an operation example during the test of FIG. 2. It is a flowchart which shows the processing flow of FIG. It is explanatory drawing which shows the operation | movement at the time of the test of FIG. It is a block diagram of the memory BIST circuit which shows Example 2 of this invention. It is a flowchart which shows the processing flow of FIG. It is explanatory drawing which shows the operation | movement at the time of the test of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Circuit under test 11A Test step count part 12 Test pattern generation part 13 Expected value generation part 14 Comparison part 15A, 15B Failure information output part 16 Selector 17 Diagnosis state flag

Claims (3)

A test step count unit that generates step information according to the comparison result signal, the test resumption information, and the diagnosis state information;
A test pattern generator for generating a test pattern to be applied to the circuit under test according to the step information;
An expected value generator for generating an expected value to be output from the circuit under test according to the step information;
A comparator for comparing the expected value with output data output from the circuit under test and outputting the comparison result signal;
Based on the step information, the test pattern, the comparison result signal, and the output data, the failure information of the circuit under test is captured and output as failure diagnosis information, and the processing state is output as the diagnosis state information, A failure information output unit for outputting the test resumption information after completion of the output of the failure diagnosis information;
A built-in memory test circuit characterized by comprising:   2. The embedded memory according to claim 1, wherein the test resumption information is information indicating a step preceding the step information corresponding to the failure information of the circuit under test taken in by the failure information output unit. Test circuit.   3. The embedded memory test circuit according to claim 1, wherein the failure information output section has a first-in first-out buffer for storing a plurality of pieces of failure information of the circuit under test.

Images