JP2008217687A - Branch prediction device and branch prediction method using local branch history - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dynamic branch prediction device capable of generating a more precise branch prediction result in a short time. <P>SOLUTION: The dynamic branch prediction device 100 is provided with: a local branch history table 102 for holding a local branch history related to each branch instruction; a performance completion branch instruction address 109; a plurality of index calculation circuits 103 for calculating indices respectively according to the performance completion branch instruction address 109 and a local branch history read from the local branch history table 102; a plurality of pattern history tables 104 for obtaining prediction results by using the indices calculated by the index calculation circuits 103; a branch prediction result operation circuit 105 for calculating total outputs of the pattern history table 104 and outputting its sum as a branch prediction result; and a branch prediction cache memory 108 for storing the branch prediction result. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a branch prediction apparatus and a branch prediction method using a local branch history.

  So far, many devices for performing dynamic branch prediction using local branch history have been proposed. FIG. 4 is a block diagram showing a configuration of a conventional dynamic branch prediction apparatus using such a local branch history.

  As shown in FIG. 4, the conventional dynamic branch prediction apparatus 200 includes a local branch history table 202, an index calculation circuit 203, a pattern history table 204, and a branch prediction result calculation circuit 205.

  The local branch history table 202 holds a local branch history regarding each branch instruction.

  The index calculation circuit 203 calculates an index from the branch instruction address 201 and the local branch history read from the local branch history table 202.

  The turn history table 204 obtains a prediction result using the index calculated by the index calculation circuit 203.

  The branch prediction result calculation circuit 205 calculates the sum of the outputs of the pattern history table 204 and outputs the sum as a branch prediction result 206.

As described above, in the conventional dynamic branch prediction apparatus 200, the branch prediction result 206 is calculated using the single pattern history table 204.
JP 2001-014162 A (FIG. 1) JP 2000-132391 A (FIG. 1) JP 2005-032024 A

  However, the conventional dynamic branch prediction apparatus 200 using the local branch history has the following problems.

  The first problem is that the branch prediction result 206 cannot be generated in a sufficiently short time because it is necessary to access two tables, the local branch history table 202 and the pattern history table 204.

  The second problem is that branch prediction is performed using a single pattern history table 204, so that a sufficiently advanced branch prediction result 206 cannot be generated.

  The present invention has been made in view of the problems in the conventional dynamic branch prediction apparatus 200 as described above, and can generate a highly accurate branch prediction result in a sufficiently short time. An object is to provide a prediction device and a dynamic branch prediction method.

  To achieve the above object, the present invention provides an index based on a local branch history table that holds a local branch history for each branch instruction, an execution completion branch instruction address, and a local branch history read from the local branch history table. Using at least two index calculation circuits for calculating each of the above, the index calculated by the index calculation circuit, at least one pattern history table for obtaining a prediction result, and calculating the sum of the outputs of the pattern history table, There is provided a dynamic branch prediction apparatus comprising a branch prediction result calculation circuit that outputs a sum as a branch prediction result, and a branch prediction cache memory that stores the branch prediction result.

  The dynamic branch prediction apparatus according to the present invention can include the same number of pattern history tables as the index calculation circuit. In this case, each of the pattern history tables corresponds to each of the index calculation circuits, and each of the pattern history tables independently uses the index calculated by the corresponding index calculation circuit. It is preferable that the prediction result is obtained.

  The index calculation circuits preferably use different branch history lengths.

  The branch history length is represented by the following equation, for example.

L (j) = L (1) · α ^(j−1)
L (j): Branch history length of the j-th index calculation circuit L (1): Constant exceeding 1: Constant exceeding α: 1 The branch prediction result is stored in the branch prediction cache memory using the execution completion branch instruction address as a key. Preferably it is stored.

  The branch prediction result is preferably read from the branch prediction cache memory using a prediction target branch instruction address as a key.

  The contents of the local branch history table and the pattern history table are preferably updated according to the execution result of the branch instruction that has been executed.

  The present invention further calculates an index from a local branch history table holding a local branch history for each branch instruction, an execution completion branch instruction address, and an arbitrary local branch history read from the local branch history table. A dynamic branch prediction apparatus comprising: a branch predictor that obtains a branch prediction result using the index; and a branch prediction cache memory that stores the branch prediction result.

  The branch prediction cache memory can be composed of, for example, a 1-read 1-write SRAM.

  The present invention further includes a first step of calculating an index from an execution completion branch instruction address and a local branch history for each branch instruction in at least two index calculation circuits for calculating the index, respectively, Using each of the indexes calculated in the process of (2), a second process for obtaining each prediction result independently of each other, a sum of outputs in the second process, and calculating the sum as a branch prediction result A dynamic branch prediction method comprising: a third process for outputting; and a fourth process for storing the branch prediction result output in the third process.

  The present invention is further a program for causing a computer to execute the dynamic branch prediction method, and the processing performed by the program is executed by an execution completion branch instruction address in at least two index calculation circuits that respectively calculate indexes. A first process for calculating each index from the local branch history for each branch instruction, and a second for obtaining each prediction result independently of each other using each of the indexes calculated in the first process. A fourth process for calculating the sum of outputs in the second process, outputting the sum as a branch prediction result, and storing the branch prediction result output in the third process. And a program comprising the following processes.

  In the dynamic branch prediction apparatus according to the present invention, the branch prediction result is calculated in advance, and the calculated branch prediction result is stored in the branch prediction cache memory. The branch prediction result is read directly from the branch prediction cache memory using the prediction target branch instruction address as a key. For this reason, it is possible to reduce the latency of branch prediction.

  In the dynamic branch prediction apparatus according to the present invention, a branch prediction result is calculated using a plurality of pattern history tables. For this reason, compared with the conventional dynamic branch prediction apparatus 200 (refer FIG. 4) which calculated the branch prediction result using the single pattern history table 204, a more highly accurate branch prediction result can be produced | generated. Is possible.

(First embodiment)
FIG. 1 is a block diagram showing the structure of a dynamic branch prediction apparatus 100 according to the first embodiment of the present invention.

  The dynamic branch prediction apparatus 100 according to the present embodiment is used by being mounted on, for example, a central processing unit.

  The dynamic branch prediction apparatus 100 according to the present embodiment includes a local branch history table 102, N (N is a positive integer greater than or equal to 2) index calculation circuits 103, and N index calculation circuits 103 each. N pattern history tables 104, a branch prediction result calculation circuit 105, and a branch prediction cache memory 108.

  The local branch history table 102 holds a local branch history related to each branch instruction with the execution completion branch instruction address 109 as a key.

  The execution completion branch instruction address 109 represents the address of the branch instruction that has been executed and is to be updated.

  Each of the N index calculation circuits 103 is an index for the pattern history table 104 corresponding to each of the N index calculation circuits 103 from the execution completion branch instruction address 109 and the local branch history read from the local history table 104. Calculate

  Each index calculation circuit 103 uses a different branch history length, and the branch history length used by each index calculation circuit 103 is expressed by the following equation.

L (j) = L (1) · α ^(j−1)
L (j): Branch history length of the jth index calculation circuit L (1): Constant exceeding 1 α: Constant exceeding 1: Each of the N pattern history tables 104 is calculated by the index calculation circuit 103 corresponding thereto. Using the index, the prediction result is obtained independently. The obtained prediction result is output to the branch prediction result calculation circuit 105.

  The branch prediction result calculation circuit 105 takes the sum of the outputs from each pattern history table 104 and outputs the sum as a branch prediction result 106.

  The branch prediction result 106 output from the branch prediction result calculation circuit 105 is stored in the branch prediction cache memory 108.

  FIG. 2 is a block diagram showing an example when the dynamic branch prediction apparatus 100 according to the present embodiment is configured using a central processing unit (CPU).

  The dynamic branch prediction apparatus 100 includes a central processing unit (CPU) 120, a first memory 121, a first memory 122, an input interface 123 for inputting various instructions and data to the central processing unit 120, and a central processing unit. The output interface 124 outputs the result of the processing executed by the apparatus 120, and the bus 125 connects the central processing unit 120 and other components.

  Each of the first and second memories 121 and 122 may be a read only memory (ROM), a random access memory (RAM) or a semiconductor storage device such as an IC memory card, a storage medium such as a flexible disk, a hard disk, or It consists of an optical magnetic disk. For example, the first memory 121 is a ROM, and the second memory 122 is a RAM.

  The first memory 121 stores various control programs and other fixed data to be executed by the central processing unit 120. The second memory 122 stores various data and parameters, and provides an operating area for the central processing unit 120, that is, data temporarily required for the central processing unit 120 to execute a program. Storing. The central processing unit 120 reads a program from the first memory 121 and executes the program. That is, the central processing unit 120 operates according to a program stored in the first memory 121.

  As shown in FIG. 2, the central processing unit 120 and the first and second memories 121 and 122 functionally include a local branch history table 102, an index calculation circuit 103, a pattern history table 104, and a branch prediction. A result calculation circuit 105 and a branch prediction cache memory 108 are configured.

  The contents of the local branch history table 102 and the pattern history table 104 are updated based on a branch instruction execution result 107 obtained from a branch instruction unit (not shown) of a central processing unit (not shown). The branch instruction execution result 107 represents the execution result of the branch instruction that has been executed. By using the updated contents of the local branch history table 102 and the pattern history table 104, each pattern history table 104 calculates the next branch prediction result.

  The branch prediction results calculated in each pattern history table 104 are all added in the branch prediction result calculation circuit 105. This addition result is stored in the branch prediction cache memory 108 as a branch prediction result.

  The branch prediction cache memory 108 stores the sum of the branch prediction results calculated by the branch prediction result calculation circuit 105 using the execution completion branch instruction address 109 as a key.

  When the branch prediction result is read from the branch prediction cache memory 108, the branch prediction result is read from the branch prediction cache memory 108 using the prediction target branch instruction address 101 as a key. A prediction target branch instruction address 101 represents an address of a branch instruction to be predicted.

  For example, the branch prediction cache memory 108 can be composed of a 1-read 1-write SRAM (Static Random Access Memory).

  Hereinafter, an operation of the dynamic branch prediction apparatus 100 according to the present embodiment, that is, a prediction procedure and a data update procedure will be described.

  First, the prediction procedure will be described.

  In the central processing unit in which the dynamic branch prediction device 100 according to the present embodiment is mounted, when a branch instruction is fetched from the memory, the branch instruction address 101 is used as a key, and the value is read from the branch prediction cache memory 108. Is read.

  The value read from the branch prediction cache memory 108 becomes the branch prediction result 106 generated by the dynamic branch prediction apparatus 100 according to the present embodiment.

  Next, the update procedure will be described.

  First, whether or not each pattern history table 104 needs to be updated is calculated using the following equation (1).

Predicted value × X <θ (1)
Predicted value: predicted value generated at the time of prediction X: 1 when the branch instruction execution result 107 is Taken, -1 when the branch instruction execution result 107 is not Taken
θ: When the value of the threshold value (predicted value × X) is smaller than θ, that is, when Expression (1) is satisfied, it is determined that there is no need to update each pattern history table 104.

  Conversely, if the value of (predicted value × X) is not smaller than θ, that is, if equation (1) is not satisfied, it is determined that each pattern history table 104 needs to be updated. .

  When it is determined that each pattern history table 104 needs to be updated, when execution of the branch instruction is completed in the central processing unit equipped with the dynamic branch prediction apparatus 100 according to the present embodiment, Each pattern history table 104 is updated using the branch instruction execution result 107 and the execution completion branch instruction address 109.

  Specifically, each pattern history table 104 is updated as follows.

  First, in the local branch history 102 immediately before the update, the branch history immediately before the update is obtained using the execution completion branch instruction address 109, and at the same time, the entry is shifted by one bit. The branch instruction execution result 107 is inserted into one bit vacated by this shift.

  Next, each index calculation circuit 103 is used to calculate the branch history immediately before the update and the hash value of the execution completion branch instruction address 109 (hereinafter referred to as “first hash value”).

  Similarly, each index calculation circuit 103 is used to calculate the branch history immediately after the update and the hash value of the execution completion branch instruction address 109 (hereinafter referred to as “second hash value”).

  When the calculation result of Expression (1) is true, the value of the entry indicated by the first hash value in the pattern history table 104 is +1 if the prediction direction is true, and -1 if not true.

  A value is read from the entry indicated by the second hash value in the pattern history table 104.

  The branch prediction result calculation circuit 105 calculates the sum of a plurality of integer values read from the entry indicated by the second hash value in the pattern history table 104, and outputs this as a branch prediction value.

  The branch prediction value output from the branch prediction result calculation circuit 105 is stored in an entry in the branch prediction cache memory 108 that is designated by the execution completion branch instruction address 109.

  According to the dynamic branch prediction apparatus 100 according to the present embodiment, the following effects can be obtained.

  In the dynamic branch prediction apparatus 100 according to the present embodiment, the branch prediction result is calculated in advance, and the calculated branch prediction result is stored in the branch prediction cache memory 108. For this reason, as a first effect, according to the dynamic branch prediction apparatus 100 according to the present embodiment, it is possible to reduce the latency of branch prediction.

  In the dynamic branch prediction apparatus 100 according to the present embodiment, a branch prediction result is calculated using N (N is a positive integer of 2 or more) pattern history tables 104. For this reason, as a second effect, the branch is more accurate than the conventional dynamic branch prediction apparatus 200 (see FIG. 4) that calculates the branch prediction result using the single pattern history table 204. It is possible to generate prediction results.

  Note that by using the dynamic branch prediction apparatus 100 according to the present embodiment, the accuracy of branch prediction can be improved by 8% or more compared to the conventional dynamic branch prediction apparatus 200 (see FIG. 4). It was.

  The dynamic branch prediction apparatus 100 according to the present embodiment is not limited to the above configuration, and various modifications can be made.

  For example, the dynamic branch prediction apparatus 100 according to the present embodiment is configured to have the same number N pattern history tables 104 as the index calculation circuit 103, but instead of the N pattern history tables 104, It is also possible to configure as having a single pattern history table 104. When the dynamic branch prediction apparatus 100 according to the present embodiment has a single pattern history table 104, branch prediction results are sequentially predicted from the single pattern history table 104 corresponding to each index calculation circuit 103. The result is output to the salt mountain circuit 105, and the branch prediction result calculation circuit 105 calculates the sum of these outputs.

  Further, the plurality of index calculation circuits 103 can be configured as an index calculation circuit using exclusive OR, or can be realized by simply connecting the plurality of index calculation circuits 103 to each other by bit connection or the like. You can also.

(Second embodiment)
FIG. 3 is a block diagram showing the structure of the dynamic branch prediction apparatus 300 according to the second embodiment of the present invention.

  The dynamic branch prediction apparatus 300 according to the present embodiment is mounted and used in, for example, a central processing unit, similarly to the dynamic branch prediction apparatus 100 according to the first embodiment.

  The dynamic branch prediction apparatus 300 according to the present embodiment includes a local branch history table 302, a branch predictor 303, and a branch prediction cache memory 308.

  The local branch history table 302 has the same configuration and function as the local branch history table 102 in the dynamic branch prediction apparatus 100 according to the first embodiment.

  The branch prediction cache memory 308 has the same configuration and function as the branch prediction cache memory 108 in the dynamic branch prediction apparatus 100 according to the first embodiment.

  The dynamic branch prediction apparatus 300 according to the present embodiment has N index calculation circuits 103, N pattern history tables 104, and branch prediction results as compared with the dynamic branch prediction apparatus 100 according to the first embodiment. Instead of the arithmetic circuit 105, a branch predictor 303 is provided.

  The branch predictor 303 has a function of performing branch prediction using an arbitrary local branch history among the local branch histories stored in the local branch history table 302. That is, the branch predictor 303 has functions equivalent to the N index calculation circuits 103, the N pattern history tables 104, and the branch prediction result calculation circuit 105 in the dynamic branch prediction apparatus 100 according to the first embodiment. is doing.

  The branch prediction result output from the branch predictor 303 is stored in the branch prediction cache memory 308 using the execution completion branch instruction address 309 as a key.

  According to the dynamic branch prediction apparatus 300 according to the present embodiment, the same effects as those of the dynamic branch prediction apparatus 100 according to the first embodiment can be obtained, and the prediction latency of branch prediction can be further reduced. Is possible.

  The dynamic branch prediction apparatus according to the present invention can be mounted on, for example, a central processing unit that requires high performance calculation.

It is a block diagram which shows the structure of the dynamic branch prediction apparatus which concerns on 1st embodiment of this invention. It is a block diagram which shows an example at the time of comprising the dynamic branch prediction apparatus which concerns on 1st embodiment of this invention using a central processing unit (CPU). It is a block diagram which shows the structure of the dynamic branch prediction apparatus which concerns on 2nd embodiment of this invention. It is a block diagram which shows the structure of the conventional dynamic branch prediction apparatus.

Explanation of symbols

100 dynamic branch prediction apparatus 101 according to first embodiment of the present invention 101 prediction target branch instruction address 102 local branch history table 103 index calculation circuit 104 pattern history table 104
105 Branch prediction result calculation circuit 106 Branch prediction result 107 Branch instruction execution result 108 Branch prediction cache memory 109 Execution completion branch instruction address 120 Central processing unit (CPU)
121 first memory 122 second memory 123 input interface 124 output interface 300 dynamic branch prediction apparatus 302 local branch history table 303 branch predictor 308 branch prediction cache memory according to the second embodiment of the present invention

Claims (11)

A local branch history table that holds the local branch history for each branch instruction;
At least two index calculation circuits each for calculating an index from an execution completion branch instruction address and a local branch history read from the local branch history table;
Using the index calculated by the index calculation circuit, at least one pattern history table for obtaining a prediction result;
A branch prediction result calculation circuit that calculates a sum of outputs of the pattern history table and outputs the sum as a branch prediction result;
A branch prediction cache memory for storing the branch prediction result;
A dynamic branch prediction apparatus comprising:   The same number of pattern history tables as the index calculation circuits are provided, each of the pattern history tables corresponds to each of the index calculation circuits, and each of the pattern history tables is calculated by the corresponding index calculation circuit. The dynamic branch prediction apparatus according to claim 1, wherein each prediction result is obtained independently using the index.   3. The dynamic branch prediction apparatus according to claim 2, wherein each of the index calculation circuits uses different branch history lengths. The dynamic branch prediction apparatus according to claim 3, wherein the branch history length is expressed by the following equation.
L (j) = L (1) · α ^(j−1)
L (j): Branch history length of the j-th index calculation circuit L (1): constant exceeding 1; constant exceeding α: 1   5. The dynamic branch prediction apparatus according to claim 1, wherein the branch prediction result is stored in the branch prediction cache memory using the execution completion branch instruction address as a key.   6. The dynamic branch prediction apparatus according to claim 5, wherein the branch prediction result is read from the branch prediction cache memory using a prediction target branch instruction address as a key.   7. The dynamic branch prediction apparatus according to claim 1, wherein contents of the local branch history table and the pattern history table are updated according to an execution result of a branch instruction that has been executed. . A local branch history table that holds the local branch history for each branch instruction;
A branch predictor that calculates an index from an execution completion branch instruction address and an arbitrary local branch history read from the local branch history table and obtains a branch prediction result using the index;
A branch prediction cache memory for storing the branch prediction result;
A dynamic branch prediction apparatus comprising:   9. The dynamic branch prediction apparatus according to claim 1, wherein the branch prediction cache memory is composed of a 1-read 1-write SRAM. A first step of calculating an index from each of the execution completion branch instruction address and the local branch history for each branch instruction in at least two index calculation circuits each calculating an index;
Using each of the indices calculated in the first step, a second step for obtaining each prediction result independently of each other;
Calculating a sum of outputs in the second step, and outputting the sum as a branch prediction result;
A fourth step of storing the branch prediction result output in the third step;
A dynamic branch prediction method comprising: A program for causing a computer to execute a dynamic branch prediction method,
The processing performed by the program is as follows:
In at least two index calculation circuits each calculating an index, a first process for calculating an index from an execution completion branch instruction address and a local branch history for each branch instruction,
A second process for obtaining each prediction result independently of each other using each of the indexes calculated in the first process;
Calculating a sum of outputs in the second process, and outputting the sum as a branch prediction result;
A fourth process for storing the branch prediction result output in the third process;
A program that consists of:

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