JP2011141619A - Microprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently compare a preceding input value and this-time input value, in a microprocessor skipping execution of some processing according to a comparison result between the preceding input value and this-time input value of the processing. <P>SOLUTION: The microprocessor 100 includes: a main memory 110 provided with an evacuation area 112 storing a value of a register a; a cache memory 120; and a flag 180 having first and second status. The microprocessor 100 copes with a flag reset instruction, a flag setting-equipped memory read instruction, a flag setting-equipped memory write instruction, a flag setting-equipped register setting instruction, and a flag reference-equipped branch instruction. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a microprocessor.

  In recent years, microprocessors have been widely used in various fields, and attempts have been made to improve the microprocessors from various viewpoints.

  For example, the technique disclosed in Patent Document 1 creates a code at the time of a cache miss and a cache hit, and branches to a corresponding code when a cache miss or a cache hit occurs. According to this technique, it is said that the efficiency of the combine can be improved.

  Further, the technique disclosed in Patent Document 2 provides a history storage in a CPU (in a general-purpose arithmetic unit, a floating-point arithmetic unit, etc.), and for each instruction that has already been executed, input of arithmetic and result data, The main memory read / write address and data are stored in the history memory. When the same instruction (calculation instruction or read / write instruction) is executed again, execution of the calculation or read / write is skipped according to the contents of the history storage. Specifically, when executing an arithmetic instruction, the current input data is stored in the history storage, and the input data of the arithmetic instruction in the past is compared. Skip execution. When a read / write instruction is executed, the current read / write address is compared with the read / write address stored in the history storage. If they are the same, the read / write is executed. skip. By doing so, it is said that instruction execution time can be shortened and load / store operations for main memory can be suppressed. In addition, when registering an instruction in the instruction queue, the presence / absence of corresponding history information is registered in the V field when the instruction is registered in the instruction queue in order to shorten the time for determining the presence / absence of history information corresponding to the executed instruction. To do. Then, when executing an instruction in the instruction queue, the V field is referred to, and if there is corresponding history information, the above-described comparison is performed.

Japanese Patent Laid-Open No. 10-91455 Republished patent WO98 / 11484

  Of the processes performed by the microprocessor, an input value of a certain process (referred to as process B) may be an execution result of another process (referred to as process A). In this case, for example, the method of Patent Document 2 can be applied as in the flow shown in FIG. For ease of understanding, as an example, only one instruction (instruction A) is executed in process A, and only one instruction (instruction B) is executed in process B.

  A history storage is provided in the CPU, and a history storage for storing the input value of the instruction B executed in the past and the execution result in association with each other is provided. When the current input value of the command B is obtained by executing the command A (S10), the previous input value and the execution result of the command B stored in the history storage are read, and the previous input value and the current input value are read. Are compared (S12, S14). As a result of the comparison, if there is an input value that is the same as the current input value among the previous input values (S14: Yes), execution of the instruction B is skipped. On the other hand, if there is no input value that is the same as the current input value, the current input value is added to the history storage and the command B is executed (S14: No, S16, S18). Then, the current execution result of the instruction B is added to the history storage (S20).

  As can be seen from the flow shown in FIG. 16, in this method, it is necessary to compare with a past input value every time the instruction B is executed. As described in Patent Document 2, when registering an instruction in the instruction queue, even if the history information corresponding to the instruction is described in the V field of the history storage, Only the presence / absence of history information corresponding to the command can be known, and the comparison cannot be omitted.

  One embodiment of the present invention is a microprocessor. The microprocessor includes a main memory, a cache memory, and a flag having first and second statuses.

  This microprocessor includes a memory read instruction with a flag setting, which is a memory read instruction accompanied by the setting of the flag, and a register setting instruction that obtains data by other than the memory read and sets the data in a register together with the setting of the flag. It corresponds to a register setting instruction with a flag setting, a write instruction with a flag setting which is a memory write instruction with the setting of the flag, a flag reset instruction, and a flag reference branch instruction.

  The microprocessor sets the flag to the first status according to the flag reset instruction.

  In addition, when reading is performed according to a memory read instruction with a flag set, a cache miss occurs at the time of reading, and the read address is an address in a non-cache area, and the read data is different from the cache data corresponding to the read address The flag is set to the second status.

  Further, writing is performed according to the memory write instruction with flag setting, and the flag is set to the second status when a cache miss occurs during writing and when the cache data corresponding to the write address and the write data are different.

  Further, according to the register setting instruction with flag setting, the data obtained this time is compared with the register value set by the previous execution of the instruction, and the flag is set to the second status only when they do not match. At the same time, the value of the register is updated with the data obtained this time.

  Also, according to the branch instruction with flag reference, the flag is referred to. When the flag is in the first status, the branch is made to the specified branch destination, and when the flag is in the second status, the next instruction is executed. To do.

  Note that a representation in which the microprocessor of the above aspect is replaced with a method or system, a program that causes a computer to execute a part of the processing of the microprocessor, an apparatus including the microprocessor, and the like are also effective as an aspect of the present invention. It is.

  According to the technology of the present invention, input values can be compared efficiently in a microprocessor that skips execution of the process according to a comparison result between an input value before a certain process and the current input value. .

It is a figure which shows the microprocessor concerning the 1st Embodiment of this invention. 2 is a flowchart for executing a memory write instruction with a flag set by the microprocessor shown in FIG. 1. 3 is a flowchart for executing a memory read instruction with a flag set by the microprocessor shown in FIG. 1. FIG. 3 is a flowchart in which the microprocessor shown in FIG. 1 executes a register setting instruction with flag setting. 2 is a flowchart for executing a branch instruction with a flag reference by the microprocessor shown in FIG. It is a figure which shows the process example. 7 is an instruction code for executing the processing shown in FIG. 6 by the microprocessor shown in FIG. 8 is a flowchart in which the microprocessor shown in FIG. 1 executes the instruction code shown in FIG. FIG. 8 is a diagram showing a state transition of each component accompanying execution of the instruction code shown in FIG. 7 (No. 1). FIG. 8 is a diagram showing state transition of each component accompanying execution of the instruction code shown in FIG. 7 (No. 2). It is a figure which shows an example of the instruction code in the case of implement | achieving the process example shown in FIG. 6 by the method different from this invention. It is a figure which shows the transition of each component accompanying execution of the instruction code shown in FIG. It is a figure which shows another example of the instruction code in the case of implement | achieving the process example shown in FIG. 6 with the method different from this invention. It is a figure which shows the state transition of each component accompanying execution of the instruction code shown in FIG. 13 (the 1). It is a figure which shows the state transition of each component accompanying execution of the instruction code shown in FIG. 13 (the 2). It is a figure for demonstrating the problem of the method of patent document 2. FIG.

  Embodiments of the present invention will be described below with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Each element described in the drawings as a functional block for performing various processes can be configured by a CPU, a memory, and other circuits in terms of hardware, and a program loaded in the memory in terms of software. Etc. Note that, in each drawing, the same element is denoted by the same reference numeral, and redundant description is omitted as necessary.

  FIG. 1 shows a microprocessor 100 according to a first embodiment of the present invention. The microprocessor 100 includes a main memory 110, a cache memory 120, a memory I / O 130, a CPU 140, a register group 150, and a bus 190.

  The CPU 130 includes components (not shown) such as an instruction control unit that controls instructions, a branch operation unit that performs branch operations, a general-purpose operation unit that executes fixed-point instructions and load / store instructions, and a floating-point operation unit that executes floating-point operations. Is provided. The CPU 140 directly accesses each register in the register group 150, and transfers data and instructions to / from the main memory 110, the cache memory 120, and the memory I / O 130 via the bus 190.

  The register group 150 includes a plurality of registers (registers a, b, c,...) And a flag register 180.

  In the following description, for convenience of explanation, the flag register 180 is referred to as a flag 180, and the term “register” simply refers to a register other than the flag 180.

  The main memory 110 is provided with a save area 112 for saving register values.

The microprocessor 100 is different from a normal microprocessor including a cache memory in the following points.
(1) It has a flag 180.
(3) The CPU 140 corresponds to the following five commands:
Flag reset instruction, memory read instruction with flag setting, memory read instruction with flag setting, register setting instruction with flag setting, branch instruction with flag reference.

  The status of the flag 180 is set by the CPU 140. The flag register 180 has two statuses “same” or “different”. For example, a value “0” indicates a “same” status, and a value “1” indicates a “different” status.

  The flag reset command is a command for resetting the status of the flag 180. In response to this instruction, the CPU 140 sets the status of the flag 180 to a predetermined one of the two statuses. In the present embodiment, as an example, the CPU 140 sets the status of the flag 180 to “0” (same) in response to the flag reset command.

  The memory write instruction with flag setting is a memory write instruction with the setting of the flag 180. In response to this command, the CPU 140 may set the flag 180 in addition to the normal memory write process. FIG. 2 is an example of a flowchart in which the CPU 140 executes this command.

  When executing the memory write command with flag setting, the CPU 140 sets the status of the flag 180 to a status different from the status set by the flag reset command, that is, “1” (different) in two cases. One is a cache miss (S100: Yes), and the other is not a cache miss, but the cache data corresponding to the write address is different from the write data (S100: No, S108: No). ).

  As shown in FIG. 2, in the above two cases, the CPU 140 sets the flag 180 to “1” and updates the cache data and writes to the main memory 110 (S102, S104, S106). Specifically, when the data of the write address is not stored in the cache memory 120, the cache data is updated by adding the data of the write address to the cache memory 120 and changing the write address of the write address stored in the cache memory 120. When the data and the write data are different, the write address data stored in the cache memory 120 is replaced with the write data.

  Except for the above two cases (S100: No, S108: Yes), the CPU 140 executes normal memory write and does not set the flag 180.

  The memory read instruction with flag setting is a memory read instruction with the setting of the flag 180. In response to this command, the CPU 140 may set the flag 180 in addition to the normal memory read process. FIG. 3 is an example of a flowchart in which the CPU 140 executes this command.

  When executing the memory read command with flag setting, the CPU 140 sets the status of the flag 180 to “1” (different) in two cases. One is an address in which the read address indicates a non-cache area including the memory I / O 130, and the data read to the memory I / O 130 is different from the cache data corresponding to the read address (S110: Yes, S112, S114). : No). The other is a case of a cache miss (S110: No, S120: Yes).

  As shown in FIG. 3, in the above two cases, the CPU 140 updates the cache data corresponding to the read address and sets the flag 180 to “1” (S116, S118). Then, the cache data is set in the register designated by the read instruction (S122).

  In cases other than the above two cases (S110: No, S120: No), the CPU 140 executes a normal memory read, and sets the cache data corresponding to the read address in the register designated by the read instruction (S122). In this case, the CPU 140 does not set the flag 180.

  The “register setting instruction” in the description of the present invention means an instruction for obtaining data by other than memory reading and setting the data in a register. For example, data is obtained from a register assigned as a register variable and set in the register to be set, or data obtained by performing some operation on the value stored in another register is set in the register to be set. It is a command to set. The register setting instruction with flag setting is a register setting instruction with setting of the flag 180. In response to this instruction, the CPU 140 may set the flag 180 in addition to the processing corresponding to the register setting instruction described above. FIG. 4 is an example of a flowchart in which the CPU 140 executes this command.

  When executing the register setting instruction with flag setting, the CPU 140 compares the data obtained this time with the register value (register stored value) set by the previous execution of the instruction, and only when they do not match The flag 180 is set to “1” (different), and the value of the register is updated with the data obtained this time (S130: No, S132, S134). If the register saved value and the data obtained this time are the same, the CPU 140 proceeds to the next instruction without setting the flag 180 and the register.

  The branch instruction with flag reference is an instruction that performs either a branch to a branch destination specified by the instruction or execution of the next instruction according to the status of the flag 180. FIG. 5 is a flowchart in which the CPU 140 executes this command.

  The CPU 140 first refers to the flag 180 when executing this instruction. When the flag 180 is one of the two statuses set according to the flag reset instruction (“0” (same) in the present embodiment) (S140: Yes), the CPU 140 determines the designated branch destination. Branch to (S142).

  On the other hand, when the flag 180 is different from the status set according to the flag reset instruction in step S140 (S140: No), the CPU 140 executes the next instruction without branching to the designated branch destination.

  According to such a configuration of the microprocessor 100, the process B is skipped before the execution of the second process (hereinafter referred to as process B) using the process result of the first process (hereinafter referred to as process A) as an input value. Whether or not to do so can be determined as follows.

  First, a flag reset instruction is executed before execution of process A. Thereby, the flag 180 is set to “0” (same).

  Then, each instruction of process A is executed. Among the instructions of process A, if a memory read instruction with a flag setting is used for a read instruction, a memory write instruction with a flag setting is used for a write instruction, and a register setting instruction with a flag setting is used for an instruction with a register setting, The status of the flag 180 indicates whether or not the current processing result of the processing A and the previous processing result are the same when the execution of A is completed. Since the process B uses the process result of the process A as an input value, the status of the flag 180 indicates whether or not the current input value and the previous input value of the process B are the same.

  For example, the process A is a process for executing an instruction with a flag setting of a register setting instruction that adds the value of the register a and the value of the register b and stores the result in the register c, and the process B uses the value of the register c as an input value. CPU 140 adds the values of registers a and b to obtain a sum, and compares this sum with the processing result of the previous process A stored in register c. If they match, the process proceeds to the next instruction without setting the register c and the flag 180. If they do not match, the flag 180 is set to “1” (different) and the value of the register c is newly obtained. Update with the sum.

  Further, for example, when the process A is a process of reading data from a predetermined read address to the register a, and the process B is a process using the value of the register a as an input value, the CPU 140 performs a memory read and performs a cache miss. And the cache corresponding to the read address when the read address is an address indicating a non-cache area including the memory I / O 130 and the data read to the memory I / O 130 is different from the cache data corresponding to the read address. The data is updated and the flag 180 is set to “1”. Then, the cache data is set in the register a. In other cases, the CPU 140 executes normal memory read and sets the cache data corresponding to the read address in the register a.

  The processing result of processing B is stored using the save area 112. The update of the process result of process B in the save area 112 is performed only when process B is executed. Before the process B, a branch instruction with a flag reference is executed. If the flag 180 is “0”, the process B is skipped. When the process result of process B is used later, the process result of process B may be read from the save area 112. Of course, the processing result of processing B may be read from the save area 112 before the branch instruction with flag reference to prepare for the subsequent processing.

  By doing this, when execution of the process A is completed, the flag 180 becomes a status indicating whether or not the process B is skipped, so that it is not necessary to save the input value of the process B, and memory consumption is suppressed. be able to. Furthermore, since the comparison of the input value of the process B is performed during the execution of the process A, the efficiency is high.

  In addition, the read / write instruction with flag setting is used for the memory read / write instruction included in the process A, and the status of the flag 180 is set according to the cache hit / miss or the comparison result between the read data or the write data and the cache data. It's so easy.

  Hereinafter, a detailed processing example shown in FIG. 6 will be described in detail. In the following description and illustration, “MEM + number” means a read address or a write address. For the sake of brevity, the area indicated by the address may be indicated by “MEM + number” under the assumption that no misunderstanding occurs.

  The processing example illustrated in FIG. 6 is processing for dividing the value stored in “MEM1” by the value stored in “MEM2” and storing the division result in the register c. As shown in FIG. 6, this processing can be divided into processing A and processing B. The process A is a process of reading the values stored in “MEM1” and “MEM2” into the register b and the register c, respectively. The process B divides the value of the register b by the value of the register c, and the division result is obtained. This is a process of storing in the register a.

  FIG. 7 shows instruction codes executed by the microprocessor 100 in order to realize the processing shown in FIG. The instructions on each line in FIG. 7 will be described.

  The first line is a flag reset instruction. By executing this instruction, the status of the flag 180 is set to “0” (same).

  The second line is a memory read instruction with a flag setting for reading the value stored in “MEM1” to the register b. This command is executed in the flowchart shown in FIG.

  The third line is also a memory read instruction with a flag setting for reading the value stored in “MEM2” to the register c. This command is also executed in the flowchart shown in FIG.

  Here, the process A is completed. If a cache miss occurs when “MEM1” and “MEM2” are read during execution of process A, or if the read data is different from the cache data, the flag 180 is changed to “different”.

  After the process A and before the process B, the instructions in the fourth and fifth lines are executed. The fourth line is a memory read instruction for reading the value stored in “MEM5” to the register a. As can be seen from the description below, [MEM5] is the address of the save area 112 that stores the result of the process B. This instruction is provided for subsequent processing using the processing result of processing B when processing B is skipped, and does not need to be flagged. Note that the timing of the instruction on the fourth line is not limited to immediately after the process A, but the post-process using the process result of the process B, excluding the branch instruction with flag reference on the fifth line and each instruction of the process B. It may be any previous timing.

  The fifth line is a branch instruction with a flag reference. This command is executed in the flowchart shown in FIG. Specifically, when the flag 180 is “0” (same), a branch is made to the designated branch destination (the eighth line in this case), and from the next instruction to the instruction immediately before the branch destination. The execution of each instruction (in this case, instructions in the sixth to seventh lines) is skipped. On the other hand, when the flag 180 is “1”, the branch is not performed and the next instruction is executed.

  The sixth line is an instruction that divides the value of the register b by the value of the register c and stores the division result in the register a. Processing B is executed by this instruction.

  The seventh line is an instruction to write the value of the register a to “MEM5”. “MEM5” is a save area 112 for storing the value of the register a. In the present embodiment, since the flag reset instruction is always executed before reading the values stored in “MEM1” and “MEM2”, the write instruction includes the memory write instruction with flag setting and the normal write instruction. Either may be sufficient. In the case of a normal write command, the flag 180 is not set. In the case of a memory write instruction with a flag setting, since it is executed according to the flowchart shown in FIG. 2, in addition to the operation at the time of a normal write instruction, the flag 180 may be set to “different”.

  FIG. 8 shows a flowchart in which the instruction code shown in FIG. 7 is executed. First, the flag 180 is reset to “0” (same) (S150). Then, the process A indicated by the second and third lines in FIG. 7 is executed (S152). The execution of the process A includes an operation of the flag 180.

  Prior to the execution of the process B, a process of reading the previous result of the process B stored in the save area 112, that is, “MEM5”, to the register a is performed (S154).

  Then, a branch instruction with a flag reference is executed before execution of the process B. If the flag 180 is “0” (same) (S160: Yes), the process B is skipped. On the other hand, if the flag 180 is “1” (different) (S160: No), the process B is executed and the result is written in the save area 112 (“MEM5”).

  FIG. 9 and FIG. 10 show state transitions of related components as the instruction code shown in FIG. 7 is executed. FIGS. 9 and 10 correspond to the case where the flag 180 remains “0” immediately before execution of the process B and the case where the flag 180 is set to “1” before the process B, respectively. In the figure, the first column indicates an instruction, and the second column indicates the number of steps (cycle number) required to execute the leftmost instruction in the same row. From the third column, it is the state of each of the above-described components immediately before the leftmost instruction in the same row is executed.

  As shown in FIG. 9, immediately before the execution of the first instruction (flag reset instruction) shown at the left end of the first line, the status of the flag 180 is undefined and stored in the registers a, b, and c. The data is also undefined. The data at the address “MEM1” in the main memory 110 and the address “MEM1” in the cache memory 120 is “12”. The data at the address “MEM2” in the main memory 110 and the address “MEM2” in the cache memory 120 is “3”. The data at the address “MEM5” in the main memory 110 and the address “MEM5” in the cache memory 120 is “4”.

  This instruction completes execution in one cycle. As a result, the status of the flag 180 becomes “0” (identical) as shown in the second line. The state of each other component does not change.

  In this state, the instruction at the left end of the second line (memory read instruction with flag setting) is executed. As a result, the value of the register b becomes “12” as shown in the third line. The states of other components including the flag 180 are not changed. Note that execution of this instruction is completed in one cycle.

  In this state, the instruction at the left end of the third line (memory read instruction with flag setting) is executed. As a result, the value of the register c becomes “3” as shown in the fourth line. The states of other components including the flag 180 are not changed. Note that execution of this instruction is completed in one cycle.

  In this state, the instruction at the left end of the fourth line (memory read instruction) is executed. As a result, the value of the register a becomes “4” as shown in the fifth line. The states of the other components including the flag 180 are not changed. This instruction is also completed in one cycle.

In this state, the instruction at the left end of the fifth line (branch instruction with flag setting) is executed. Since the status of the flag 180 is “0”, the branch to the branch destination is made. There is no change in the state of the component by executing this command. Therefore, although the execution of the process B is skipped, “4”, which should be the current execution result of the process B, is stored in the register a and the save area 112 (“MEM5”).
Note that execution of this instruction is completed in one cycle.
Thereby, the execution of the instruction code shown in FIG. 7 is completed in a total of five cycles.

Next, a case where the flag 180 is set to “different” before the process B will be described.
As shown in FIG. 10, immediately before the execution of the first instruction (flag reset instruction) shown at the left end of the first line, the status of the flag 180 is undefined and stored in the registers a, b, and c. The data is also undefined. The data at the address “MEM1” in the main memory 110 and the address “MEM1” in the cache memory 120 is “12”. The data at the address “MEM5” in the main memory 110 and the address “MEM5” in the cache memory 120 is “4”.

  However, the data of the address “MEM2” is different from the case of FIG. The data of the address “MEM2” in the main memory 110 is “6”, whereas the data of the address “MEM2” in the cache memory 120 is “3”.

  The flag reset instruction is completed in one cycle. As a result, the status of the flag 180 is set to “0” as shown in the second line. The state of each other component does not change.

  In this state, the instruction at the left end of the second line (memory read instruction with flag setting) is executed. As a result, the value of the register b becomes “12” as shown in the third line. The states of other components including the flag 180 are not changed. Note that execution of this instruction is completed in one cycle.

  In this state, the instruction at the left end of the third line (memory read instruction with flag setting) is executed. Since a cache miss has occurred, the execution of the instruction causes the data “6” at the address “MEM2” to be read from the main memory 110 to the register c and the address “MEM2” of the cache memory 120 as shown in the fourth line. Is updated to “6”, and the status of the flag 180 is set to “1” (different). The state of each other component does not change.

  In this state, the instruction at the left end of the fourth line (memory read instruction) is executed. As a result, the value of the register a becomes “4” as shown in the fifth line. The states of other components including the flag 180 are not changed.

  In this state, the instruction at the left end of the fifth line (branch instruction with flag setting) is executed. Since the status of the flag 180 is “1” (different), the branch to the branch destination is not performed, and the transition to the instruction on the next line (the instruction of the process B) is performed. The state of each component is not changed.

  Then, the process B instruction shown at the left end of the sixth line is executed. As a result, the value of the register a becomes “2” as shown in the seventh line. The state of other components does not change. The execution of this instruction requires 32 cycles.

In this state, the memory write instruction on the seventh line is executed. As a result, the data of the address “MEM5” in the main memory 110 and the cache memory 120 is updated to “2” as shown in the eighth line. If this memory write command is a memory write command with flag setting, the flag 180 is set to “different” again.
Thereby, the process indicated by the instruction code shown in FIG. 6 is completed in a total of 38 cycles.

Here, the processing example shown in FIG. 6 will be compared with a case where it is realized by another method.
First, the processing B is compared with the case where the processing B is not skipped according to the comparison result of the previous input value and the current input value. It is assumed that the microprocessor does not include components corresponding to the cache memory 120 and the flag 180. Further, the result of process B is not saved in the save area 112.

  FIG. 11 is an instruction code in this case, and FIG. 12 is a diagram showing state transition of each component accompanying execution of the instruction code shown in FIG.

  As can be seen from FIGS. 11 and 12, since the process B is not skipped in accordance with the comparison result between the previous value and the current input value of the process B, the previous value of the process B and the current input value (that is, the previous value of the process A) Regardless of the relationship between the current processing result and the current processing result, the number of cycles required to realize the processing shown in FIG. 6 is the same “34” every time.

  In the microprocessor 100 according to the embodiment of the present invention, 5 cycles are required when the input value of the process B and the current input value are the same, and 38 cycles are required when they are different. For example, when the ratio between the previous and current input values for process B is the same as the current input value is “5: 5”, the microprocessor 100 saves about 37% of the processing time from the above method. be able to. Of course, the processing time can be saved as the number of executions of the process B is increased and the cycle number of the process B is increased.

  Next, the process B is skipped according to the comparison result of the previous input value and the current input value of the process B, but the comparison is made with the method using no cache memory. The microprocessor in this case has a flag for comparing the previous input value of process B with the current input value, but in order to distinguish it from the flag 180 in the microprocessor 100, it is hereinafter referred to as “equivalent flag”.

  In this case, the instruction code shown in FIG. 13 can be considered to realize the processing shown in FIG. Note that “MEM3” and “MEM4” are save areas for the previous two input values of process B in the main memory.

  The first line in FIG. 13 is an instruction for reading the data of the address “MEM1” to the register b. By executing this instruction, the current first input value of the process B is stored in the register b.

  The second line is an instruction for reading the data of the address “MEM2” to the register c. By executing this instruction, the current second input value of the process B is stored in the register c.

  Here, although the process A is completed, the subsequent third line is an instruction for reading the data of “MEM3” into the register d because of whether or not the process B is skipped. By executing this instruction, the previous first input value of the process B is stored in the register d.

  The fourth line is an instruction for comparing the registers b and d. By executing this command, the result of whether or not the previous first input value of process B and the current first input value are the same is obtained. This result is set in the equivalence flag.

  The fifth line is an instruction for referring to the value of the equivalence flag and executing the next instruction or branching to the branch destination (line 10) indicated by LAVE1. Specifically, when the equivalence flag indicates “same”, the instruction on the next line is executed, and when the equivalence flag indicates “different”, the sixth to ninth lines are skipped and 10 is skipped. Branch to LAVE1 on the line.

  The sixth line is an instruction for reading the data of the address “MEM4” to the register d. By executing this instruction, the previous second input value of the process B is stored in the register d.

  The seventh line is an instruction for reading the data of the address “MEM5” to the register a. By executing this instruction, the previous processing result of the processing B is stored in the register a.

  The eighth line is an instruction for comparing the registers c and d. By executing this command, the result of whether or not the previous second input value of process B and the current second input value are the same is obtained. This result is set in the equivalence flag.

  The ninth line is an instruction for referring to the value of the equivalence flag and executing the next instruction or branching to the branch destination (line 15) indicated by LAVE2. Specifically, when the equivalence flag indicates “different”, the instruction on the next line is executed, and when the equivalence flag indicates “same”, the 11th to 14th lines are skipped to 15 Branch to LAVE2 on the line.

  The eleventh line is an instruction to write the first input value of the register b, that is, the current process B to the address “MEM3” of the main memory. The 12th line is an instruction for writing the register c, that is, the current second input value of the process B to the address “MEM4” of the main memory. The 13th line is an instruction for executing the process B. The 14th line is an instruction to write the current processing result of the register a, that is, the processing B to the address “MEM5” of the main memory. With these processes, the current two input values and the process result of process B are stored in addresses “MEM3”, “MEM4”, and “MEM5”, respectively.

  FIG. 14 and FIG. 15 show state transitions of related constituent elements as the instruction code shown in FIG. 13 is executed. FIG. 14 corresponds to the case where the current two input values of process B are the same as the previous two input values, respectively, and FIG. 15 is the same as the previous and current input values of process B. However, the second input value corresponds to a case where the previous input value is different from the current input value.

  As can be seen from FIG. 14, when the current two input values of process B are the same as the previous two input values, the process indicated by the instruction code of FIG. 13 is completed in a total of nine cycles. Further, as can be seen from FIG. 15, the first input value of process B is the same between the previous time and this time, but the second input value is different between the previous time and this time, the case of FIG. The process indicated by the instruction code is completed in a total of 44 cycles.

  That is, although this technique can increase the processing speed by about 22% compared to the technique that does not skip the process B according to the comparison result between the previous and current input values of the process B, the embodiment of the present invention. Therefore, the effect as much as that of the microprocessor 100 cannot be obtained.

  In this technique, the greater the number of input values for process B, the greater the number of comparisons and the greater the number of cycles required. Furthermore, since it is necessary to store all the previous input values of the process B, the larger the number of input values, the larger the memory consumption. Therefore, the larger the number of input values of the process B, the more remarkable the effect of reducing the memory consumption and increasing the speed by the technique of the present invention.

<Second Embodiment>
In the first embodiment shown in FIG. 1, whether or not the previous input of process B is the same as the first input value of this time, and whether the previous input of process B and the second input value of this time are the same. Whether or not, only one flag 180 is used, and when one of them is not “same”, the flag 180 is set to “different”. A separate flag may be used for each input value.

  Specifically, instead of the flag 180, a flag 180b corresponding to the register b and a flag 180c corresponding to the register c are provided. Prior to execution of process A, the flags 180b and 180c are reset. When the process A is executed, the previous input of the process B and the first input value of this time are not the same (that is, when the first input of the register b is read from the main memory 110 to the register b). The status of the flag 180b is set to “different” when a cache miss occurs and when the read data and the cache data are different. Similarly, the status of the flag 180c is set to “different” when the previous input value and the second input value of process B are not the same.

Then, when either one of the flags 180b and 180c is “different”, the processing B is executed and the processing result is stored in the save area, while when both the flags 180b and 180c are “same”, the processing is performed. Skip B.
The microprocessor having such a configuration can also obtain the above-described effects of the present invention.

  The present invention has been described above based on the embodiment. The embodiment is an exemplification, and various modifications, increases / decreases, and combinations may be made to the above-described embodiments without departing from the gist of the present invention. It will be understood by those skilled in the art that modifications in which these changes, increases / decreases, and combinations are also within the scope of the present invention.

100 Microprocessor 110 Main memory 112 Save area 120 Cache memory 130 Memory I / O
140 CPU
150 register group 180 flag 190 bus a register b register c register

Claims (2)

Main memory,
Cache memory,
A microprocessor comprising a flag having a first and a second status,
A memory read instruction with a flag setting which is a memory read instruction accompanied by the setting of the flag, and a register with a flag setting which is a register setting instruction which obtains data other than the memory read and sets the data in a register together with the setting of the flag. Corresponding to a setting instruction, a write instruction with flag setting that is a memory write instruction with the setting of the flag, a flag reset instruction, and a flag reference branch instruction,
Setting the flag to the first status according to the flag reset instruction;
When reading is performed in accordance with the memory read instruction with the flag set and a cache miss occurs at the time of reading, and when the read address is a non-cache area address and the read data is different from the cache data corresponding to the read address , Set the flag to the second status,
Write according to the memory write instruction with flag setting, and when the cache miss occurs at the time of writing and when the cache data corresponding to the write address and the write data are different, the flag is set to the second status,
According to the register setting instruction with flag setting, the data obtained this time is compared with the register value set by the previous execution of the instruction, and the flag is set to the second status only when they do not match. At the same time, the value of the register is updated with the data obtained this time,
According to the branch instruction with flag reference, the flag is referred to. When the flag is in the first status, a branch is made to the designated branch destination. When the flag is in the second status, A microprocessor that executes the following instructions. The main memory is a processing result of a first process including execution of one or a plurality of instructions among the memory read instruction with flag setting, the memory write instruction with flag setting, and the register setting instruction with flag setting Is provided with a save area for storing the processing result of the second processing using as an input value,
Setting the flag to a first status by executing the flag reset instruction prior to the first process;
By executing the branch instruction with flag reference before the second process, the execution of the second process is skipped when the status of the flag is the first status,
2. The microprocessor according to claim 1, wherein the processing result stored in the save area is updated with the current processing result only when the second processing is executed.

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