JP2008216606A - Display device driving method, display device and television receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device driving method capable of taking measures to EMI due to frequency diffusion and suppressing the generation of display defects. <P>SOLUTION: In the display device driving method for inputting a reference clock signal and an input image signal synchronous with the reference clock signal, generating a frequency diffusion clock signal by continuously varying the frequency of the reference clock signal at a prescribed variation period, generating a source signal to be written in each pixel on the basis of the input image signal, successively selecting respective pixels at a prescribed horizontal scanning period synchronous with the frequency diffusion clock signal, and writing a display signal; the variation period of the frequency diffusion clock signal is synchronized with the horizontal scanning period. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device driving method, a display device, and a television receiver, and more particularly to a display device driving method and display device suitable for electromagnetic interference (EMI) countermeasures, and a television including such a display device. It relates to a receiver.

  In recent years, flat display devices such as liquid crystal display devices have been widely used as display units for electrical products such as computers and televisions.

  Such a liquid crystal display device generally includes a display screen in which a large number of picture elements are arranged in a matrix. Images are sequentially displayed on the display screen based on an input clock signal and an image signal synchronized with the clock signal. Is displayed. The picture elements arranged in a matrix on the display screen are connected to a large number of gate lines and a large number of source lines which are also arranged vertically and horizontally in the display screen. A gate voltage is applied to these gate wirings, a picture element for one row connected to each gate wiring is selected, and a source voltage is applied to the selected picture elements via the source wiring.

  In the following description, the period from the selection of a row on the display screen to the selection of another row is referred to as a horizontal scanning period or a horizontal scanning cycle, and a row with a display screen is selected. Next, a period until the same row is selected is called a vertical scanning period or a vertical scanning period. The reciprocal numbers are called the horizontal scanning frequency and the vertical scanning frequency.

FIG. 11 shows an equivalent circuit for one picture element of such a liquid crystal display device. Each picture element 100 includes a liquid crystal capacitor C _CL in which liquid crystal is filled between the picture element electrode 102 and the counter electrode 104, and a thin film transistor (TFT) 106 that is a switching element connected to the liquid crystal capacitor C _CL. I have. The gate electrode 106G of the TFT 106 is connected to the gate wiring 108G, the source electrode 106S is connected to the source wiring 108S, and the drain electrode 106D is connected to the pixel electrode 102. While the gate voltage Vg ₁ applied to the TFT 106 is high (hereinafter referred to as a writing period), the TFT 106 is turned on and the source voltage Vs ₁ is applied to the pixel electrode 102, so that the pixel electrode The voltage Vp of 102 changes, and the liquid crystal capacitor _CCL is charged. Then, the source voltage to the picture element which is connected to the 'gate voltage Vg ₂ is a gate wiring 108G becomes high the' next gate line 108G after a predetermined horizontal scanning period T _H1 has elapsed is applied. In this way, each picture element on the display screen is sequentially selected for each row (a group of picture elements connected to one gate wiring) and the source voltage Vs is applied. In this way, the liquid crystal is aligned by the electric field generated by the potential difference between the voltage Vp of the picture element electrode 102 and the voltage Vcom of the counter electrode 104, and the transmittance of each picture element is adjusted to display an image on the display screen. .

  Conventionally, in such a display device, operation control of each unit has been performed using a clock signal generated by a clock such as a crystal oscillator with high oscillation accuracy. However, the circuit scale becomes larger due to the high definition of the display device, and accordingly, the level of radiated electromagnetic waves generated during the operation of the display device tends to increase. In recent years, regulations requiring suppression of electromagnetic interference (EMI) caused by such radiated electromagnetic waves have become stricter year by year.

  Therefore, as an EMI countermeasure means for adapting radiated electromagnetic waves to the standards of each country, a frequency spreading technique for intentionally changing the frequency of the clock signal is applied. This frequency spreading technique is to disperse the spectrum of radiated electromagnetic waves by periodically and continuously changing the frequency of the clock signal to lower its peak.

  The image display device described in Patent Document 1 applies such a frequency spreading technique to an image display device, and drives a device provided in the image display device based on a frequency-spread clock signal to thereby generate a radiation electromagnetic wave. This is to prevent the EMI by suppressing the peak. In addition, the image forming apparatus described in Patent Document 2 needs to modulate the reference clock signal to spread the frequency and transmit the frequency spread clock signal to suppress EMI noise and to precisely match the timing. In a predetermined device, a frequency spread clock signal is demodulated into a reference clock signal by a demodulation circuit.

JP 2006-154820 A JP 2003-332997 A

However, when the liquid crystal display device is driven in synchronization with the frequency-spread clock signal, the following problem may occur. For example, as shown in FIG. 12, if the frequency f of the clock signal CK is always constant, and each horizontal scanning period T _H1 , T _H2 , T _H3 includes the same number of clocks, each horizontal scanning period T _H1 , T _H2 and T _H3 are the same time. However, in the case of the clock signal SS-CK whose frequency fss varies, even when the number of clocks included in one horizontal scanning period is the same, the times of the horizontal scanning periods T _H1 , T _H2 and T _H3 are different. That is, as the frequency fss of the clock signal varies, the horizontal scanning periods T _H1 , T _H2 , and T _H3 vary, so that the gate voltage applied to the TFT of each pixel becomes high and the TFT is turned on. The writing period Ton varies. As a result, minute variations may occur in the amount of charge charged in the liquid crystal capacitor.

  For example, when the vertical scanning frequency is relatively low such as 60 Hz as in normal television broadcasting, the writing period can be set sufficiently long. Accordingly, the amount of charge charged in the liquid crystal capacitor is large. In such a case, even if the writing period varies somewhat, the difference in the amount of charge due to the difference is unlikely to be a luminance difference that can be visually recognized on the display screen.

  However, for example, when driving with a high vertical scanning frequency 1 / Tv in order to improve the performance of moving image display of the liquid crystal display device, the writing period Ton must be set relatively short. In this way, when the writing period Ton is set short, if there is a minute variation in the writing period Ton, a difference in charge amount due to the variation tends to appear as a luminance difference on the display screen.

  In addition, the variation in the writing period Ton due to the frequency diffusion of the clock signal is generated in synchronization with the variation in the clock frequency fss, so that the luminance unevenness is displayed on the display screen.

  Therefore, even if the luminance difference caused by the frequency diffusion of the clock signal is of a level that is hardly visible when the luminance unevenness is displayed stationary, the luminance unevenness moves without being stationary. In such a case, it becomes easy to be visually recognized, which contributes to a reduction in display quality.

  Therefore, the problem to be solved by the present invention is to provide a display device driving method capable of taking EMI countermeasures by frequency spreading and suppressing the occurrence of display defects. Moreover, it is providing the television receiver provided with such a display device and such a display device.

  In order to solve the above-described problem, the present invention inputs a reference clock signal and an input image signal to a display device having a display screen in which a large number of picture elements are arranged in a matrix, and sets the frequency of the reference clock signal. A frequency spread clock signal is generated by continuously fluctuating at a predetermined fluctuation period, and a display signal written to each pixel is generated based on the input image signal, and a predetermined signal synchronized with the frequency spread clock signal is generated. A display device driving method for sequentially selecting the picture elements for each row in a horizontal scanning period and writing the display signal, wherein the fluctuation period of the frequency spread clock signal is synchronized with the horizontal scanning period. It is a summary.

  The display device of the present invention is a display device that receives a reference clock signal and an input image signal and displays an image corresponding to the input image signal on a display screen in which a large number of picture elements are arranged in a matrix. A frequency spread clock signal generator for continuously changing the frequency of the reference clock signal in a predetermined cycle to generate a frequency spread clock signal, and writing to each picture element of the display screen based on the input image signal A display signal generation unit that generates a display signal, and a scanning signal generation unit that generates a scanning signal that sequentially selects the pixels for each row in a predetermined horizontal scanning period synchronized with the frequency spread clock signal, The gist is to synchronize the fluctuation period in which the frequency of the frequency spread clock signal fluctuates with the horizontal scanning period in which the picture elements are sequentially selected for each row. .

  Such a display device can be applied to a television receiver.

  According to the present invention, when a large number of picture elements arranged in a matrix on a display screen are sequentially selected for each row by a gate signal at a predetermined horizontal scanning period and a display signal is written to display an image, a reference clock is displayed. The display signal is written in each picture element in synchronization with the frequency spread clock signal in which the signal frequency is continuously fluctuated at a predetermined fluctuation period, thereby dispersing the spectrum of the radiated electromagnetic wave and lowering its peak to take measures against EMI. Can be planned. Furthermore, since the fluctuation cycle of the frequency spread clock signal and the horizontal scanning cycle are synchronized, it is possible to suppress the luminance unevenness of the picture element due to the variation in the writing time. In addition, it is possible to prevent a problem that occurs such that luminance unevenness moves on the display screen. In this way, it is possible to take measures against EMI by frequency spreading, and to suppress the occurrence of display defects.

Hereinafter, a driving method of the display device according to the first embodiment of the present invention will be described in detail with reference to the drawings. In this embodiment, an example in which the display device driving method according to the present invention is applied to an active matrix liquid crystal display device 1 including a thin film transistor (TFT) as a switching element is shown. Therefore, in the following description, a display signal written to each picture element of the display screen based on an input image signal is called a source signal, and a scanning signal for sequentially selecting each picture element for each row is called a gate signal. Further, in the following description, from the selection of a pixel in a row (a row of pixels connected to one scanning wiring (gate wiring)) on the display screen to the selection of another row period called the horizontal scanning period T _H or horizontal scanning period T _H, the period until the next also the same line a row of the display screen is selected is selected as the vertical scanning period T _v or vertical scanning period T _v . And each of the reciprocal of the horizontal scanning frequency 1 / _{T H} and a vertical scanning frequency of 1 / _{T V.}

  FIG. 1 is a block diagram showing a configuration of a liquid crystal display device driven by a display device driving method according to an embodiment of the present invention.

  As shown in FIG. 1, the liquid crystal display device 1 includes a liquid crystal display panel 10 in which a large number of picture elements P are arranged in a matrix on a display screen, a gate drive circuit 12G connected to the liquid crystal display panel 10, and source drive. The circuit 12S includes a control circuit 14 that controls the gate driving circuit 12G and the source driving circuit 12S based on a reference clock signal CK and an input image signal Data that are input from the outside. The picture elements P arranged in a matrix on the display screen of the liquid crystal display panel 10 are transferred to the gate driving circuit 12G and the source driving circuit 12S via the gate wiring 16G and the source wiring 16S which are also provided in the vertical and horizontal directions on the display screen. It is connected. Furthermore, a light source driving circuit 20 that drives a light source 18 disposed on the back surface of the liquid crystal display panel 10 is connected to the control circuit 14.

  The control circuit 14 receives a reference clock signal CK and an input image signal Data from the outside. The control circuit 14 continuously varies the frequency of the input reference clock signal CK with a predetermined fluctuation period to generate the frequency spread clock signal SS-CK (see FIG. 2), and this frequency spread clock signal SS-CK. To control the timing to generate the gate signal G-Dr and the source signal S-Dr based on the input image signal Data. The gate signal G-Dr is input to the gate drive circuit 12G, and the source signal S-Dr is input to the source drive circuit 12S. The gate driving circuit 12G and the source driving circuit 12S apply the gate voltage Vg and the source voltage Vs to the gate wiring 16G and the source wiring 16S at timings specified by the gate signal G-Dr and the source signal S-Dr, respectively. Drive P.

  FIG. 2 is a diagram showing the timing of the change in the frequency fss of the frequency spread clock signal SS-CK and the change in the gate voltage Vg applied to each gate line 16G of the liquid crystal display panel 10. The frequency spread clock signal SS-CK exemplified here is such that the frequency of an average 80 MHz pulse signal fluctuates by ± 2% at a fluctuation frequency 1 / Tss of 90 kHz. That is, the frequency fss of the frequency spread clock signal SS-CK repeats rising and falling continuously between 81.6 MHz and 78.4 MHz with a fluctuation frequency 1 / Tss of 90 kHz. Therefore, the frequency spread clock signal SS-CK has a frequency fss that changes every clock.

As shown in FIG. 2, and the fluctuation period Tss of the frequency of the spread spectrum clock signal SS-CK, the horizontal scanning period _{T H} is synchronous, the horizontal scanning period _{T H} and the gate voltage pulse width of Vg (write time Ton) Is set based on the number of clocks of the frequency spread clock signal SS-CK. First pulse gate voltages Vg ₁ applied to the gate wiring 16G disposed at the top of the display screen, spread spectrum clock signal SS-CK rises at 80 MHz. When spread spectrum clock signal SS-CK returns to again 80MHz lowered to 78.4MHz after rising from 80MHz to 81.6MHz, pulses of the gate voltage Vg ₂ applied to the second gate wiring 16G rises. As described above, the pulses of the gate voltage Vg sequentially applied up to the nth gate line 16G arranged at the bottom of the display screen have the same timing in synchronization with the fluctuation cycle Tss of the frequency spread clock signal SS-CK. (That is, in the case shown in FIG. 2, the frequency spread clock SS-CK starts to rise from 80 MHz at the same time). Then, the frequency fss of the frequency spread clock signal SS-CK included in the period from when the pulse of the gate voltage Vg applied to each gate line 16G rises to when the pulse falls (write period Ton) is always the same. The pulse width of the gate voltage (write period Ton) is always the same.

FIG. 3 is a diagram showing an equivalent circuit for one picture element of the liquid crystal display device 10 shown in FIG. FIG. 4 is a diagram showing an outline of changes in each voltage when the picture element P is driven. As shown in FIG. 3, each picture element P includes a liquid crystal capacitor C _CL in which liquid crystal is filled between the picture element electrode 22 and the counter electrode 24, and an auxiliary capacitor connected in parallel to the liquid crystal capacitor C _CL. Cs and a thin film transistor 26 (hereinafter referred to as TFT) which is a switching element connected to the liquid crystal capacitor _CCL and the auxiliary capacitor Cs. The gate electrode 26G of the TFT 26 is connected to the gate wiring 16G, the source electrode 26S is connected to the source wiring 16S, and the drain electrode 26D is connected to the pixel electrode 22. Further, parasitic capacitances Csd and Cgd are generated between the source electrode 26S and the drain electrode 26D and between the drain electrode 26D and the gate electrode 26G.

As shown in FIG. 4, while the gate voltage Vg applied to the gate electrode 26G of the TFT 26 through the gate wiring 16 is high (writing period Ton), the picture elements connected to the gate wiring 16G are connected. (A picture element for one line) is selected. During the writing period Ton, the TFT 26 is turned on, and the source voltage Vs applied to the source electrode 26S via the source line 16S is applied to the pixel electrode 22 to charge the liquid crystal capacitor _CCL .

When the gate voltage Vg falls, the liquid crystal capacitor _CCL is charged, and the voltage Vp of the pixel electrode 22 rises to near the source voltage Vs. Under the influence of the voltage Vp parasitic capacitances Csd and Cgd of the pixel electrode 22, the level shifts by ΔV, and the voltage Vp is held until the TFT 26 is turned on next time. Thus, when the liquid crystal capacitor C _CL is charged, an electric field is generated due to a potential difference between the pixel electrode 22 and the voltage Vcom of the counter electrode 24. Then, the liquid crystal is aligned between the picture element electrode 22 and the counter electrode 24, and the light transmittance of each picture element P is controlled. When the light source 18 disposed on the back surface of the liquid crystal display panel 10 is driven to irradiate the liquid crystal display panel 10 from the back surface, the illumination light passes through each picture element P and displays an image on the display screen.

  Here, for example, when a normal television broadcast is displayed with the vertical scanning frequency of 60 Hz as it is, when the vertical scanning frequency is relatively low and the writing period can be secured sufficiently long, the pixel electrode voltage is equal to the source voltage. Rise to the same level. However, for example, if the vertical scanning frequency is set high, it may be difficult to ensure a sufficiently long writing period Ton.

FIG. 4 shows an example in which the vertical scanning frequency 1 / Tv is relatively high (for example, 120 Hz) and the writing period Ton is short (for example, 10 μsec). In such a case, the voltage Vp of the pixel electrode 22 does not reach the same level as the source voltage Vs (for example, about 80% of the source voltage Vs). Thus, when the voltage Vp of the picture element electrode 22 is low, the luminance of each picture element P becomes dark. However, according to the driving method of the liquid crystal display device 1 according to the present embodiment, since the fluctuation frequency Tss of spread spectrum clock signal SS-CK and the horizontal scanning frequency T _H is synchronized, the pulse width of the gate voltage Vg i.e. The writing period Ton is always constant. Accordingly, even if such a decrease in brightness cannot be avoided, the decrease in brightness occurs in the same manner in all the picture elements P in the display screen, so the light amount of the light source 18 is increased. The decrease in luminance on the display screen can be covered. Further, in each picture element P in the display screen, there is no periodic variation in the writing time Ton, and this uneven brightness does not move on the display screen. Therefore, a fine screen display without display defects can be realized.

  Further, since the liquid crystal display device 1 is controlled based on the frequency spread clock signal SS-CK generated by frequency spreading the input reference clock signal CK, the control circuit 14, the gate drive circuit 12G, and the source drive circuit 12S. The spectrum of the radiated electromagnetic waves generated from the liquid crystal display panel 10 and the transmission line connecting them can be dispersed to reduce the peak.

Next, a first modification of the liquid crystal display device driving method according to the first embodiment of the present invention described above will be described with reference to FIG. As shown in FIG. 5, two cycles of the variation cycle Tss frequency fss of the spread spectrum clock signal SS-CK is synchronized with one period of the horizontal scanning period _{T H.} That is, the clock speed of the spread spectrum clock signal SS-CK included in one horizontal scanning period T _H has doubled the number of clocks included in one variation period Tss. Therefore, the pulse of the gate voltage Vg ₁ applied to the first gate line 16G arranged at the top of the display screen rises when the frequency of the frequency spread clock signal SS-CK is 80 MHz, and the frequency spread clock When the frequency of the signal SS-CK returns to again vary two cycles 80 MHz, the next gate line 16G, that is, the pulse of the gate voltage Vg ₂ applied to the second gate wiring 16G rises. Thus, the pulse of the gate voltage Vg sequentially applied to each gate wiring 16G is applied at the same timing in synchronization with the fluctuation period Tss of the frequency spread clock signal SS-CK. Then, the pulse width (write time Ton) of the gate voltage Vg applied to each gate line 16G is always the same.

Thus, in all of the picture element P on the display screen, the write period Ton in which the liquid crystal capacitor C _CL source voltage Vs to the liquid crystal capacitor C _CL is applied is charged is the same, to suppress the occurrence of luminance unevenness Can do. Further, a variation period Tss frequency fss of the spread spectrum clock signal SS-CK, since the horizontal scanning period T _H are synchronized, there is no such thing as luminance unevenness move on the display screen. Further, since the liquid crystal display device 1 is controlled based on the frequency spread clock signal SS-CK, the spectrum of the radiated electromagnetic wave from the liquid crystal display device 1 is dispersed to reduce the peak thereof, and EMI countermeasures can be taken. .

Next, a second modification of the method for driving the liquid crystal display device according to the first embodiment of the present invention will be described with reference to FIG. As shown in FIG. 6, when the frequency spread clock signal SS-CK starts to rise from 80 MHz, a pulse of the gate voltage Vg applied to the first gate line 16G arranged at the top of the display screen rises. . The frequency SS-CK of the frequency spread clock signal rises from 80 MHz to 81.6 MHz and then falls to 78.4 MHz. Then, the pulse of the gate voltage Vg applied to the second gate wiring 16G rises at the same time as the fluctuation of the frequency of the frequency spread clock signal SS-CK is reset and starts to rise again from 80 MHz. 1 are determined in the number of clocks of the frequency spread clock signal SS-CK contained in the horizontal scanning period T _H is in advance, when the number of clocks reaches that value, the variation of the frequency of the spread spectrum clock signal SS-CK is reset . Since the pulse of the gate voltage Vg rises at the same time as it starts to fluctuate in the same manner, the pulse width (write period Ton) of the gate voltage Vg applied to each gate line 16G is always the same.

Then, all the pixels P on the display screen, writing period Ton in which the liquid crystal capacitor C _CL source voltage Vs to the liquid crystal capacitor C _CL is applied is charged is the same, is possible to suppress the occurrence of luminance unevenness it can. Further, a variation period Tss frequency fss of the spread spectrum clock signal SS-CK, since the horizontal scanning period T _H are synchronized, there is no such thing as luminance unevenness move on the display screen. Furthermore, since the liquid crystal display device 1 is controlled based on the frequency spread clock signal SS-CK, the spectrum of the radiated electromagnetic waves from the liquid crystal display device 1 can be dispersed to reduce the peak.

  Next, a display device according to a second embodiment of the present invention will be described in detail with reference to the drawings. Here, an example of a liquid crystal display device 1 including a liquid crystal display panel is shown as the display device. The liquid crystal display device 1 is driven by applying the method for driving the display device shown in the first embodiment. Accordingly, the same components as those described in the first embodiment are denoted by the same reference numerals and detailed description thereof is omitted.

  As shown in FIG. 1, the liquid crystal display device 1 includes a liquid crystal display panel 10, a gate drive circuit 12G and a source drive circuit 12S connected to the liquid crystal display panel 10, and the gate drive circuit 12G and the source drive circuit. The control circuit 14 controls the 12S based on a reference clock signal CK and an input image signal Data input from the outside. Furthermore, a light source driving circuit 20 that drives a light source 18 disposed on the back surface of the liquid crystal display panel 10 is connected to the control circuit 14.

  FIG. 7 is a block diagram showing the configuration of the control circuit 14. The control circuit 14 includes a frequency spread circuit 30 that is a frequency spread clock signal generator that generates a frequency spread clock signal SS-CK by continuously changing the frequency of the reference clock signal CK input from the outside in a predetermined cycle. A source signal generation unit that generates a source signal S-Dr based on an input image signal Data input from the outside, and a gate signal generation unit that generates a gate signal D-Dr synchronized with the frequency spread clock signal The display control circuit 32 having the above.

  The reference clock signal CK input to the control circuit 14 is first input to the display control circuit 32 and sent to the frequency spreading circuit 30. Since the frequency spread circuit 30 that is conventionally used can be applied, a detailed description is omitted and an example is briefly described. The frequency spread circuit 30 includes an up / down counter, a DA converter, a low-pass filter, and a voltage controlled variable oscillator connected in series. In the frequency spreading circuit 30, first, the reference clock signal CK input from the display control circuit 32 is input to the up / down counter. For example, if the up / down counter is set to 100 clocks in one fluctuation period (usually set to 2 to the power of n, 100 will be described here as an example for the sake of simplicity), from 0 clocks to 24 clocks. Up-counting is performed, down-counting is performed from 25 clocks to 74 clocks, and up-counting is performed from 75 clocks to 100 clocks. In this way, the up / down counter generates a triangular wave of a digital signal. The output of the up / down counter is input to a DA converter and converted to an analog output, and a high-frequency component is removed by a low-pass filter to obtain an analog voltage triangular wave. By inputting this analog voltage to the voltage controlled variable oscillator, a frequency spread clock signal SS-CK having an oscillation frequency as shown in FIG. 2 is obtained.

  The frequency spread clock signal SS-CK generated in this way is input to the display control circuit 32. The display control circuit 32 includes a source signal generation unit that generates a source signal S-Dr based on an input image signal SS-CK that is input, and a gate signal generation unit that generates a gate signal G-Dr. The source signal S-Dr and the gate signal G-Dr are output to the source driving circuit 12S and the gate driving circuit 12G at a timing based on the clock signal SS-CK.

  Since the display control circuit 32 can be applied to an electronic circuit for display control that has been generally used in the past, a detailed description of its configuration is omitted, and an example is briefly described. The display control circuit 32 includes a timing controller 34 that is a source signal generation unit and a gate signal generation unit, a voltage driving circuit 36, and the like. The input image signal Data includes a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data signal RGB, and the like. The timing controller 34 applies the gate signal G-Dr and the source signal S-Dr to the gate drive circuit 12G and the source drive circuit 12S based on the input frequency spread clock signal SS-CK, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync. In addition to the output, the voltage drive circuit 36 is controlled to supply a drive voltage to the gate drive circuit 12G and the source drive circuit 12S.

  These frequency spreading circuit 30 and display control circuit 32 are connected to a synchronizing circuit 38 and operate in synchronization with each other.

The gate drive circuit 12G is applied based on a predetermined horizontal scanning period T _H for controlling the timing controller 34 outputs drive voltage from the voltage driving circuit 36 of the display control circuit 32 to the gate line 16G of the liquid crystal display panel 10 The TFT 26 of the picture element P connected to the gate wiring 16G is turned on.

  The source drive circuit 12S applies the drive voltage output from the voltage drive circuit 36 of the display control circuit 32 to the source line 16S as the source voltage Vs corresponding to the display content in synchronization with the scanning of the gate line 16G by the gate drive circuit 12G. To do. The timing of application of the source voltage Vs to the source line 16S by the source drive circuit 12S is controlled by the timing controller 34 as in the gate drive circuit 12G.

According to the liquid crystal display device 1 having such a configuration, the liquid crystal display panel 10 can be driven by the display device driving method described in the first embodiment. Thus, in all the pixels P on the display screen, writing period Ton in which the liquid crystal capacitor C _CL source voltage Vs to the liquid crystal capacitor C _CL is applied is charged is the same, it is possible to suppress the occurrence of luminance unevenness it can. Further, a variation period Tss of the frequency of the spread spectrum clock signal SS-CK, since the horizontal scanning period T _H are synchronized, there is no such thing as luminance unevenness move on the display screen. Furthermore, since the liquid crystal display device 1 is controlled based on the frequency spread clock signal SS-CK, the spectrum of the radiated electromagnetic waves from the liquid crystal display device 1 is dispersed to reduce the peak thereof, thereby reducing EMI. it can.

  The control circuit 14 is mounted on a control circuit board 59 described later. At this time, the display control circuit 32 having the gate signal generation unit and the source signal generation unit is built in one application specific integrated circuit (ASIC), and the frequency spread circuit 30 is built in another integrated circuit. Alternatively, the display control circuit 32 and the frequency spread circuit 30 can be incorporated in one ASIC.

Further, a variation period Tss of spread spectrum clock signal SS-CK to the control circuit 14, further comprising a synchronization deviation detection unit for detecting a deviation of a horizontal scanning period T _H, if the fluctuation period Tss a horizontal scanning period T _H If synchronization is fallen into disorder, better when to synchronize the fluctuation period Tss a horizontal scanning period T _H based on the deviation detected by the synchronization deviation detection unit.

For example, when the deviation detected by the synchronization deviation detection unit exceeds a predetermined threshold, the frequency variation of the frequency spread clock signal SS-CK of the frequency spread circuit 30 may be reset. Or corrects the frequency spread clock signal SS-CK and / or the gate signal S-Dr, a variation period Tss, may be looking for frequency synchronization by finely adjusting the horizontal scanning period T _H.

  Next, a modification of the second embodiment of the present invention will be described. Since the liquid crystal display device 1a is a modification of the control circuit 14 of the liquid crystal display device shown in the second embodiment, only the control circuit 14a will be described here.

  FIG. 8 is a block diagram showing the configuration of the control circuit 14a. The control circuit 14a is a frequency spread circuit that is a frequency spread clock signal generator that generates a frequency spread clock signal SS-CK by continuously changing the frequency of the reference clock signal CK input from the outside with a predetermined change period Tss. 30, a synchronizing circuit 38 for synchronizing an input image signal Data input from the outside with the frequency spread clock signal SS-CK, a display signal SS-Data and a frequency spread clock synchronized with the frequency spread clock signal SS-CK. A display control circuit 32a that generates a source signal S-Dr and a gate signal D-Dr based on the signal SS-CK is provided.

  The frequency spreading circuit 30 generates the frequency spreading clock signal SS-CK by changing the frequency of the input reference clock signal CK with a predetermined changing period Tss. This frequency spread clock signal SS-CK is input to the synchronization circuit 40. The synchronization circuit 40 outputs the input image signal Data in synchronization with the frequency of the frequency spread clock signal SS-CK. The display control circuit 32a includes a timing controller 34a and a voltage driving circuit 36a. The timing controller 34a supplies the gate signal G-Dr and the source signal S-Dr to the gate drive circuit 12G and the source drive circuit 12S based on the input frequency spread clock signal SS-CK, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync. At the same time, the voltage drive circuit 36a is controlled to supply a drive voltage to the gate drive circuit 12G and the source drive circuit 12S.

  The frequency spreading circuit 30 and the display control circuit 32a are connected to a synchronizing circuit 38 and operate in synchronization with each other.

  According to the liquid crystal display device having such a configuration, the liquid crystal display panel can be driven by the driving method of the display device shown in the first embodiment. Therefore, the same effect as the above embodiment can be obtained.

  The control circuit 14 is mounted on a control circuit board 59 which will be described later. However, the gate signal generation unit and the source signal generation unit may be built in one application specific integrated circuit (ASIC). Alternatively, the display control circuit 32 and the frequency spread circuit 30 can be incorporated in one ASIC.

Further, the fluctuation period Tss of spread spectrum clock signal SS-CK to the control circuit 14, further comprising a synchronization deviation detection unit for detecting a deviation of a horizontal scanning period T _H, if the fluctuation period Tss a horizontal scanning period T _H If synchronization is fallen into disorder, it is preferable to be synchronized and variation period Tss a horizontal scanning period T _H based on the deviation detected by the synchronization deviation detection unit.

  Next, the overall structure of the liquid crystal display device 1 or 1a will be described. FIG. 9 is an exploded perspective view schematically showing the configuration of the main part of the liquid crystal display device 1 or 1a. For convenience of explanation, the upper part of FIG. 9 is referred to as the “front side” of the display device, and the lower part is referred to as the “rear side”.

  As shown in FIG. 9, the liquid crystal display device 1 or 1a includes a chassis 51, a reflection sheet 52, a light source 18, a side holder 54, optical sheets 55, a frame 56, a liquid crystal display panel 10, and a bezel 58. A light source drive circuit board 60, a light source drive circuit board cover 60a, a control circuit board 59, and a control circuit board cover 59a.

  These chassis 51, reflection sheet 52, light source 18, side holder 54, optical sheets 55, frame 56, liquid crystal display panel 10, bezel 58, light source drive circuit board 60, light source drive circuit board cover 60a, control circuit board cover 59a A configuration generally known in the art can be applied. Therefore, it will be briefly described below, and detailed description will be omitted.

  The chassis 51 is a substantially flat plate-like member, and is formed, for example, using a metal plate or the like by press working.

  As the light source 18, various known light sources such as a fluorescent tube such as a cold cathode tube and a hot cathode tube, a discharge tube such as a xenon tube, and a light emitting element such as an LED can be applied. Here, a configuration to which a linear cold cathode tube is applied is shown.

  The reflection sheet 52 is a sheet-like or plate-like member having a surface property that diffusely reflects light emitted from the light source 18. The reflection sheet 52 is made of, for example, foamed PET (polyethylene terephthalate).

  The side holder 54 is a member that functions as a spacer or the like for disposing optical sheets 55 described later. The side holder 54 is a substantially rod-shaped member, and is integrally formed of, for example, a resin material.

  The optical sheets 55 refer to a sheet-like member or a plate-like member that adjusts the characteristics of light emitted from the light source 18, or a set of such members. The optical sheets 55 include, for example, a diffusion plate, a diffusion sheet, a polarization reflection sheet, a lens sheet, and the like. In general, these are stacked and used.

  The frame 56 is a member having a function of holding and / or protecting the optical sheets 55, the liquid crystal display panel 10, and the like. The frame 56 has a substantially quadrangular shape with an opening, for example, a structure formed integrally with a resin material or the like, a structure where a plurality of parts formed of a resin material or the like are combined, a press work using a metal plate material, and the like. The structure formed by using, the structure which combines the parts etc. which are formed using a press work etc. with a metal plate material, etc. are applicable.

  The light source drive circuit board 60 is a circuit board on which the light source drive circuit 20 and the like are constructed. The light source drive circuit board cover 60a is a plate-like member that covers the light source drive circuit board 60, and is formed of, for example, a metal plate material.

  As shown in FIG. 9, the liquid crystal display panel 10 has a circuit board 12ga (including a film-like one) on which the gate driving circuit 12G is mounted on the outer peripheral edge and a circuit board 12sa on which the source driving circuit 12S is mounted. (Including film-like ones) are attached.

  The bezel 58 is a member having a function of protecting and / or holding the liquid crystal display panel 10. The bezel 58 has an open substantially quadrangular shape. For example, a structure that is integrally formed of a resin material, a structure that combines parts formed of a resin material, a structure that is formed using a metal plate material using a press process, or a metal plate material that is formed using a press process. A configuration in which different members are combined can be applied.

  The control circuit board 59 is a circuit board on which the control circuit 14 or 14a or the like is constructed. The control circuit board cover 59a is a member that covers the control circuit board 59, and is formed of, for example, a metal plate.

  The assembly structure of the display device 1 including such a member is as follows.

  First, the reflection sheet 52 is disposed on the front side of the chassis 51. And the light source 18 is arrange | positioned in the front side, and the side holder 54 is arrange | positioned so that the edge part of each light source 18 may be covered. An optical sheet 55 is disposed on the front side, and a frame 56 is mounted on the front side. The liquid crystal panel 15 is disposed on the front side of the frame 56, and the bezel 58 is mounted on the front side.

  A light source driving circuit board 60 and a control circuit board 59 are disposed on the rear side of the chassis 51. The light source drive circuit board 60 and each light source 18 are electrically connected, and the control circuit board 59 and the circuit board mounted on the liquid crystal display panel 10 are electrically connected. Then, the light source drive circuit board cover 16 a is attached so as to cover the light source drive circuit board 60, and the control circuit board cover 59 a is attached so as to cover the control circuit board 59.

  Next, a television receiver according to an embodiment of the present invention will be described. FIG. 10 is an exploded perspective view showing a schematic configuration of the television receiver 2 according to the embodiment of the present invention.

  As shown in FIG. 10, the television receiver 2 includes a display device 1 or 1a according to an embodiment of the present invention, a tuner 71, a loudspeaker 73, a power source 72, cabinets 74a and 74b, and a support member 75. Is provided. Since the tuner 71, the loudspeaker 73, the power source 72, the cabinets 74a and 74b, and the support member 75 can be those commonly used in the related art, they will be described briefly and detailed description thereof will be omitted.

  The tuner 71 generates an image signal and an audio signal of a predetermined channel from the received radio wave. As this tuner 71, a conventional general terrestrial tuner (analog terrestrial tuner, digital terrestrial tuner, or both) BS tuner, CS tuner, or the like can be applied. The loudspeaker 73 emits a sound based on the sound signal generated by the tuner 71. As this loudspeaker 73, a general speaker or the like can be applied. The power source 72 can supply power to the display device 1, the tuner 71, the loudspeaker 73, and the like according to the embodiment of the present invention.

  The display device 1, the tuner 71, the loudspeaker 73, and the power source 72 according to the embodiment of the present invention are housed in the cabinets 74 a and 74 b and supported by the support member 75. FIG. 12 shows a configuration in which the cabinet includes a front side cabinet 74a and a back side cabinet 74b, and the display device 1, the tuner 71, the loudspeaker 73, and the power source 72 are accommodated therebetween. In addition, the tuner 71, the loudspeaker 73, and the power source 72 may be assembled to the display device 1.

According to the television receiver 2 according to the present invention configured as described above, the liquid crystal display device 1 or 1a is driven in synchronization with the frequency spread clock signal SS-CK. Thus, the peak can be lowered to reduce EMI. Further, prevent a problem that suppresses uneven brightness because it is synchronized with the fluctuation period Tss of spread spectrum clock signal SS-CK and the horizontal scanning period T _H, also occurs as luminance unevenness is moved on the display screen can do.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to such embodiment at all, Of course, it can implement in a various aspect in the range which does not deviate from the meaning of this invention. For example, although the liquid crystal display device has been described as an example in the above embodiment, various hold-type display devices such as a display device using inorganic or organic electroluminescence or a light emitting diode, a plasma display, and the like can be applied.

It is a block diagram which shows the structure of the liquid crystal display device driven with the drive method of the display apparatus which concerns on embodiment of this invention. It is a figure which shows the fluctuation period of a frequency spread clock signal, and the timing of a change of a gate voltage. It is a figure which shows the equivalent circuit for 1 picture element of the liquid crystal display device shown in FIG. It is a figure which shows the outline of the change of each voltage at the time of the drive of the pixel shown in FIG. It is a 1st modification of the drive method of the liquid crystal display device which concerns on the 1st Embodiment of this invention. It is a 2nd modification of the drive method of the liquid crystal display device which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the control circuit of the display apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the modification of a control circuit. FIG. 2 is an exploded perspective view schematically showing the configuration of the liquid crystal display device shown in FIG. 1. It is the disassembled perspective view which showed schematic structure of the television receiver concerning embodiment of this invention. It is a figure which shows the equivalent circuit for 1 picture element of the conventional liquid crystal display device. It is a figure which shows the timing of the change of each voltage applied to a clock signal and a pixel.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2 Television receiver 10 Liquid crystal display panel 12S Source drive circuit 12G Gate drive circuit 14 Control circuit 16S Source line 16G Gate line 22 Pixel electrode 24 Counter electrode 30 Frequency diffusion circuit 32 Display control circuit 34 Timing controller 36 Voltage drive circuit 38 synchronizing circuit P picture element CK reference clock signal SS-CK spread spectrum clock signal Data input image signal _{T H} horizontal scanning period _{T V} vertical scanning period Ton writing period Tss fluctuation cycle

Claims (14)

A reference clock signal and an input image signal are input to a display device having a display screen in which a large number of picture elements are arranged in a matrix, and the frequency of the reference clock signal is continuously changed at a predetermined fluctuation period. A spread clock signal is generated, and a display signal to be written to each picture element is generated based on the input image signal, and each picture element is set for each row at a predetermined horizontal scanning period synchronized with the frequency spread clock signal. A method of driving a display device that sequentially selects and writes the display signal,
A driving method of a display device, wherein the fluctuation period of the frequency spread clock signal and the horizontal scanning period are synchronized.   The display according to claim 1, wherein the number of clocks of the frequency spread clock signal in one horizontal scanning cycle is an integer multiple of the number of clocks in one cycle of the fluctuation cycle of the frequency spread clock signal. Device driving method.   2. The method of driving a display device according to claim 1, wherein when the number of clocks of the frequency spread clock signal reaches a predetermined value, a change in frequency of the frequency spread clock signal is reset.   A shift between the fluctuation period of the frequency of the frequency spread clock signal and the horizontal scanning period for sequentially writing the display signals by selecting the pixels for each row is detected, and the fluctuation period and the horizontal scanning period are detected. 4. The display device driving method according to claim 1, wherein the fluctuation period and / or the horizontal scanning period are corrected so as to synchronize with each other. 5.   The method for driving a display device according to claim 1, wherein the display device is a liquid crystal display device.   A display device that is driven by using the method for driving a display device according to claim 1. A display device that receives a reference clock signal and an input image signal and displays an image corresponding to the input image signal on a display screen in which a large number of picture elements are arranged in a matrix,
A frequency spread clock signal generator that continuously varies the frequency of the reference clock signal at a predetermined period to generate a frequency spread clock signal;
A display signal generator for generating a display signal to be written in each picture element of the display screen based on the input image signal;
A scanning signal generation unit that generates a scanning signal that sequentially selects the pixels for each row in a predetermined horizontal scanning period synchronized with the frequency spread clock signal;
A display device characterized in that the fluctuation cycle in which the frequency of the frequency spread clock signal fluctuates is synchronized with a horizontal scanning cycle in which the picture elements are sequentially selected for each row.   The scanning signal generation unit generates the scanning signal so that the number of clocks corresponding to one period of the fluctuation period of the frequency spread clock signal is an integral multiple of the number of clocks corresponding to one period of the horizontal scanning period. The display device according to claim 7.   The frequency spread clock signal generation unit resets the frequency fluctuation of the frequency spread clock signal when the number of clocks of the frequency spread clock signal reaches the number of clocks corresponding to one cycle of the horizontal scanning period of the display device. The display device according to claim 7, wherein the display device is characterized. A synchronization shift detection unit that detects a shift between the fluctuation period in which the frequency of the frequency spread clock signal fluctuates and the horizontal scanning period;
The scanning signal generation unit corrects the frequency spread clock signal and / or the scanning signal so that the fluctuation period and the horizontal scanning period are synchronized based on the deviation detected by the synchronization deviation detection unit. The display device according to claim 7.   11. The display device according to claim 7, wherein the display signal generation unit and the scanning signal generation unit are built in the same ASIC (Application Specific Integrated Circuit).   The display device according to claim 11, further comprising a frequency spread clock generator built in an ASIC (application-specific integrated circuit).   The display device according to claim 7, wherein a liquid crystal display panel in which liquid crystal is held between a pair of transparent substrates constitutes the display screen.   14. A television receiver comprising receiving means for receiving broadcast radio waves and display means for displaying broadcast contents of the broadcast radio waves received by the receiving means, wherein the display means is any one of claims 6 to 13. A television receiver comprising the display device according to claim 1.

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