JP2008211708A - Signal line monitoring circuit, protection method and electronic device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the hacking of data transmitted on a signal line 104. <P>SOLUTION: A charging circuit 20 supplies a current to a terminal 102 connected to the signal line 104 on which data to be protected are transmitted. A determination unit 30 compares a transition time Tx required for changing a voltage Vx of the terminal 102 only by a predetermined amount Vth by charging by the charging circuit 20 with predetermined times Ty1, Ty2. In the case of Ty1<Tx<Ty2, as a result, the absence of an abnormality is determined or in the case of Tx<Ty1 or Ty2<Tx, the presence of the abnormality is determined. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for preventing hacking of data transmitted through a signal line.

When data transmitted through a signal line connecting electronic circuits and electronic devices is monitored, problems such as unauthorized copying and leakage of information occur. In order to avoid such a problem, measures such as data protection using a password and data protection by encryption are taken. Such data protection techniques are often executed by software processing.
Japanese Patent Laid-Open No. 5-100958

  However, in order to realize more robust data protection, it is desirable to protect data by a hardware mechanism in addition to software protection. The present invention has been made in view of such circumstances, and a comprehensive object thereof is to provide a more reliable data protection technique.

  One embodiment of the present invention relates to a signal line monitoring circuit. The signal line monitoring circuit includes a charging circuit that supplies current to a terminal connected to a signal line that transmits data to be protected, and a transition time required for the terminal voltage to change by a predetermined amount due to charging by the charging circuit. And a determination unit that compares the value with a predetermined time.

  Another embodiment of the present invention is also a signal line monitoring circuit. This signal line monitoring circuit has a discharge circuit that extracts charges from a terminal connected to a signal line that transmits data to be protected, and a transition time required for the terminal voltage to change by a predetermined amount due to discharge by the discharge circuit. And a determination unit for comparing with a predetermined time.

  The combined capacitance such as the terminal and the signal line connected thereto is often known at the design stage of the set. Therefore, the transition time required to charge the terminal and generate a predetermined voltage change can be estimated at the design stage. If an unexpected probe or wiring is connected to the terminal, the capacitance deviates from the design value, and the transition time deviates from the value estimated in the design stage. Therefore, according to this aspect, it is possible to detect that a probe or wiring is connected to the signal line.

  Another embodiment of the present invention is also a signal line monitoring circuit. The signal line monitoring circuit is configured to supply a current to a terminal connected to a signal line through which data to be protected is transmitted during a predetermined charging period, and to set a voltage at a terminal after charging by the charging circuit to a predetermined level. And a determination unit for comparing with a threshold voltage.

  Another embodiment of the present invention is also a signal line monitoring circuit. This signal line monitoring circuit applies a predetermined voltage to a discharge circuit that extracts charges from a terminal connected to a signal line through which data to be protected is transmitted during a predetermined discharge period, and a voltage at a terminal after discharge by the discharge circuit. And a determination unit for comparing with a threshold voltage.

  The combined capacitance such as the terminal and the signal line connected thereto is often known at the design stage of the set. Therefore, if the terminal is charged or discharged for a predetermined time, a predetermined voltage change should occur. If an unexpected probe or wiring is connected to the terminal, the capacitance deviates from the design value, and the voltage change deviates from the predetermined value. Therefore, according to this aspect, it is possible to detect that a probe or wiring is connected to the signal line.

  The signal line monitoring circuit may further include an initialization circuit that initializes the terminal voltage.

  The determination unit compares the voltage of the terminal with a predetermined threshold voltage, a plurality of latch circuits that latch the output of the comparator at different timings, and the transition time and the predetermined time based on the output of the latch circuit. And a logic gate for determining a magnitude relationship.

  Yet another embodiment of the present invention is an electronic device. This electronic device has at least an internal circuit that transmits or receives data to be protected through a signal line, a buffer circuit provided between the signal line and the internal circuit, and any of the above that monitors the signal line. And a signal line monitoring circuit according to the above aspect. The buffer circuit is set to high impedance while the signal line monitoring circuit monitors the signal line.

  Yet another embodiment of the present invention is a signal line protection method. This method is a signal line protection method for transmitting data to be protected, the step of initializing the voltage of a terminal connected to the signal line for transmitting data to be protected, the step of charging the terminal, and the charging The transition time required for the terminal voltage to change by a predetermined amount is compared with the predetermined time, and a predetermined protection process is executed when the transition time deviates from the predetermined time.

  According to the present invention, it is possible to detect an unexpected reading of data from a signal line.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A and the member B are connected” means that the member A and the member B are physically directly connected, or the member A and the member B are in an electrically connected state. Including the case of being indirectly connected through other members that do not affect the above.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical connection. The case where it is indirectly connected through another member that does not affect the state is also included.

  FIG. 1 is a circuit diagram showing a configuration of a signal line monitoring circuit 10 according to the embodiment. The first circuit 100 and the second circuit 200 are connected via the signal line 104, and data to be protected is transmitted. The data transmitted through the signal line 104 may be analog or digital. For example, the second circuit 200 is an IC card, and the first circuit 100 is an IC card reader.

  The first circuit 100 includes a signal line monitoring circuit 10, an input tristate buffer 50, an output tristate buffer 52, and an internal circuit 54. The internal circuit 54 transmits and receives data to be protected via the signal line 104. The internal circuit 54 may perform only data transmission or reception. The input tristate buffer 50 and the output tristate buffer 52 are provided between the signal line 104 and the internal circuit 54. The signal line monitoring circuit 10 monitors the signal line 104.

  The parasitic capacitance C1 connected to the signal line 104 schematically shows a combined capacitance of the terminal 102, the signal line 104, and the internal wiring 106 connected to the terminal 102.

The signal line monitoring circuit 10 includes a charging circuit 20, an initialization transistor M2, a control unit 22, and a determination unit 30.
The charging circuit 20 supplies current to the terminal 102. The charging circuit 20 includes, for example, a charging transistor M1 and a resistor R1. The charging transistor M1 is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and a power supply voltage Vdd is applied to the source. The resistor R1 is provided between the drain of the charging transistor M1 and the terminal 102. A control signal SW1 is input to the gate of the charging transistor M1. When the control signal SW1 is at a low level, the charging transistor M1 is turned on, a charging path through the resistor R1 is formed, and the terminal 102 is charged. The charging circuit 20 may be composed of a constant current source.

  The initialization transistor M2 functions as an initialization circuit that initializes the voltage Vx of the terminal 102. The initialization transistor M2 is an N-channel MOSFET, its source is grounded, and its drain is connected to the terminal 102. A control signal SW2 is input to the gate of the initialization transistor M2. When the control signal SW2 is at a high level, the initialization transistor M2 is turned on, and the voltage Vx of the terminal 102 is initialized to the ground voltage 0V.

The determination unit 30 compares the transition time Tx required for the voltage Vx at the terminal 102 to change by a predetermined amount ΔV due to charging by the charging circuit 20 with the predetermined time Ty.
In order to realize this function, the determination unit 30 includes a comparator 32, a plurality of flip-flops FF1 to FF3, a first inverter 42, a second inverter 44, and an AND gate 46.

  The comparator 32 compares the voltage Vx at the terminal 102 with a predetermined threshold voltage Vth. The comparator 32 outputs a detection signal S1 that is at a high level when Vx> Vth and at a low level when Vx <Vth.

  The plurality of flip-flops FF1 to FF3 latch the detection signal S1 that is the output of the comparator 32 at different timings. Clocks CK1 to CK3 that sequentially become high level are input to the clock terminals of the first flip-flop FF1 to the third flip-flop FF3. The clocks CK1 to CK3 sequentially become high level at predetermined intervals.

  The first inverter 42, the second inverter 44, and the AND gate 46 determine the magnitude relationship between the transition time Tx and the predetermined time Ty based on the outputs of the first flip-flop FF1 to the third flip-flop FF3. The first inverter 42 inverts the output S2 of the first flip-flop FF1. The second inverter 44 inverts the output S3 of the second flip-flop FF2. The AND gate 46 outputs a logical product of the output * S2 of the first inverter 42, the output * S3 of the second inverter 44, and the output S4 of the third flip-flop FF3. The output signal S5 of the AND gate 46 is data indicating a monitoring result by the signal line monitoring circuit 10.

  The control unit 22 uses the system clock CKsys to generate control signals SW1 and SW2 and clocks CK1 to CK3, and controls the operation of the signal line monitoring circuit 10.

  The above is the configuration of the signal line monitoring circuit 10. Hereinafter, the operation will be described. FIG. 2 is a time chart showing the operation of the signal line monitoring circuit 10 of FIG. The normal operation is indicated by a solid line, and the operation when an abnormality occurs is indicated by a dashed line.

First, normal operation will be described. The signal line monitoring circuit 10 becomes active at time t0 prior to data transmission between the first circuit 100 and the second circuit 200, and monitors the state of the signal line 104. In the initial state, the control signal SW1 is high level and SW2 is low level.
During monitoring, the input tristate buffer 50 and the output tristate buffer 52 are set to high impedance. As a result, the influence on the parasitic capacitance C1 of the input tristate buffer 50 and the output tristate buffer 52 is suppressed.

  Subsequently, at time t1, the control signal SW2 becomes high level, and the voltage Vx at the terminal 102 is initialized to the ground voltage. Subsequently, at time t2, the control signal SW1 becomes low level and the charging transistor M1 is turned on. At this time, the clock CK1 becomes high level and the detection signal S1 of the comparator 32 is latched. Since time t2 is immediately after initialization, Vx <Vth, and the output signal S2 of the first flip-flop FF1 is at a low level.

  When the charging transistor M1 is turned on, the parasitic capacitance C1 associated with the terminal 102 is charged through the charging transistor M1 and the resistor R1. As a result, the voltage Vx at the terminal 102 increases with time. At time t3 when a predetermined time Ty1 has elapsed from time t2 when charging is started, the clock CK2 becomes high level. At this time, since Vx <Vth and the detection signal S1 is at the low level, the output signal S3 of the second flip-flop FF2 is at the low level.

When Vx> Vth at time t4, the detection signal S1 of the comparator 32 becomes high level.
Thereafter, the clock CK3 goes high at time t5 when a predetermined time Ty2 has elapsed from time t2 when charging starts, and the output signal S4 of the third flip-flop FF3 goes high. As a result, the output signal S5 of the AND gate 46 becomes high level at time t5, and the normal state is confirmed.

That is, the transition time Tx required for the voltage Vx of the terminal 102 to change from 0 V to Vth is compared with the predetermined time Ty1 and the predetermined time Ty2. As a result of the comparison, if the following inequality (1) holds, the signal S5 becomes a high level, and if not, the signal S5 becomes a low level.
Ty1 <Tx <Ty2 (1)

  In other words, in the present embodiment, the values of the predetermined times Ty1 and Ty2 may be set so as to satisfy the inequality (1) when the parasitic capacitance C1 is in a predetermined range. The values of Ty1 and Ty2 can be realized by adjusting the timing of the clocks CK1 to CK3.

  Next, an operation when an unexpected impedance such as a probe or wiring is connected to the signal line 104 will be described. When the impedance connected to the signal line 104 is capacitive, the value of the parasitic capacitance C1 is larger than the design value. As a result, the transition time Tx until the voltage Vx at the terminal 102 reaches the threshold voltage Vth becomes longer. As a result, if Ty2 <Tx, the signal S5 maintains the low level, and it is detected that an unexpected capacity is connected.

  As described above, according to the signal line monitoring circuit 10 according to the present embodiment, the abnormal state in which the probe or the wiring is connected to the signal line 104 is detected by monitoring the parasitic capacitance C1 associated with the terminal 102. Can do. When detecting an abnormality, the internal circuit 54 can execute a protection process such as not performing transmission / reception of data with the second circuit 200.

When the charging circuit 20 is composed of the charging transistor M1 and the resistor R1, the transition time Tx is
Tx = −CR · ln (1−Vth / Vdd) (2)
Given in. Here, C is a capacitance value of the parasitic capacitance C1, R is a resistance value of the resistor R1, and ln is a natural logarithm. Therefore, the transition time Tx suitable for signal processing can be set by adjusting the resistance value of the resistor R1 and the threshold voltage Vth according to the capacitance value of the parasitic capacitance C1. Furthermore, since the predetermined times Ty1 and Ty2 compared with the transition time Tx can be suitably controlled by the timing of the clocks CK1 to CK3, it is possible to determine an abnormality with respect to an arbitrary capacitance value.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there. Hereinafter, a modification is illustrated.

In the circuit of FIG. 1, the case where the charging circuit 20 charges the parasitic capacitance C1 and the capacitance value of the parasitic capacitance C1 is determined based on the transition time Tx required for the voltage change has been described. On the other hand, in the modified example, a discharge circuit that extracts charges from the terminal 102 may be provided instead of the charging circuit 20. In this case, the discharge circuit may include an N-channel MOSFET discharge transistor and a discharge resistor. The discharge transistor and the discharge transistor may be provided in series between the terminal 102 and the ground terminal.
An initialization transistor M2 that is an initialization circuit may be provided as a P-channel MOSFET between the power supply voltage Vdd and the terminal 102.

  According to this modification, when the initialization transistor M2 is turned on, the voltage Vx at the terminal 102 is initialized to the power supply voltage Vdd. Thereafter, the voltage Vx is gradually lowered by the discharge circuit, and a function equivalent to the circuit of FIG. 1 can be realized by comparing the transition time Tx until Vx <Vth is satisfied with a predetermined time.

Furthermore, another modified example will be described. The circuit in FIG. 1 measured the transition time Tx and indirectly measured the parasitic capacitance C1. On the other hand, in the modified example, the time for charging the terminal 102 is set constant, and the voltage change Vx generated by the charging is compared with a predetermined voltage.
In this modification, the charging circuit 20 supplies current to the terminal 102 for charging during a predetermined charging period. The comparator 32 compares the voltage Vx of the terminal 102 after charging by the charging circuit 20 with a predetermined threshold voltage.

  In the case where the charging period is constant, if the capacitance value of the parasitic capacitance C1 changes, the voltage change ΔV caused by the charging period changes. That is, if the parasitic capacitance C1 is a design value, the voltage change ΔV is also included in the range of the predetermined design value, and if an unexpected impedance is added to the signal line 104, the voltage change ΔV has a predetermined design value. Deviate from scope. Therefore, according to this modification, the abnormality of the signal line 104 can be detected by comparing the voltage change ΔV with the threshold voltage.

  Further, the comparator 32 may be omitted and the inverter threshold voltage Vt (= Vdd / 2) may be used. Further, the voltage Vx may be directly input to the input terminals of the first flip-flop FF1 to the third flip-flop FF3. In this case, the circuit area can be reduced.

  Although the present invention has been described based on the embodiments, the embodiments merely illustrate the principle and application of the present invention, and the embodiments are intended to include the idea of the present invention defined in the claims. Many modifications and changes in arrangement are possible within the range not leaving.

It is a circuit diagram which shows the structure of the signal line monitoring circuit which concerns on embodiment. It is a time chart which shows the operation | movement of the signal line monitoring circuit of FIG.

Explanation of symbols

  10 signal line monitoring circuit, 20 charging circuit, M1 charging transistor, R1 resistance, M2 initialization transistor, 22 control unit, 30 determination unit, 32 comparator, 42 1st inverter, 44 2nd inverter, 46 AND gate, FF1 1st Flip-flop, FF2 second flip-flop, FF3 third flip-flop, 50-input tri-state buffer, 52-output tri-state buffer, 54 internal circuit, 100 first circuit, 102 terminal, 104 signal line, C1 parasitic capacitance, 200 second circuit.

Claims (6)

A charge / discharge circuit for charging or discharging at least a terminal connected to a signal line for transmitting data to be protected;
A determination unit that compares a transition time required for the voltage of the terminal to change by a predetermined amount by charging or discharging by the charge / discharge circuit with a predetermined time;
A signal line monitoring circuit comprising: A charge / discharge circuit that charges or discharges at least a terminal connected to a signal line for transmitting data to be protected during a predetermined charging period;
A determination unit that compares the voltage of the terminal after charging or discharging by the charge / discharge circuit with a predetermined threshold voltage;
A signal line monitoring circuit comprising:   The signal line monitoring circuit according to claim 1, further comprising an initialization circuit that initializes the voltage of the terminal. The determination unit
A comparator for comparing the voltage of the terminal with a predetermined threshold voltage;
A plurality of latch circuits for latching the outputs of the comparators at different timings;
A logic gate for determining a magnitude relationship between the transition time and the predetermined time based on an output of the latch circuit;
The signal line monitoring circuit according to claim 1, comprising: An internal circuit that transmits or receives at least data to be protected via a signal line;
A buffer circuit provided between the signal line and the internal circuit;
The signal line monitoring circuit according to claim 1 or 2, wherein the signal line is monitored;
With
The electronic apparatus according to claim 1, wherein the buffer circuit is set to high impedance while the signal line monitoring circuit monitors the signal line. A signal line protection method for transmitting data to be protected,
Initializing a voltage of a terminal connected to a signal line for transmitting data to be protected;
Charging or discharging the terminal;
Comparing a transition time required for the voltage of the terminal to change by a predetermined amount by charging or discharging with a predetermined time, and executing a predetermined protection process when the transition time deviates from the predetermined time;
A signal line protection method comprising:

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