JP2008210979A - Nonvolatile semiconductor memory, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve and secure a working margin of an intermediate insulating film of a selective gate transistor. <P>SOLUTION: A nonvolatile semiconductor memory has a memory cell transistor MC and a selective gate transistor SGD disposed at the end of the memory cell transistor MC. The selective gate transistor SGD is constituted of: a first gate electrode 3B formed on a gate insulating film 2B; an intermediate insulating film 4B formed on the first gate electrode 3B; a second gate electrode 5B formed on the intermediate insulating film 4B and on an element separately insulating film 9; an opening X formed in the intermediate insulating film 4B and in the second gate electrode 5B and extended to the first gate electrode 3B; and a third gate electrode 6B formed in the opening X. The first gate electrode 3B has a protruding portion P on its top surface, and the top surface of the protruding portion P is exposed to the opening X, and further, the third gate electrode 6B is made to contact directly with the first gate electrode 3B. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory and a method for manufacturing the same, and more particularly to a gate electrode of a select gate transistor.

  As a nonvolatile semiconductor memory mounted on an electronic device, for example, a NAND flash memory is widely used.

  The NAND flash memory has a plurality of NAND cell units each composed of a plurality of memory cell transistors and select gate transistors arranged at both ends thereof.

  When the gate electrode of the memory cell transistor has a stacked gate structure including a floating gate electrode and a control gate electrode, the select gate transistor is formed simultaneously with the memory cell transistor to simplify the manufacturing process. A similar stacked gate structure is obtained.

  However, the select gate transistor has intermediate insulation interposed between the lower electrode corresponding to the floating gate electrode of the memory cell transistor and the upper electrode corresponding to the control gate electrode of the memory cell transistor in order to facilitate threshold voltage control. An opening is formed in the film, and the lower electrode and the upper electrode are electrically connected through the opening (see, for example, Patent Document 1).

  When the control gate electrode of the memory cell transistor has a two-layer structure, processing for forming an opening in the intermediate insulating film of the select gate transistor is performed by controlling the lower control gate electrode material (hereinafter referred to as the second gate electrode material). After the is formed.

  The intermediate insulating film of the select gate transistor is processed to be over-etched in order to secure a processing margin in the wafer. Therefore, the upper surface of the floating gate electrode material (hereinafter referred to as the first gate electrode material) that becomes the lower electrode of the select gate transistor is also etched. Thereafter, the natural oxide film formed on the exposed surface of the first gate electrode material is removed by wet etching using an HF solution.

  The second gate electrode material is also formed on the element isolation insulating film that separates the first gate electrode material, and the second gate electrode material is also etched when the above-described opening is formed. The second gate electrode material on the element isolation insulating film serves as a protective film for the element isolation insulating film when wet etching with HF solution is performed. However, if the second gate electrode material does not remain on the element isolation insulating film due to etching at the time of forming the opening, the HF solution damages the element isolation insulating film made of silicon oxide.

Until now, since the film thickness of the first gate electrode material has been large, the difference between the height of the upper surface of the element isolation insulating film and the height of the upper surface of the first gate electrode material is large, and the second gate electrode material It was possible to secure a processing margin such that the gate electrode material remained, and to control the etching. However, as the miniaturization of memory cell transistors progresses and the film thickness of the first gate electrode material and the like decreases, the difference between the height of the upper surface of the element isolation insulating film and the height of the upper surface of the first gate electrode material increases. It becomes difficult to secure a processing margin such that the second gate electrode material remains on the element isolation insulating film, and it is very difficult to control the etching as described above.
JP 2002-176114 A

  The example of the present invention proposes a technique capable of improving and ensuring the processing margin of the intermediate insulating film of the select gate transistor.

  A nonvolatile semiconductor memory according to an example of the present invention includes a memory cell transistor and a selection gate transistor disposed at one end of the memory cell transistor, and the selection gate transistor is an active region surrounded by an element isolation insulating film. A first gate electrode formed on the gate insulating film formed on the region; an intermediate insulating film formed on the first gate electrode; and formed on the intermediate insulating film and the element isolation insulating film. A second gate electrode, an opening formed in the intermediate insulating film and the second gate electrode, reaching the first gate electrode, and a third gate electrode formed in the opening The first gate electrode has a convex portion on the upper surface, the upper surface of the convex portion is exposed to the opening, and the third gate electrode is in direct contact with the first gate electrode. Provided that it is.

A method for manufacturing a nonvolatile semiconductor memory according to an example of the present invention includes a step of forming a first gate electrode material on a gate insulating film on a surface of a semiconductor substrate, and etching the first gate electrode material and the semiconductor substrate. Forming a groove and forming an element isolation insulating film in the groove;
Forming a convex portion on the first gate electrode material; forming an intermediate insulating film on the first gate electrode material on which the convex portion is formed; and A step of forming a second gate electrode material, a step of forming a slit-shaped first mask extending over the first gate electrode material and the element isolation insulating film, and the second mask using the first mask as a mask. Etching the gate electrode material and the intermediate insulating film to form an opening through which the upper surface of the convex portion is exposed; removing the first mask; and directly contacting the first gate electrode material Forming a third gate electrode material on the second gate electrode material and in the opening; the first gate electrode material; the second gate electrode material; the intermediate insulating film; Selective removal of gate electrode material Comprising by comprising a step of forming a stacked gate electrode of the over phototransistor.

  According to the example of the present invention, the processing margin of the intermediate insulating film of the select gate transistor can be improved and secured.

  The best mode for carrying out an example of the present invention will be described below in detail with reference to the drawings.

1. Overview
Embodiments described herein relate generally to a structure and a manufacturing method of a select gate transistor of a nonvolatile semiconductor memory.

  A selection gate transistor according to an embodiment of the present invention has a stacked gate structure in which a first gate electrode, a second gate electrode, and a third gate electrode are stacked. The first gate electrode and the second gate An intermediate insulating film is interposed between the electrodes.

  In the select gate transistor, the first gate electrode formed on the gate insulating film has a convex portion on the upper surface, and the opening formed in the intermediate insulating film and the second gate electrode on the upper surface of the convex portion is formed. The third gate electrode is in direct contact with the first gate electrode.

  As described above, when the first gate electrode has a convex portion, when the opening is formed in the intermediate insulating film, overetching may be performed on the convex portion.

  Therefore, when the opening is formed, even if the height of the convex portion of the second gate electrode material on the element isolation insulating film is over-etched, the lower end of the convex portion and the upper end of the element isolation insulating film are formed. Thus, the second gate electrode material can be left as much as the level difference due to the above.

  Therefore, by forming the convex portion on the upper surface of the first gate electrode, the processing margin is improved by the height of the convex portion, and accordingly, the processing margin of the intermediate insulating film of the select gate transistor can be secured.

2. Embodiment
Next, an embodiment that seems to be the best will be described.

(A) Structure
In this embodiment, a NAND flash memory will be described as an example.

  FIG. 1 is a schematic diagram of a NAND flash memory according to the present embodiment. The memory cell array portion, which is a storage area, has a plurality of blocks BK1, BK2,. Each of the blocks BK1, BK2,... BKn has a plurality of NAND cell units as basic units.

  A row decoder circuit is provided in the row direction of the memory cell array portion, and a sense amplifier circuit is provided in the column direction. Further, a control circuit such as a booster circuit is provided on the same chip.

  FIG. 2 is a diagram showing an equivalent circuit of the memory cell array unit. One NAND cell unit includes a plurality of memory cell transistors MC and select gate transistors SGD and SGS connected to one end and the other end thereof.

  The memory cell transistors MC adjacent in the column direction share the source / drain and are connected in series.

  The word line WL extends in the row direction and is commonly connected to the control gate terminal of the memory cell transistor MC of the NAND cell unit adjacent in the row direction.

  A selection gate transistor SGD is connected to one end (drain side) of the plurality of memory cell transistors MC, and a selection gate transistor SGS is connected to the other end (source side). These select gate transistors SGD and SGS share the source / drain with the adjacent memory cell transistor MC and are connected in series with the memory cell transistor MC. The selection gate transistors SGD and SGS function as gates for supplying a predetermined potential to the memory cell transistor MC in the unit at the time of data writing and data reading.

  A selection gate line SGDL extending in the row direction is connected to the gate terminal of the selection gate transistor SGD, and a selection gate line SGSL extending in the row direction is connected to the gate terminal of the selection gate transistor SGS. The selection gate lines SGDL and SGSL are provided for controlling on / off of the selection gate transistors SGD and SGS.

  The bit line BL is connected to the drain terminal of the select gate transistor SGD and extends in the column direction. The source line SL is connected to the source terminal of the select gate transistor SGS and extends in the row direction.

  A plurality of NAND cell units are arranged in the row direction and the column direction to constitute a memory cell array unit.

  As shown in FIG. 1, a plurality of blocks BK1, BK2,... BKn are arranged in the column direction. Accordingly, as shown in FIG. 2, the two select gate transistors SGD of the NAND cell units adjacent in the column direction are arranged to face each other and are connected so as to share the bit line BL. Further, two select gate transistors SGS of NAND cell units adjacent in the column direction are arranged to face each other and are connected so as to share the source line SL.

  Next, a structure of the selection gate transistor in this embodiment is described.

  FIG. 3 is a plan view showing the structure of region A shown in FIG. 4A is a cross-sectional view taken along line IVA-IVA in FIG. 3, and FIG. 4B is a cross-sectional view taken along line IVB-IVB in FIG. 4C is a cross-sectional view taken along line IVC-IVC in FIG. Note that the channel width direction shown in FIGS. 3 to 4C is a direction in which the selection gate line and the word line extend and is equal to the row direction. The channel length direction is the direction in which the bit line extends and is equal to the column direction.

  An active area AA in which an element is formed is provided on the surface of the semiconductor substrate 1, and an active area AA adjacent in the channel width direction is isolated by an element isolation area STI.

  In the active area AA, a memory cell transistor MC and a select gate transistor SGD are provided. Here, a region where the memory cell transistor MC is arranged is a memory cell region, and a region where the selection gate transistor SGD is arranged is a selection gate region.

  As shown in FIGS. 4A and 4B, the memory cell transistor MC has a stacked gate structure including a floating gate electrode 3A and control gate electrodes 5A and 6A.

  The floating gate electrode 3A is formed on a gate insulating film (tunnel oxide film) 2A formed on the surface of the semiconductor substrate 1.

  The control gate electrodes 5A and 6A have a two-layer structure, and are formed so as to cover the upper surface and side surfaces of the floating gate electrode 3A via the intermediate insulating film 4A. The control gate electrodes 5A and 6A function as word lines and are shared by memory cell transistors MC adjacent in the channel width direction.

  When the ratio of the thickness of the floating gate electrode 3A to the floating gate electrode 3A is set to 1, for example, the ratio of the thickness of the control gate electrodes 5A and 6A is 8 to 10. Set to

  Since the select gate transistor SGD is formed at the same time as the memory cell transistor MC, it has a stacked gate structure like the memory cell transistor MC.

  That is, the first gate electrode 3B formed simultaneously with the floating gate electrode 3A is formed on the gate insulating film 2B on the surface of the semiconductor substrate 1.

  The first gate electrode 3B has a convex portion P in which the height from the surface of the semiconductor substrate 1 at the center of the upper surface is higher than the height at the end of the upper surface. The first gate electrode 3B has a film thickness that is thicker than the above-described film thickness of the floating gate electrode 3A due to the presence of the projection P.

  The second and third gate electrodes 5B and 6B formed simultaneously with the control gate electrodes 5A and 6A are formed so as to cover the upper surface and side surfaces of the first gate electrode 3B via the intermediate insulating film 4B. The The second and third gate electrodes 5B and 6B function as selection gate lines and are shared by the selection gate transistors SGD adjacent in the channel width direction.

  As described above, the select gate transistor functions as a gate for supplying a predetermined potential to the memory cell transistor MC in the unit. That is, the first gate electrode does not need to function as a charge storage layer unlike the floating gate electrode.

  Therefore, as shown in FIGS. 4A and 4C, the first gate electrode 3B and the third gate electrode 6B are connected via the opening X formed in the intermediate insulating film 4B and the second gate electrode 5B. Thus, the threshold voltage control is easy. The opening X is formed on the upper surface of the convex portion P of the first gate electrode 3B.

  When the opening X is formed, over-etching for securing a processing margin may be performed on the convex portion P of the first gate electrode 3B. Therefore, the second gate electrode 5B that is etched simultaneously when the opening X is formed remains on the element isolation insulating film 9 at least by the level difference between the lower end of the convex part P and the upper end of the element isolation insulating film 9. It becomes a structure.

  That is, the upper surface of the element isolation insulating film 9 in the select gate region is covered with the second gate electrode 5B.

  Therefore, even if the memory cell transistor is miniaturized in the select gate transistor, the processing margin for forming the opening X is improved by forming the convex portion P on the upper surface of the first gate electrode 3B. A sufficient processing margin for processing can be secured.

  Accordingly, even if the natural oxide film removal step using the HF solution performed after the opening X is formed, the element isolation insulating film 9 is covered with the second gate electrode 5B, so that the upper surface is covered with the HF solution. There is no damage.

  Thus, the manufacturing yield of the NAND flash memory shown in this embodiment can be improved.

  Note that the gate structure of the selection gate transistor SGS shown in FIG. 2 has the same structure as that of the selection gate transistor SGD. Therefore, in the present embodiment, detailed description of the select gate transistor SGS is omitted.

  Note that the memory cell transistor MC may have a convex portion similarly to the select gate transistor SGD.

(B) Manufacturing method
The manufacturing method of the present embodiment will be described with reference to FIGS.

  First, one process of the manufacturing method of this Embodiment is demonstrated using FIG. 5A is a cross-sectional view in the channel length direction of the memory cell array portion, and FIG. 5B is a cross-sectional view in the channel width direction.

  As shown in FIG. 5, for example, a silicon oxide film 2 serving as a gate insulating film is formed on the semiconductor substrate 1 by using, for example, a thermal oxidation method. Subsequently, as a first gate electrode material, for example, a polysilicon film 3 is deposited on the silicon oxide film 2 by using, for example, a CVD (Chemical Vapor Diposition) method. At this time, the polysilicon film 3 is deposited thicker than the desired thickness of the floating gate electrode of the memory cell transistor. Next, after patterning for a desired channel width is performed on the polysilicon film 3, the polysilicon film 3, the silicon oxide film 2, and the semiconductor substrate 1 are, for example, RIE (Reactive Ion Etching) based on the patterning. Etching is performed sequentially by the method. As a result, a polysilicon film 3 having a desired channel width is obtained, and an element isolation groove is formed in the semiconductor substrate 1.

  Subsequently, one step of the manufacturing method will be described with reference to FIGS. In this embodiment, FIG. 6 shows a plan view of the process following FIG. 5, FIG. 7 (a) being along the line VIIa-VIIa in FIG. 6, and FIG. 7 (b) being along the line VIIb-VIIb in FIG. A cross-sectional view is shown.

  As shown in FIGS. 6 and 7, the element isolation insulating film 9 made of, for example, a silicon oxide film is formed on the upper surface of the polysilicon film 3 and the element isolation insulation by using, for example, a CVD method and a CMP (Chemical Mechanical Polishing) method. It forms so that the upper surface of the film | membrane 9 may correspond. Thereafter, a resist pattern 10 is formed on the upper surface of the polysilicon film 3 in a portion where the convex portion is formed in a later step in the selection gate region.

  Note that when the element isolation insulating film is etched in a later process, peripheral circuit portions such as a row decoder circuit do not need to be etched and are therefore covered with a resist. Therefore, after a resist is applied to the entire surface of the semiconductor substrate 1, patterning is performed so that the memory cell array portion is exposed. Therefore, the resist pattern 10 can be formed at the same time as the resist covering the peripheral circuit portion, and the manufacturing process and the manufacturing cost are not newly increased to form the resist pattern 10.

  Thereafter, in order to expose a part of the side surface of the polysilicon film 3 in the channel width direction, for example, RIE is performed so that the element isolation insulating film 9 is moved back to the semiconductor substrate side.

  In this etching, the polysilicon film 3 has a sufficient selection ratio with respect to the silicon oxide film constituting the element isolation insulating film 9. However, since the etching is performed on the entire surface, the polysilicon film 3 is also etched at a slower etching rate than the silicon oxide film and recedes to the semiconductor substrate side. At this time, the polysilicon film 3 covered with the resist pattern 10 in the selection gate region is not etched.

  Therefore, as shown in FIGS. 9A and 9B which are sectional views taken along lines IXa-IXa and IXb-IXb in FIGS. Can be formed. Further, the height of the upper end portion of the polysilicon film 3 which is the lower end (broken line portion) of the convex portion P is set to be higher than the upper end of the element isolation insulating film 9.

  In addition, the above-mentioned process shows the process in which the convex part P is formed only by the etch back performed on the semiconductor substrate 1 whole surface. In addition to this step, only the polysilicon film 3 may be etched again. As a result, the height of the convex portion P can be further secured, and the accuracy of film thickness control of the floating gate electrode in the memory cell region is improved.

  Next, one process of the manufacturing method of this embodiment is demonstrated using FIG. FIG. 10A is a cross-sectional view in the channel length direction of the memory cell array portion in the process following FIGS. 8 and 9, and FIG. 10B is a cross-sectional view in the channel width direction.

As shown in FIGS. 10A and 10B, for example, an ONO film 4 serving as an intermediate insulating film is deposited on the polysilicon film 3 by a CVD method. Subsequently, for example, a polysilicon film 5 serving as a lower electrode layer of the control gate electrode in the memory cell transistor is deposited by a CVD method. Further, for example, a TEOS film 11 serving as a hard mask is formed on the polysilicon film 5. The intermediate insulating film may be a high-k film such as Al ₂ O ₃ or HfSiON.

  Subsequently, one step of the manufacturing method according to the present embodiment will be described with reference to FIGS. 11 and 12. 11 is a plan view of the process following FIG. 10, FIG. 12 (a) is a cross-sectional view taken along line XIIa-XIIa in FIG. 11, and FIG. 12 (b) is a cross-sectional view taken along line XIIb-XIIb in FIG.

  As shown in FIGS. 11, 12A and 12B, the TEOS film 11 is patterned, and the TEOS film 11 and the polysilicon film 5 are etched by, for example, the RIE method. Thereby, the opening Y is formed. The opening Y is a slit-like opening extending over the active area AA and the element isolation area STI in the selection gate region. Therefore, the ONO film 4 and the polysilicon film 5 are exposed in the select gate region.

  Subsequently, one step of the manufacturing method according to the present embodiment will be described with reference to FIGS. 13 is a plan view of the process following FIGS. 11 and 12, FIG. 14A is a cross-sectional view taken along line XIVa-XIVa in FIG. 13, and FIG. 14B is a cross-sectional view taken along line XIVb-XIVb in FIG. Show.

  As shown in FIG. 13, FIG. 14A and FIG. 14B, the ONO film 4 and the polysilicon film 5 are etched by, for example, the RIE method to form the opening X.

  It is necessary to form an opening on the upper surface of each convex portion P by this etching. Therefore, in consideration of the processing margin in the wafer, so-called over-etching is performed in which not only the ONO film 4 but also the polysilicon film 3 and the polysilicon film 5 are etched.

  Even if the entire protrusion P is removed by overetching, the polysilicon film 5 is formed on the element isolation insulating film 9 on the lower surface (broken line) of the protrusion P and the upper surface of the ONO film 4 on the element isolation insulating film. Can be left as much as the level difference.

  Thereafter, the TEOS film is removed, and the entire surface of the semiconductor substrate 1 is etched with, for example, a hydrogen fluoride (HF) solution, and the natural oxide film on the polysilicon films 3 and 5 is removed. At this time, as shown in FIG. 14B, the upper surface of the element isolation insulating film 9 in the select gate region is covered with the polysilicon film 5. Therefore, the element isolation insulating film 9 is not etched by the HF solution.

  Subsequently, one step of the manufacturing method of the present embodiment will be described with reference to FIG. FIG. 15A shows a cross-sectional view in the channel length direction, and FIG. 15B shows a cross-sectional view in the channel width direction.

  As shown in FIG. 15, as the third gate electrode material, for example, a polysilicon film 6 is formed in the upper surface of the polysilicon film 5 and in the opening X so as to be in direct contact with the polysilicon film 3.

  Then, one process of the manufacturing method of this Embodiment is demonstrated using FIG. FIG. 16A shows a cross-sectional view in the channel length direction of the memory cell array portion, and FIG. 16B shows a cross-sectional view in the channel width direction.

  The first gate electrode material 3, the ONO film 4, the second gate electrode material 5, and the third gate electrode material 6 are selectively etched so as to obtain a desired channel length, and FIG. As shown in FIG. 16B, the stacked gate electrodes of the memory cell transistor MC and the select gate transistor SGD are formed. Further, diffusion layers 7A and 7B are formed in the semiconductor substrate 1 in a self-aligned manner with respect to the gate electrode.

  Thereafter, the insulating layer 8 is formed so as to cover the stacked gate electrodes of the memory cell transistor and the select gate transistor. Further, the bit line BL is connected to the diffusion layer 7B shared by the two select gate transistors SGD via the bit line contact portion BC formed in the insulating layer 8.

  As described above, the NAND flash memory according to the present embodiment is formed.

  As described above, the convex portion P is formed on the upper surface of the first gate electrode 3B of the selection gate transistor SGD.

  Thereby, when forming the opening X, over-etching for securing a processing margin may be performed on the convex portion P of the first gate electrode 3B.

  Therefore, the second gate electrode 5B that is etched simultaneously when the opening X is formed remains on the element isolation insulating film 9 at least by the level difference between the lower end of the convex part P and the upper end of the element isolation insulating film 9. .

  Therefore, the upper surface of the element isolation insulating film 9 in the select gate region can be covered with the second gate electrode 5B.

  Therefore, even if the memory cell transistor is miniaturized in the selection gate transistor, the processing margin is improved by forming the protrusion P on the upper surface of the first gate electrode 3B, and the opening is formed in the intermediate insulating film. The processing margin can be secured.

  As a result, even if the natural oxide film removing step with the HF solution performed after the opening X is formed, the element isolation insulating film 9 is not damaged by the HF solution.

  Thus, the manufacturing yield of the NAND flash memory shown in this embodiment can be improved.

  Note that the selection gate transistor SGS shown in FIG. 2 is manufactured in the same process as the selection gate transistor SGD. Therefore, in the present embodiment, the description of the method for manufacturing the select gate transistor SGS is omitted.

(C) Modification
Although the NAND flash memory has been described in the above embodiment, the example of the present invention can be applied to all nonvolatile semiconductor memories having a select gate transistor.

  For example, a NOR type flash memory composed of one memory cell transistor and one select gate transistor, a 3-Tr NAND type flash memory composed of one memory cell transistor and two select gate transistors sandwiching it, Can be applied to a 2-Tr type flash memory having both NAND type and NOR type characteristics.

3. Other
According to the example of the present invention, the processing margin of the intermediate insulating film of the select gate transistor can be improved and secured.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the scope of the invention. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

1 is a schematic diagram of a NAND flash memory in an embodiment. FIG. The equivalent circuit diagram of a memory cell array part. Sectional drawing which shows the structure of the area | region A shown in FIG. Sectional drawing which follows the IVA-IVA line | wire of FIG. Sectional drawing which follows the IVB-IVB line | wire of FIG. Sectional drawing which follows the IVC-IVC line | wire of FIG. Sectional drawing which shows 1 process of the manufacturing method of embodiment. The top view which shows 1 process of the manufacturing method of embodiment. Sectional drawing which follows the VIIa-VIIa line | wire and VIIb-VIIb line | wire of FIG. The top view which shows 1 process of the manufacturing method of embodiment. Sectional drawing which follows the IXa-IXa line | wire and IXb-IXb line | wire of FIG. Sectional drawing which shows 1 process of the manufacturing method of embodiment. The top view which shows 1 process of the manufacturing method of embodiment. Sectional drawing which follows the XIIa-XIIa line | wire and XIIb-XIIb line | wire of FIG. The top view which shows 1 process of the manufacturing method of embodiment. Sectional drawing which follows the XIVa-XIVa line | wire and XIVb-XIVb line | wire of FIG. Sectional drawing which shows 1 process of the manufacturing method of embodiment. Sectional drawing which shows 1 process of the manufacturing method of embodiment.

Explanation of symbols

  1: semiconductor substrate, 2A, 2B: gate insulating film, 3A: floating gate electrode, 3B: first gate electrode, P: convex portion, 4A, 4B: intermediate insulating film, X, Y: opening, 5A: first 1 control gate electrode, 5B: second gate electrode, 6A: second control gate electrode, 6B: third gate electrode, 7A, 7B: diffusion layer, 8: insulating layer, 9: element isolation insulating film, 10: resist pattern, 11: mask material, MC: memory cell transistor, SGD, SGS: selection gate transistor, AA: active region, STI: element isolation region, BC: bit line contact portion, BL: bit line.

Claims (5)

  A memory cell transistor; and a selection gate transistor disposed at one end of the memory cell transistor, wherein the selection gate transistor is formed on a gate insulating film formed on an active region surrounded by an element isolation insulating film A first gate electrode, an intermediate insulating film formed on the first gate electrode, a second gate electrode formed on the intermediate insulating film and the element isolation insulating film, and the intermediate insulation An opening formed in the film and in the second gate electrode and reaching the first gate electrode, and a third gate electrode formed in the opening, the first gate electrode being A non-volatile semiconductor memo having a convex portion on an upper surface, the upper surface of the convex portion is exposed in the opening, and the third gate electrode is in direct contact with the first gate electrode. .   The memory cell transistor includes a floating gate electrode formed on a gate insulating film formed on an active region surrounded by an element isolation insulating film, and a control formed on the floating gate electrode via an intermediate insulating film The nonvolatile semiconductor memory according to claim 1, further comprising a gate electrode, wherein the upper surface of the floating gate electrode is formed flat.   Forming a first gate electrode material on the gate insulating film on the surface of the semiconductor substrate; etching the first gate electrode material and the semiconductor substrate to form a groove; and forming an element isolation insulating film in the groove A step of forming, a step of forming a protrusion on the first gate electrode material, a step of forming an intermediate insulating film on the first gate electrode material on which the protrusion is formed, and the intermediate Forming a second gate electrode material on the insulating film; forming a slit-shaped first mask straddling the first gate electrode material and the element isolation insulating film; and Etching the second gate electrode material and the intermediate insulating film as a mask to form an opening exposing the upper surface of the convex portion; removing the first mask; and the first gate The third gate that is in direct contact with the electrode material Forming a first electrode material on the second gate electrode material and in the opening; the first gate electrode material; the second gate electrode material; the intermediate insulating film; and the third gate electrode material. And a step of forming a stacked gate electrode of a select gate transistor.   Forming the second mask on the upper surface of the first gate electrode material to cover a central portion in the plane of the first gate electrode, and using the second mask as a mask Etching is performed on the upper surface of the isolation insulating film and the upper surface of the first gate electrode material to form a convex portion on the upper surface of the first gate electrode material, and the step of removing the second mask. The method for manufacturing a nonvolatile semiconductor memory according to claim 3.   Forming the second mask on the upper surface of the first gate electrode material to cover a central portion in the plane of the first gate electrode, and using the second mask as a mask Etching the upper surface of the isolation insulating film and the upper surface of the first gate electrode material to form a convex portion on the upper surface of the first gate electrode material; and selectively only for the first gate electrode material 4. The method according to claim 3, wherein etching is performed to control a shape of a convex portion and a film thickness of the first gate electrode material, and a step of removing the second mask. 5. A method for manufacturing a nonvolatile semiconductor memory.

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