JP2008210849A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a capacitor in which a bore diameter can be enlarged sufficiently by preventing a short circuit between capacitors even under such conditions as a sufficient inter-capacitor distance cannot be obtained. <P>SOLUTION: The manufacturing method of a semiconductor device having a cylinder type capacitor structure comprises a step for forming a sacrifice film (104) on a semiconductor substrate, a step for providing a gap (106) between the sacrifice films by etching (104') the sacrifice film into cylinder shape, a step for forming a cylinder insulating film (107) in the gap between the sacrifice films, a step for forming a cylinder hole (108) by removing the sacrifice film selectively, a step for forming a lower electrode on the inner wall and the bottom of the cylinder hole, a step for forming a capacitor insulating film on the entire surface, and a step for forming an upper electrode on the entire surface. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a structure of a cylinder capacitor of a memory element such as a DRAM.

  In recent years, the increase in capacity and miniaturization of semiconductor devices has been accelerated, and in particular, DRAM (Dynamic Random Access Memory) has been commercialized as a gigabit class memory having a minimum processing dimension of 70 nm or less.

  In a capacitor, which is a main component of a DRAM, it is necessary to secure a predetermined capacity in order to prevent malfunction of a memory due to external noise such as an α-ray soft error, regardless of the miniaturization of elements. The capacitor capacity (C) is represented by the following formula (1).

C = εS / d (1)
(Ε represents the dielectric constant of the capacitive insulating film, S represents the electrode area, and d represents the thickness of the capacitive insulating film)

  With miniaturization, it is becoming difficult to ensure the capacitor area. Therefore, in order to secure a predetermined capacitance (C) with respect to the reduction of the electrode area, the dielectric constant ε of the capacitive insulating film is increased (use of a high dielectric constant material (High-K material)), or the capacitive insulating film It is necessary to reduce the thickness d.

  When the electrode area is further reduced by miniaturization, it is difficult to secure a sufficient capacity only by these measures.

  Under such circumstances, it has been practiced to form electrodes three-dimensionally to ensure a sufficient electrode area. One is to secure the electrode area by extending the capacitor in the vertical direction. Such capacitors are roughly classified into a stack type that is stacked upward and a trench type that is digged downward, but at present, the stack type is the mainstream. Among the stack types, a cylinder type capacitor in which a lower electrode is formed in a cylindrical shape can be cited as a structure suitable for large capacity and miniaturization. On the other hand, it has been proposed and put into practical use to form fine irregularities on the surface of the lower electrode to ensure the electrode area. A typical example is an HSG (Hemi Spherical Grain) technique in which the lower electrode is formed of polysilicon, a thin amorphous silicon film is deposited on the polysilicon surface, and Si grains are grown by low-temperature CVD using disilane or the like as a raw material. . At present, the electrode area is secured by forming HSG on the lower electrode of the cylinder type capacitor.

  In early cylinder capacitors, a lower electrode material was formed in the pores formed in the insulating film, and after removing the insulating film, a capacitor insulating film was provided on the inner wall and outer wall of the cylindrical portion of the lower electrode, and the upper electrode (So-called crown type capacitor). However, as the degree of integration increases, when the insulating film is made thicker and the pores are made deeper, there is a problem that the lower electrode is lifted or falls when the insulating film is removed. Therefore, it has been proposed to form a capacitor using only the inner wall without removing the insulating film surrounding the outer wall of the lower electrode. As a result, the cylinder type capacitor needs to form a lower electrode in a deeper pore to ensure an electrode area.

  In the gigabit class memory, a large number of cylinder-type capacitors must be erected in a predetermined region, and when it is attempted to form a capacitor having a predetermined hole diameter, it is difficult to obtain a sufficient distance between adjacent capacitors. Although it is only necessary to form the pores deeper, there is a limit to the formation of the high aspect ratio pores, and the capacitor formation itself becomes difficult. If such deep pores are formed under conditions where the distance between the capacitors cannot be sufficiently obtained, adjacent pores may be connected due to bowing during etching, which may cause a short circuit. Therefore, the hole diameter could not be expanded sufficiently.

Further, in a capacitor (so-called MIS (Metal-Insulator-Semiconductor) type capacitor) having HSG polysilicon as a lower electrode, when a tantalum oxide (Ta ₂ O ₅ ) having a high dielectric constant is used as a capacitor film, the capacitor film and the polysilicon are used. Since a thin silicon oxide film is formed at the interface with the layer and the capacitance is likely to be reduced, the lower electrode is made of a metal on which an oxide film is not formed, even if it is polysilicon capable of forming HSG. If a metallized capacitor (so-called MIM (Metal-Insulator-Metal) type capacitor) can be formed on the lower electrode, the effective capacitance can be increased. However, even with MIM type capacitors, as described above, it is difficult to increase the cylinder diameter due to the occurrence of bowing at the time of cylinder processing in a finely structured semiconductor device that forms a cylinder type capacitor. Since the electrode area cannot be secured, the capacitor capacity for improving the memory operation margin has not been obtained.

  It is an object of the present invention to provide a method for manufacturing a capacitor that can prevent a short circuit between capacitors and maximize the hole diameter by forming a cylinder having no bowing shape, that is, having a vertical side wall.

The present invention is a method for manufacturing a semiconductor device having a cylindrical capacitor structure,
Forming a sacrificial film on a semiconductor substrate;
Etching the sacrificial film into a cylinder shape and providing a gap between the sacrificial films;
A step of burying and forming a cylinder insulating film in a gap between the sacrificial films;
Removing the sacrificial film and forming a cylinder hole;
Forming a lower electrode on the inner wall and bottom of the cylinder hole;
The present invention relates to a method for manufacturing a semiconductor device including a step of forming a capacitive insulating film on the entire surface and a step of forming an upper electrode on the entire surface.

  In the present invention, a cylinder hole is not formed by forming a hole in the cylinder insulating film as a mold at the time of capacitor formation as in the prior art, but a sacrificial film in a region other than the cylinder hole is first etched to form a cylinder hole. A sacrificial film pillar is formed in the power region. Since the regions other than the cylinder holes are all continuously connected and have a large spatial expansion, ions in the plasma that contribute to the dry etching of the sacrificial film are not concentrated at specific locations to promote the lateral etching. Therefore, a sacrificial film column having a vertical sidewall can be formed. In the prior art, in order to form a cylinder hole in a closed space, the ions supplied into the hole scatter with a certain probability as the etching progresses and the depth of the hole increases. Although the bowing shape is generated by etching the specific portion in the lateral direction, the bowing shape is not generated in the present invention. Once the columnar sacrificial film is formed, the cylinder insulating film is embedded and formed between the remaining sacrificial films, and the columnar sacrificial film is removed, so that the insulating film can be reliably interposed between adjacent cylinders. It becomes possible. The cylinder hole formed by removing the columnar sacrificial film does not have a bowing shape and the side walls are vertical, so even if the distance between the cylinders is reduced to the limit, a short circuit between the cylinders can be prevented sufficiently. A capacitor with an enlarged hole diameter can be obtained.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
FIG. 1 is a process cross-sectional view illustrating the manufacturing method of the first embodiment of the present invention. As shown in FIG. 1A, a capacitor contact portion 102 connected to a cylinder type capacitor and an interlayer insulating film 101 serving as a base of the capacitor are formed in advance. The capacitor contact portion 102 is connected to an impurity diffusion region (source region) of a cell transistor (not shown). Next, as shown in FIG. 1B, a stopper nitride film 103 is formed to a thickness of, for example, about 50 nm in order to stop the etching of the cylinder-cylinder groove. Subsequently, in order to create a groove portion between the cylinders and cylinders, a silicon oxide film to be the sacrificial film 104 is formed to a film thickness of about 3 μm using a plasma CVD method. In the present invention, the depth of the cylinder hole, that is, the thickness of the sacrificial film 104 needs to be 2.5 μm or more. If it is set to 2 μm or less, the bowing problem can be avoided, but in this case, it is difficult to obtain the capacitor capacity necessary for the memory operation even if the MIM structure is adopted. Next, patterning is performed so that the resist pattern 105 remains in the cylinder formation scheduled region. Here, the minimum interval between adjacent cylinder formation scheduled regions is set to the resist resolution limit (for example, 70 nm). As shown in FIG. 1C, when dry etching (etchant gas: Ar + O ₂ + C ₄ F ₆ ) is performed using the resist pattern as a mask, a sacrificial film 104 ′ corresponding to the cylinder shape remains, and between the sacrificial films 104 ′. A gap 106 is formed. The side wall of the sacrificial film 104 ′ is formed vertically. When the remaining resist is removed, the structure shown in the sectional perspective view of FIG. 2 is obtained. Subsequently, as shown in FIG. 1D, a cylinder insulating film 107, which is an insulating film other than the capacitor film formed in the subsequent process and can selectively remove the sacrificial film 104 ′, for example, A silicon nitride film is formed to fill the gap, and the surface of the sacrificial film 104 ′ is exposed by CMP or etchback. The silicon nitride film is formed by LP-CVD (Low Pressure-Chemical Vapor Deposition) using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as source gases. Since this silicon nitride film has very good step coverage, the gap can be completely filled. As shown in FIG. 1E, wet etching is performed with an etching solution (hydrofluoric acid-containing solution) that can selectively remove the silicon oxide film of the sacrificial film 104 ′. Subsequently, the cylinder hole 108 is formed by dry etching the stopper nitride film 103 exposed after the removal of the sacrificial film 104 ′. The side wall of the cylinder hole 108 is formed vertically. A cross-sectional perspective view up to this step is shown in FIG. As shown in FIG. 1 (f), a lower electrode 109 (metal, Ti + TiN, etc.) is formed, etched back, and removed except for the inside of the cylinder hole 108. As shown in FIG. 1G, a capacitor film 110 (for example, Ta ₂ O ₅ , Al ₂ O ₃ , BST, STO, etc.) is formed using an ALD (Atomic Layer Deposition) method, and an upper electrode 111 (metal) , TiN + W, etc.) are formed by using the CVD method and the sputtering method, and the cylinder type capacitor is completed as shown in FIG.

  In the present invention, the sacrificial film in the region other than the cylinder hole is first etched to form the sacrificial film column in the region to be the cylinder hole. Since the regions other than the cylinder holes are all continuously connected and have a large spatial spread, ions in the plasma that contribute to the dry etching of the sacrificial film are not concentrated in a specific location to promote lateral etching. Therefore, the sacrificial film pillar 104 ′ having a vertical sidewall can be formed. As a result, the cylinder hole 108 whose side wall is vertical and does not have a bowing shape can be formed. Therefore, even if the cylinder interval is narrowed, the cylinder insulating film 107 can be reliably interposed between the cylinders, and there is no problem of short circuit that occurs when the cylinder interval is narrowed as in the prior art. Further, since the cylinder interval can be reduced to the limit, a sufficient electrode area can be ensured.

<Second Embodiment>
A method for narrowing the cylinder interval as compared with the first embodiment will be described below as a second embodiment.

  After the sacrificial film 104 as shown in FIG. 1B is formed in the same manner as in the first embodiment, a hard mask 201 is formed on the sacrificial film 104 to a thickness of about 500 to 800 nm (FIG. 1B). 5 (a)). As the hard mask 201, a conventionally known one can be used, and examples thereof include an amorphous carbon film and an amorphous silicon film. The photoresist 105 is patterned on the hard mask 201, and the hard mask 201 is etched using the photoresist 105 as a mask. The etching of the hard mask 201 is performed under the condition that the etching selectivity with the underlying sacrificial film 104 can be obtained. In the case of an amorphous carbon film, oxygen-containing plasma can be used, and in the case of an amorphous silicon film, chlorine-containing plasma can be used.

Next, after forming a nitride film to a thickness of about 10 nm on the entire surface, etch back is performed by dry etching using Ar, O ₂ , CHF ₃ gas, etc. A wall nitride film 202 is formed (FIG. 5B).

  As shown in FIG. 5C, the sacrificial film 104 is dry-etched through the sidewall nitride film 202 to form a cylinder-shaped sacrificial film 104 'in which the shortest distance between the sacrificial films is about 100 nm. As shown in FIG. 5D, the hard mask 201 and the sidewall nitride film 202 are removed by wet etching or the like. The subsequent manufacturing method is the same as that of the first embodiment. By making it like this embodiment, the space | interval between cylinders can be narrowed rather than 1st Embodiment, and it becomes possible to aim at the further expansion of a cylinder hole diameter.

<Third Embodiment>
In the first and second embodiments, the sacrificial film is an oxide film and the cylinder insulating film is a nitride film. However, the nitride film has higher film stress than the oxide film, and the wafer warps when the film thickness is increased. There is concern. Therefore, in the present embodiment, a method will be described in which polysilicon is used as the sacrificial film and the buried cylinder insulating film is an oxide film.

  First, instead of the silicon oxide film, a silicon film is formed as a sacrificial film by LP-CVD or the like. A silicon nitride film, an amorphous carbon film, or the like is formed thereon as a hard mask, and after processing the hard mask into a predetermined shape, the silicon film is etched using the hard mask as a mask to form a cylinder as shown in FIG. Form a shape. When a silicon oxide film is used as a sacrificial film, the etching becomes difficult as the depth increases.However, in the case of a silicon film, productivity is not affected by the depth and vertical etching is possible. improves.

Next, a silicon oxide film is formed by, for example, an LP-CVD method using dichlorosilane and dinitrogen monoxide (N ₂ O) as source gases, filling a gap between the cylinder-shaped sacrificial films, and polysilicon. The surface is planarized by CMP or the like until the surface is exposed. Thereafter, the silicon film is removed by wet etching or dry etching, thereby forming a cylinder hole in the silicon oxide film. Thereafter, the lower electrode, the capacitor insulating film, and the upper electrode are formed in the same manner to complete the capacitor.

It is process sectional drawing explaining the manufacturing method which becomes one Embodiment of this invention. It is a cross-sectional perspective view explaining the structure after the process of FIG.1 (c). It is a cross-sectional perspective view explaining the structure after the process of FIG.1 (e). It is sectional drawing of the capacitor structure formed through the process shown in FIG. It is process sectional drawing explaining the manufacturing method which becomes other embodiment of this invention.

Explanation of symbols

101 Interlayer insulating film 102 Capacitor contact portion 103 Stopper nitride film 104 Sacrificial film 104 ′ Cylinder-shaped sacrificial film 105 Resist pattern 106 Gap between cylinder-shaped sacrificial films 107 Cylinder insulating film 108 Cylinder hole 109 Lower electrode 110 Capacitor insulating film 111 Upper electrode 201 Hard mask 202 Side wall nitride film

Claims (6)

A method of manufacturing a semiconductor device having a cylinder-type capacitor structure,
Forming a sacrificial film on a semiconductor substrate;
Etching the sacrificial film into a cylinder shape and providing a gap between the sacrificial films;
A step of burying and forming a cylinder insulating film in a gap between the sacrificial films;
Selectively removing the sacrificial film to form a cylinder hole;
Forming a lower electrode on the inner wall and bottom of the cylinder hole;
A method for manufacturing a semiconductor device, comprising: forming a capacitive insulating film over the entire surface; and forming an upper electrode over the entire surface.   The method for manufacturing a semiconductor device according to claim 1, wherein the etching of the sacrificial film is performed by forming a hard mask on the sacrificial film, forming a predetermined opening in the hard mask, and then using the hard mask as a mask.   3. The semiconductor device according to claim 2, wherein after forming a predetermined opening in the hard mask, a sidewall nitride film is formed on a sidewall of the hard mask, and the sacrificial film is etched using the hard mask and the sidewall nitride film as a mask. Manufacturing method.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the sacrificial film is a silicon oxide film, and the cylinder insulating film to be embedded is a silicon nitride film.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the sacrificial film is a polysilicon film, and the cylinder insulating film to be embedded is a silicon oxide film.   6. The method of manufacturing a semiconductor device according to claim 1, wherein the cylinder type capacitor is an MIM capacitor in which both a lower electrode and an upper electrode are made of a metal material.

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