JP2008206084A - Phase synchronizing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase synchronizing circuit achieving high-speed calibration. <P>SOLUTION: A VCO 16 oscillates at a frequency fosc corresponding to an input control voltage Vcnt and includes regulation capacitors 50a and 50b for varying an oscillation frequency fosc for a certain control voltage Vcnt. A frequency divider 18 frequency-divides the output signal OUT of the VCO 16 so as to be synchronized with the frequency of a predetermined reference clock REF. A phase comparing unit 2 compares the phase of the output signal OUT 2 of the frequency divider 18 with the phase of the reference clock REF and outputs a voltage corresponding to the phase difference as a control voltage Vcnt to the VCO 16. A capacity regulating unit 30 regulates the capacity value of a regulation capacitor 50 so that the control voltage Vcnt is within a predetermined voltage range in a frequency-locked state during a predetermined calibration period. A loop control unit 40 varies loop characteristics of the phase synchronizing circuit 100 between the calibration period and a normal operation period. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a phase locked loop (hereinafter referred to as a PLL circuit) that oscillates in synchronization with a reference clock.

  PLL circuits are used in various electronic devices such as mobile phone terminals that use high-frequency signals. The PLL circuit stabilizes the frequency of the output signal to a value obtained by multiplying the frequency of the reference clock signal by a predetermined ratio based on the reference clock signal input from the outside. In general, the PLL circuit includes a voltage control oscillator (VCO), a frequency divider, a phase comparator, and a loop filter.

  The VCO oscillates at a frequency corresponding to the input control voltage. The frequency divider divides the output signal of the VCO. The phase comparator compares the phase of the output of the frequency divider with the reference clock signal and outputs a signal corresponding to the phase difference. The loop filter filters the output signal of the phase comparator and feeds it back to the VCO as a control voltage.

Due to manufacturing variations of elements constituting the VCO, the relationship between the oscillation frequency of the VCO and the control voltage varies depending on the individual. Calibration is performed to eliminate this individual difference. Patent Documents 1 and 2 describe related technologies. When calibration is performed in an operating state mounted on an electronic device, it needs to be performed in a short time.
Japanese Patent Laid-Open No. 11-234124 JP 2003-78410 A

  The present invention has been made in view of such circumstances, and a comprehensive object thereof is to provide a PLL circuit capable of executing calibration at high speed.

  According to one aspect of the present invention, a phase locked loop circuit oscillates at a frequency according to an input control voltage, and includes a voltage controlled oscillator including an adjustment capacitor for making the oscillation frequency for a certain control voltage variable. A frequency divider that divides the output signal to match the frequency of a predetermined reference clock, and the output signal of the divider and the phase of the reference clock are compared, and a voltage corresponding to the phase difference is used as a control voltage. A phase comparison unit that outputs to the controlled oscillator and a capacitance adjustment that adjusts the capacitance value of the adjustment capacitor so that the control voltage is included in a predetermined voltage range while the frequency is locked during a predetermined calibration period. And a loop control unit that changes the loop characteristics of the phase-locked loop during the calibration period and during the normal operation period.

  According to this aspect, in a state where the frequency is locked, the calibration can be executed so that the control voltage is included in the predetermined voltage range. By changing the loop characteristics during the calibration period, the time until the frequency lock is applied can be shortened, so that the calibration time can be shortened.

The loop control unit may set the loop band during the calibration period wider than the loop band during the normal operation period.
The phase comparison unit is configured to generate a phase difference signal corresponding to the phase difference between the output signal of the frequency divider and a reference clock having a predetermined frequency, and to charge or discharge current depending on the phase difference signal. A charge pump circuit to be generated and a loop filter including a capacitor charged or discharged by the charge pump circuit may be included. The loop control unit may set the loop band during the calibration period wider than the loop band during the normal operation period.

The loop control unit may set the loop gain during the calibration period higher than the loop gain during the normal operation period.
The phase comparison unit is configured to generate a phase difference signal corresponding to the phase difference between the output signal of the frequency divider and a reference clock having a predetermined frequency, and to charge or discharge current depending on the phase difference signal. A charge pump circuit to be generated and a loop filter including a capacitor charged or discharged by the charge pump circuit may be included. The loop control unit may set the charging current and discharging current during the calibration period to be larger than the charging current and discharging current during the normal operation period.

  The loop control unit may set the frequency of the reference clock during the calibration period to be higher than the frequency of the reference clock during the normal operation period.

  The capacity adjusting unit compares the control voltage with a first threshold voltage that defines an upper limit of a predetermined voltage range, and compares the control voltage with a lower threshold voltage that defines a lower limit of the predetermined voltage range. You may include the 2nd comparator and the decoder which adjusts a capacitance value based on the output signal of a 1st, 2nd comparator.

The adjustment capacitors have a capacitance value ratio of 1: 2:...: 2 ⁿ⁻¹ and are connected in parallel through switches n (n is an integer of 2 or more) first to nth. A capacitor may be included. The decoder may adjust the capacitance value of the adjustment capacitor in the range of 0 to 2 ⁿ −1 by turning on / off a switch provided for each capacitor. Further, in the initial state, the decoder sets the capacitance value of the adjustment capacitor to 2 ⁿ⁻¹ , and then increases the variable i one by one in order from 1, and the i-th time by the first and second comparators. The capacitance value of the adjustment capacitor is repeated by increasing the capacitance value of the adjustment capacitor by (2 ⁿ⁻ⁱ⁻¹ ) or decreasing it by (2 ⁿ⁻ⁱ⁻¹ ). May be set.
In this case, calibration can be completed by a maximum of (n + 1) comparisons, so that the calibration time can be shortened.

  According to the present invention, calibration can be executed at high speed.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A and the member B are connected” means that the member A and the member B are physically directly connected, or the member A and the member B are in an electrically connected state. It includes the case of being indirectly connected through another member that does not affect the above.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical connection. The case where it is indirectly connected through another member that does not affect the state is also included.

  FIG. 1 is a circuit diagram showing a configuration of a PLL circuit 100 according to the embodiment. For example, the PLL circuit 100 is mounted on a wireless communication device such as a mobile phone terminal. A radio communication device requires a high frequency signal of several hundred MHz to several GHz. The PLL circuit 100 according to the present embodiment can be suitably used for the purpose of generating such a high-frequency signal.

  Hereinafter, the configuration of the PLL circuit 100 will be described. The PLL circuit 100 includes a phase comparison unit 2, a VCO 16, a frequency divider 18, a capacity adjustment unit 30, and a loop control unit 40. A reference clock REF having a predetermined frequency is input to the PLL circuit 100. The PLL circuit 100 generates an output signal OUT having a frequency m times the reference clock REF.

  The VCO 16 oscillates at a frequency corresponding to the input control voltage Vcnt. The VCO 16 is configured such that the oscillation frequency fosc for a certain control voltage Vcnt is variable.

  The VCO 16 includes inductors L10 and L11, capacitors C10 and C11, variable capacitance diodes (varicaps) D10 and D11, transistors M10 and M11, and adjustment capacitors 50a and 50b.

  The variable-capacitance diodes D10 and D11 are connected in common to the cathode, and the control voltage Vcnt is input. Inductors L10 and L11 are provided between the anodes of the variable capacitance diodes D10 and D11 and the power supply line Vdd, respectively. Capacitors C10 and C11 are connected in parallel with inductors L10 and L11, respectively.

  The transistors M10 and M11 are N-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The source of the transistor M10 is grounded, and its drain is connected to the anode of the variable capacitance diode D10. Similarly, the source of the transistor M11 is grounded, and the drain thereof is connected to the anode of the variable capacitance diode D11. The gate of the transistor M10 is connected to the drain of the transistor M11, and the gate of the transistor M11 is connected to the drain of the transistor M10.

The adjustment capacitors 50a and 50b are provided to adjust the oscillation frequency fosc for a certain control voltage Vcnt.
The adjustment capacitors 50a and 50b are provided in parallel with the transistors M10 and M11, respectively.

  The oscillation frequency of the VCO 16 changes according to the product of the combined capacitance of the variable capacitance diodes D10 and D11, the capacitors C10 and C11 and the adjustment capacitors 50a and 50b and the inductances of the inductors L10 and L11. When the control voltage Vcnt changes, the capacitance values of the variable capacitance diodes D10 and D11 change, and the oscillation frequency fosc changes. Note that the configuration of the VCO 16 is not limited to that shown in FIG. 1, and VCOs having other configurations may be used. The VCO 16 may be configured to include a capacitance component that changes according to the control voltage Vcnt and a capacitance component that can be adjusted by external control regardless of the control voltage Vcnt.

  In the circuit of FIG. 1, since the adjustment capacitors 50a and 50b have the same configuration, only the adjustment capacitor 50b will be described. The adjustment capacitor 50b includes a plurality of n (= 4) first to fourth capacitors C1 to C4 and first to fourth switches SW1 to SW4 connected in series. The first to fourth capacitors C1 to C4 are connected in parallel according to the on / off states of the first to fourth switches SW1 to SW4.

  In the present embodiment, the capacitance values of the first to fourth capacitors C1 to C4 are set to 1: 2: 4: 8. That is, the capacitance value of each capacitor is set to a power of 2. When the unit capacitance is written as Cu, the combined capacitance of the adjustment capacitor 50 is 0 when all the switches SW1 to SW4 are off, and 15 × Cu when all the switches SW1 to SW4 are on. That is, the capacitance value can be controlled with 4 bits by turning on and off the switches SW1 to SW4. The switches of the adjustment capacitors 50a and 50b operate in the same manner in conjunction with each other.

  The frequency divider 18 divides the output signal OUT of the VCO 16 so as to match the frequency of a predetermined reference clock REF. The division ratio is m. The phase comparator 2 compares the divided output signal OUT2 output from the frequency divider 18 with the phase of the reference clock REF, and outputs a voltage corresponding to the phase difference to the VCO 16 as the control voltage Vcnt.

The phase comparison unit 2 includes a phase comparator 10, a charge pump circuit 12, and a loop filter 14.
The phase comparator 10 compares the phases of the reference clock REF and the divided output signal OUT2, and outputs an up signal or a down signal depending on which phase is advanced. The charge pump circuit 12 generates a charging current or a discharging current according to an up signal / down signal (also referred to as a phase difference signal) output from the phase comparator 10.

The loop filter 14 includes switches SW20 and SW21, capacitors C20 and C21, and a resistor R21. The switch SW20 and the capacitor C20 are connected in series between the output terminal of the charge pump circuit 12 and the ground terminal. Similarly, the switch SW21, the resistor R21, and the capacitor C21 are connected in series between the output terminal of the charge pump circuit 12 and the ground terminal.
The capacitors C20 and C21 function as capacitors that are charged and discharged by the charging current and discharging current generated by the charge pump circuit 12, and are constituent elements of the CR filter.

The cut-off frequency of the loop filter 14 changes according to the on / off states of the switches SW20 and SW21. The loop filter 14 feeds back the filtered control voltage Vcnt to the VCO 16.
By charging or discharging the capacitors C20 and C21, charges corresponding to the phase difference are stored in the capacitors, and a control voltage Vcnt corresponding to the phase difference is generated.

The capacitance adjusting unit 30 adjusts the capacitance values of the adjustment capacitors 50a and 50b so that the control voltage Vcnt is included in a predetermined voltage range in a state where the frequency is locked during a predetermined calibration period.
The capacity adjustment unit 30 includes a first comparator 20, a second comparator 22, a first latch circuit 24, a second latch circuit 26, and a decoder 28.

  The first comparator 20 compares the control voltage Vcnt with an upper threshold voltage VH that defines an upper limit of a predetermined voltage range. The second comparator 22 compares the control voltage Vcnt with a lower threshold voltage VL that defines the lower limit of a predetermined voltage range. The first latch circuit 24 and the second latch circuit 26 latch the output signals S1 and S2 of the first comparator 20 and the second comparator 22, respectively. The output signal S1 of the first comparator 20 is at a high level (H) when Vcnt> VH, and is at a low level (L) when Vcnt <VH. The output signal S2 of the second comparator 22 is at a high level when Vcnt> VL, and is at a low level when Vcnt <VL.

Three states are determined by the combination of the signals S1 and S2.
1. First state (S1 = S2 = L)
A state in which the control voltage Vcnt is out of the voltage range (Vcnt <VL) is shown.
2. Second state (S1 = S2 = H)
The control voltage Vcnt indicates a state (VH <Vcnt) that is outside the voltage range.
3. Third state (S1 = L, S2 = H)
A state in which the control voltage Vcnt is included in the voltage range (VL <Vcnt <VH) is shown.

  The decoder 28 adjusts the capacitance value of the adjustment capacitor 50 based on the latched output signals S 1 and S 2 of the first comparator 20 and the second comparator 22. Hereinafter, adjustment of the adjustment capacitor 50 will be described.

  The decoder 28 holds the on / off states of the switches SW1 to SW4 as 4-bit control data SWDATA [3: 0]. The MSB (Most Significant Bit) of the control data SWDATA is associated with ON / OFF of the fourth switch SW4, and the LSB (Least Significant Bit) is associated with ON / OFF of the first switch SW1. 1 corresponds to ON and 0 corresponds to OFF.

As a result, the capacitance value of the adjustment capacitor 50 is adjusted in the range of 0 × CU to 15 × CU (= CU × 2 ⁿ −1).

The decoder 28 increases or decreases the control data SWDATA according to the first state to the third state. That is, the decoder 28 can be composed of an addition / subtraction circuit.
When determining the first state, the decoder 28 decreases the value of the control data SWDATA, and when determining the second state, the decoder 28 increases the value of the control data SWDATA. The decoder 28 repeatedly increases and decreases the control data SWDATA until the decoder 28 is stabilized in the third state.

More specifically, the following operation may be performed.
In the initial state, the decoder 28 sets the control data SWDATA to a half value [1000], sets only the fourth switch SW4 (n = 4) to ON, and sets the capacitance values of the adjustment capacitors 50a and 50b to Set to 8 × CU (= 2 ⁿ⁻¹ × CU).
Thereafter, the variable i is incremented one by one in order from 1, and the capacitance values of the adjustment capacitors 50a and 50b according to the signals S1 and S2 which are the i-th comparison results by the first comparator 20 and the second comparator 22. Is increased or decreased by (2 ⁿ⁻ⁱ⁻¹ ) × CU.
In this embodiment, if it is determined that the first state as a result of i = 1, the control data SWDATA is set to 2 ⁿ⁻ⁱ⁻¹ (= 2 ⁴⁻¹⁻¹ ), that is, only [0100]. Decrease. Conversely, if it is determined that the second state, the control data SWDATA is increased by [0100]. If it is in the third state, the calibration is completed.

If it is determined that the first state is the result of the i = 2th comparison, the control data SWDATA is increased by 2 ⁿ⁻ⁱ⁻¹ (= 2 ⁴⁻²⁻¹ ), that is, [0010]. Conversely, if it is determined that the second state, the control data SWDATA is decreased by [0010].

If it is determined that the first state is the result of the i = 3rd comparison, the control data SWDATA is increased by 2 ⁿ⁻ⁱ⁻¹ (= 2 ^4-3-1 ), that is, [0001]. Conversely, if it is determined that the second state, the control data SWDATA is decreased by [0001].

Further, if necessary, the result of the i = 4th comparison is performed, and if it is determined to be in the first state, the control data SWDATA is set to 2 ⁿ⁻ⁱ⁻¹ (= 2 ^4-3-1 ), that is, [0001 ] Only. Conversely, if it is determined that the second state, the control data SWDATA is decreased by [0001].

  The above is the calibration operation by the capacity adjustment unit 30. In the third state, the value of the control data SWDATA is held, the switch states of the adjustment capacitors 50a and 50b are fixed, and the normal operation is performed.

  When the calibration is instructed to the PLL circuit 100, the loop control unit 40 changes the loop characteristic of the PLL circuit 100 from the loop characteristic during normal operation. In the present embodiment, the loop band during the calibration period is set wider than that during the normal operation period.

  In order to change the loop band, the loop control unit 40 controls on / off of the switches SW20 and SW21 of the loop filter 14. For example, during the calibration period, the switch SW20 is turned on and the SW21 is turned off, and the cutoff frequency of the loop filter 14 is increased. When the calibration period ends and the normal operation period starts, the switch SW21 is turned on to lower the cut-off frequency of the loop filter 14, thereby improving the loop stability. Thereby, phase jitter can be suppressed.

The operation of the PLL circuit 100 configured as described above will be described. FIG. 2 is a flowchart showing the operation of the PLL circuit 100 of FIG.
When calibration is instructed, the loop control unit 40 sets a wide loop band (S10). This shortens the time until the frequency locks. Subsequently, an initialization operation is executed (S12). Specifically, the control data SWDATA is set to [1000], and the variable i is set to 1.

  In this state, the PLL circuit 100 operates and the frequency is locked (S14). When the capacity adjustment unit 30 detects the third state (Y of S16), the state of the switches SW1 to SW4 is fixed, and the loop control unit 40 sets the loop band to be narrow (S18) and completes the calibration.

In step S16, if it is not the third state (N of S16), it is determined whether it is the first state. If it is in the first state (Y in S20), the control data SWDATA is increased by 24.sup. ^-i-1 . Subsequently, the variable i is incremented by 1 (S30), and the process returns to step S14.

In step S20, if it is not in the first state (N in S20), it is determined whether it is in the second state. If it is in the second state (Y in S24), the control data SWDATA is decreased by 24 ^-i-1 . Subsequently, the variable i is incremented by 1 (S30), and the process returns to step S14.

  By repeating the above operation, the capacitance values of the adjustment capacitors 50a and 50b are adjusted so that the control voltage Vcnt with the frequency locked is included in a predetermined voltage range.

  According to the PLL circuit 100 according to the present embodiment, by setting a wide loop band during the calibration period, the time until the frequency is locked can be shortened, and the calibration time can be shortened. Further, the control data SWDATA is increased / decreased in accordance with the comparison result between the control voltage Vcnt, the upper threshold voltage VH, and the lower threshold voltage VL, thereby controlling the switches SW1 to SW4, thereby simplifying the calibration process. Can be executed.

  Furthermore, according to the PLL circuit 100 according to the present embodiment, the number of comparisons until calibration is completed can be reduced to n + 1 times or less at maximum. If only the switch SW4 is turned on (SWDATA = [1000]) is the initial state and all the switches SW1 to SW4 are turned on (SWDATA = [1111]) is the final state, the control data SWDATA is set to 1. When increasing / decreasing step by step, it is necessary to repeat the same process eight times. In this embodiment, the calibration time can be reduced to ½ or less.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there. Hereinafter, such modifications will be described.

In the embodiment, the case where the loop band during the calibration period is set wide has been described. Instead of this, or together with this, the loop gain during the calibration period may be set higher than the loop gain during the normal operation period. As a method of setting the loop gain high, in the charge pump circuit 12, the charging current and discharging current during the calibration period may be set larger than the charging current and discharging current during the normal operation period.
As another method, the frequency of the reference clock signal REF may be set high during the calibration period. In this case, the frequency division ratio m of the frequency divider 18 is also set high accordingly.
According to this modification, since the loop gain is set high, the time until the frequency lock is applied in the calibration period can be shortened, so that the calibration can be speeded up.

  Although the case where the adjustment capacitors 50a and 50b are provided has been described in the embodiment, the present invention is not limited to this. For example, the variable capacitance diodes D1 and D2 may be segmented and the number of active segments may be switched by a switch. According to this modification, the capacitances of the adjustment capacitors 50a and 50b substantially change according to the control voltage Vcnt, so that the relationship between the oscillation frequency fosc and the control voltage Vcnt can be kept good.

  Although the present invention has been described based on the embodiments, the embodiments merely illustrate the principle and application of the present invention, and the embodiments are intended to include the idea of the present invention defined in the claims. Many modifications and changes in arrangement are possible within the range not leaving.

It is a circuit diagram which shows the structure of the PLL circuit which concerns on embodiment. 2 is a flowchart showing the operation of the PLL circuit of FIG.

Explanation of symbols

  100 PLL circuit, 2 phase comparator, 10 phase comparator, 12 charge pump circuit, 14 loop filter, 16 VCO, 18 frequency divider, 20 first comparator, 22 second comparator, 24 first latch circuit, 26 second Latch circuit, 28 decoder, 30 capacity adjustment unit, 40 loop control unit, 50 adjustment capacitor.

Claims (8)

A voltage controlled oscillator including an adjustment capacitor for oscillating at a frequency according to the input control voltage and making the oscillation frequency for a certain control voltage variable;
A frequency divider that divides the output signal of the voltage controlled oscillator to match the frequency of a predetermined reference clock;
A phase comparator for comparing the output signal of the frequency divider and the phase of the reference clock and outputting a voltage corresponding to the phase difference to the voltage controlled oscillator as the control voltage;
A capacitance adjusting unit that adjusts a capacitance value of the adjustment capacitor so that the control voltage is included in a predetermined voltage range in a state where the frequency is locked during a predetermined calibration period;
A loop control unit that changes the loop characteristics of the phase-locked loop circuit during the calibration period and during the normal operation period;
A phase locked loop circuit comprising: The loop control unit
The phase synchronization circuit according to claim 1, wherein a loop band during the calibration period is set wider than a loop band during a normal operation period. The phase comparison unit includes:
A phase comparator that generates a phase difference signal corresponding to a phase difference between the output signal of the frequency divider and a reference clock having a predetermined frequency;
A charge pump circuit that generates a charging current or a discharging current according to the phase difference signal;
A loop filter including a capacitor charged or discharged by the charge pump circuit;
Including
The phase synchronization circuit according to claim 2, wherein the loop control unit sets a loop band during the calibration period wider than a loop band during a normal operation period. The loop control unit
The phase synchronization circuit according to claim 1, wherein a loop gain during the calibration period is set higher than a loop gain during a normal operation period. The phase comparison unit includes:
A phase comparator that generates a phase difference signal corresponding to a phase difference between the output signal of the frequency divider and a reference clock having a predetermined frequency;
A charge pump circuit that generates a charging current or a discharging current according to the phase difference signal;
A loop filter including a capacitor charged or discharged by the charge pump circuit;
Including
5. The phase locked loop circuit according to claim 4, wherein the loop control unit sets a charging current and a discharging current during the calibration period to be larger than a charging current and a discharging current during a normal operation period. The loop control unit
The phase synchronization circuit according to claim 1, wherein a frequency of the reference clock during the calibration period is set higher than a frequency of the reference clock during a normal operation period. The capacity adjuster is
A first comparator for comparing the control voltage with an upper threshold voltage defining an upper limit of the predetermined voltage range;
A second comparator for comparing the control voltage with a lower threshold voltage defining a lower limit of the predetermined voltage range;
A decoder for adjusting a capacitance value of the adjustment capacitor based on output signals of the first and second comparators;
The phase synchronization circuit according to claim 1, comprising: The adjustment capacitor has a capacitance ratio of 1: 2:...: 2 ⁿ⁻¹ and is connected in parallel through switches n (n is an integer of 2 or more) first to first. n capacitors,
The decoder adjusts the capacitance value of the adjustment capacitor in a range of 0 to 2 ⁿ −1 by turning on / off a switch provided for each capacitor, and
In the initial state, the capacitance value of the adjustment capacitor is set to 2 ⁿ⁻¹ ,
Thereafter, the variable i is incremented one by one in order from 1, and the capacitance value of the adjustment capacitor is increased by (2 ⁿ⁻ⁱ⁻¹ ) according to the i-th comparison result by the first and second comparators. The phase synchronization circuit according to claim 7, wherein a capacitance value of the adjustment capacitor is set by repeating an operation of decreasing or decreasing.

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