JP5104851B2 - Voltage controlled oscillator and synthesizer circuit - Google Patents

Description

  The present invention relates to a voltage controlled oscillator and a synthesizer circuit.

  2. Description of the Related Art Recently, in a wireless data communication terminal, a synthesizer circuit that generates a local clock necessary for signal transmission and reception and a voltage-controlled oscillator that is one of its main constituent circuits are required to have low noise characteristics and wideband characteristics. In order to realize the low noise characteristics of the voltage controlled oscillator, it is necessary to reduce the frequency change per unit voltage of the control voltage. On the other hand, in order to realize the broadband characteristics of the voltage controlled oscillator, it is necessary to widen the variable range of the frequency. Therefore, in applications where both low noise and wideband characteristics are required, a configuration in which a capacitance assembly composed of a plurality of capacitors having a fixed capacitance value and a variable capacitance element are used. The capacitance aggregate is for coarse frequency adjustment, and the variable capacitance element is for fine frequency adjustment.

  FIG. 18 is a diagram showing a configuration of a conventional voltage-controlled oscillator corresponding to a wide band. As shown in FIG. 18, a conventional voltage-controlled oscillator (hereinafter simply referred to as a voltage-controlled oscillator) 1 for a wide band includes a plurality of capacitors 2, 3, 4, and 5 having fixed capacitance values, and a plurality of switches 6, 7, 8, 9, varactor 10, inductor 11, amplifier 12, and capacitance switching unit 13. The capacitors 2, 3, 4, 5 and the varactor 10 are connected in parallel to the inductor 11 and constitute an LC resonance circuit together with the inductor 11.

  The switches 6, 7, 8, and 9 are connected in series to the capacitors 2, 3, 4, and 5, respectively, and control connection and disconnection of the capacitors 2, 3, 4, and 5 to the LC resonance circuit. . The capacity switching unit 13 controls opening and closing of the switches 6, 7, 8, and 9 by switching signals CT0, CT1, CT2, and CT3. The capacity of the varactor 10 changes according to a fine adjustment signal Vcntr1 input from the outside. The fine adjustment signal Vcntrl continuously changes as a voltage signal for adjusting the capacitance value of the varactor 10. The capacitors 2, 3, 4, and 5 are weighted by, for example, doubling their size in this order.

  FIG. 19 is a diagram showing a change in capacitance value in the voltage controlled oscillator shown in FIG. As shown in FIG. 19, the switching signals CT0, CT1, CT2, and CT3 are binary signals that switch between the ground potential (low level) and the power supply potential (high level) at each timing. When the switching signals CT0, CT1, CT2, and CT3 are at a low level, the corresponding switch is opened, and the capacitor connected to the switch is disconnected from the LC resonance circuit. On the other hand, when the switching signals CT0, CT1, CT2, and CT3 are at a high level, the corresponding switch is closed, and the capacitor connected to the switch is connected to the LC resonance circuit.

  Note that, in each waveform indicating the capacitance by the switching signals CT0, CT1, CT2, and CT3 in FIG. 19, the height of the step represents the capacitance value, and the higher the step, the larger the capacitance value. A waveform indicating the total capacity is obtained by adding the waveforms indicating the capacities of the switching signals CT0, CT1, CT2, and CT3. As described above, the voltage-controlled oscillator 1 having the configuration shown in FIG. 18 has a plurality of voltage-frequency characteristic curves that are discretely switched by the capacitance switching unit 13 separately from the fine adjustment of the frequency by the fine adjustment signal Vcntrl. FIG. 20 shows a voltage-frequency characteristic curve. In this way, both phase noise (curve slope) and wideband (frequency range where the curve exists) are achieved simultaneously. A synthesizer circuit using a voltage-controlled oscillator having such a configuration is disclosed in Patent Document 1.

Japanese Patent Laying-Open No. 2005-318509 (FIG. 1)

  However, the conventional voltage controlled oscillator described above has the following problems. FIG. 21 is an enlarged view of the change in the capacitance value at time T in the capacitance value waveform shown in FIG. As shown in FIG. 21, in practice, the switching signals CT0, CT1, CT2, and CT3 are shifted in time with respect to each other, and the capacitors are connected or disconnected at the time of the level transition of the switching signals CT0, CT1, CT2, and CT3. Since the timing is different and the switching level (threshold) of each switch is different, there is a difference in the timing of connection or disconnection of each capacitor for coarse adjustment, and the total capacitance may instantaneously change larger than the design value. is there.

  In FIG. 20, when switching from one voltage-frequency characteristic curve 16 to another voltage-frequency characteristic curve 17 by switching the coarse adjustment capacity, the voltage-controlled oscillator oscillates at the same frequency before and after that. As indicated by the arrow 18, it is necessary to change the potential of the fine adjustment signal Vcntrl from V2 to V1 instantaneously. As shown in FIG. 21, when the total capacity changes excessively, the change of the fine adjustment signal Vcntrl at the time of transition of the voltage-frequency characteristic curve becomes large. If the fine adjustment signal Vcntrl changes faster than the time constant of the PLL (Phase Locked Loop) of the synthesizer circuit, the PLL cannot follow, and thus the phase synchronization of the synthesizer circuit is lost. As a result, the service stops.

  As means for avoiding such inconvenience, a configuration is known in which the frequency is adjusted over a wide range with a single varactor without using a plurality of voltage-frequency characteristic curves by switching a plurality of capacitors having a fixed capacitance value. However, in this case, there is a problem in that the noise frequency deteriorates and the required characteristics cannot be satisfied because the output frequency changes more greatly due to the noise signal appearing in the fine adjustment signal Vcntrl.

  The present invention has been made in view of the above, and an object of the present invention is to provide a voltage-controlled oscillator having a plurality of voltage-frequency characteristic curves and having a capacity that gradually changes during transition between the voltage-frequency characteristic curves. And It is another object of the present invention to provide a synthesizer circuit in which phase synchronization is not lost during transition between voltage-frequency characteristic curves of a voltage-controlled oscillator having a plurality of voltage-frequency characteristic curves.

  In order to solve the above-described problems and achieve the object, the present invention provides a voltage-controlled oscillator that adjusts an oscillation frequency by changing a capacitance value with a voltage signal. A capacity assembly, capacity switching means and control voltage generation means are provided. The capacitance value of the variable capacitance element changes according to a fine adjustment signal whose potential changes continuously. The capacitive assembly is composed of one or two or more capacitive elements. The capacitance switching means outputs a switching signal for controlling the capacitive element of the capacitive assembly. The control voltage generating unit adjusts the time constant of the potential change of the switching signal input from the capacitance switching unit, and blunts the waveform of the switching signal. The capacitive element of the capacitive assembly is controlled by the switching signal having a dull waveform.

  The capacitive element of the capacitive assembly may be one or more variable capacitive elements. In this case, the capacitance value of the variable capacitance element is changed with the time constant of the switching signal having a dull waveform. In addition, the capacitive element of the capacitive assembly may include a capacitive element having one or more fixed capacitance values and a switch that controls connection and disconnection of the capacitive element to the resonance circuit. In this case, an RC filter is connected to the signal line of the switching signal, and the time constant of opening and closing of the switch is adjusted by blunting the waveform of the switching signal with this RC filter.

  According to the present invention, when the waveform of the switching signal is dull, the capacitance value of the resonance circuit changes slowly when the coarse adjustment capacitive element is switched. In particular, when the coarse adjustment capacitive element is a variable capacitive element, the capacitance value of the variable capacitive element gradually changes with the time constant of the switching signal having a dull waveform. Further, when the coarse adjustment capacitive element is a capacitive element having a fixed capacitance value, the capacitance of the resonant circuit is controlled by controlling connection and disconnection of the capacitive element to and from the resonant circuit by a switching signal having a dull waveform. The value changes slowly.

  The voltage-controlled oscillator according to the present invention has a plurality of voltage-frequency characteristic curves, and has an effect that the capacitance is gradually changed at the time of transition between the voltage-frequency characteristic curves. Further, the synthesizer circuit according to the present invention has an effect that phase synchronization is not lost at the time of transition between voltage-frequency characteristic curves of a voltage controlled oscillator having a plurality of voltage-frequency characteristic curves.

It is a figure which shows the structure of the voltage controlled oscillator concerning Example 1 of this invention. It is a figure which shows the structure of the control voltage generation part of the voltage controlled oscillator shown in FIG. It is a figure which shows the change of the output voltage of the control voltage generation part shown in FIG. It is a figure which shows the change of the capacitance value of the voltage controlled oscillator shown in FIG. It is a figure which shows the structure of the control voltage generation part of the voltage controlled oscillator concerning Example 2 of this invention. It is a figure which shows the change of the output voltage of the control voltage generation part shown in FIG. FIG. 6 is a diagram showing a configuration of a comparison / addition / subtraction circuit of the control voltage generator shown in FIG. 5. It is a figure which shows the operation | movement of the counter of the comparison / addition / subtraction circuit shown in FIG. It is a figure which shows the structure of the comparator of the comparison / addition / subtraction circuit shown in FIG. FIG. 10 is a diagram illustrating an operation of the comparator illustrated in FIG. 9. It is a figure which shows the operation timing of the comparison / addition / subtraction circuit shown in FIG. It is a figure which shows the structure of the control voltage generation part of the voltage controlled oscillator concerning Example 3 of this invention. It is a figure which shows operation | movement of the counter of the control voltage generation part shown in FIG. It is a figure which shows the structure of the voltage controlled oscillator concerning Example 4 of this invention. It is a figure which shows the structure of the control voltage generation part of the voltage controlled oscillator shown in FIG. FIG. 15 is a diagram illustrating another configuration of a control voltage generation unit of the voltage controlled oscillator illustrated in FIG. 14. It is a figure which shows the structure of the synthesizer circuit concerning Example 5 of this invention. It is a figure which shows the structure of the conventional voltage controlled oscillator. It is a figure which shows the change of the capacitance value in the voltage controlled oscillator shown in FIG. It is a figure which shows the voltage-frequency characteristic curve of a voltage controlled oscillator. It is a figure which expands and shows the change of the capacitance value in the time T of FIG.

  Embodiments of a voltage controlled oscillator and a synthesizer circuit according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. In general, the voltage controlled oscillator has a differential configuration including a pair of circuits having the same configuration. Here, the configuration on one side will be described, but the configuration on the other side is the same.

  FIG. 1 is a diagram illustrating the configuration of the voltage controlled oscillator according to the first embodiment of the present invention. As shown in FIG. 1, there are a plurality of voltage-controlled oscillators 21, and although not particularly limited, for example, a capacity aggregate for frequency coarse adjustment comprising four varactors (variable capacitance elements, varicaps) 22, 23, 24, 25. , A varactor 30 for fine frequency adjustment, an inductor 31, an amplifier 32, a capacitance switching unit 33, and a control voltage generating unit 34 are provided.

  The coarse adjustment varactors 22, 23, 24, 25 and the fine adjustment varactor 30 are connected in parallel to the inductor 31, and constitute an LC resonance circuit together with the inductor 31. The capacity switching unit 33 outputs switching signals CT0, CT1, CT2, and CT3 for controlling the coarse adjustment varactors 22, 23, 24, and 25. Each of the switching signals CT0, CT1, CT2, and CT3 is a signal that takes a binary potential of a high level and a low level. The control voltage generator 34 is provided for each of the coarse adjustment varactors 22, 23, 24, and 25.

  Each control voltage generator 34 adjusts the time constant of the potential change of each switching signal CT0, CT1, CT2, CT3 input from the capacitance switching unit 13, and blunts the waveform of each switching signal CT0, CT1, CT2, CT3. . The capacitances of the coarse adjustment varactors 22, 23, 24, and 25 vary with the time constants of the switching signals CT0 ', CT1', CT2 ', and CT3' having a dull waveform. The capacity of the fine adjustment varactor 30 varies depending on the fine adjustment signal Vcntr1 input from the outside. The fine adjustment signal Vcntrl continuously changes as a voltage signal for adjusting the capacitance value of the fine adjustment varactor 30. The coarse adjustment varactors 22, 23, 24, and 25 are weighted by, for example, doubling their size in this order.

  FIG. 2 is a diagram showing a configuration of a control voltage generation unit of the voltage controlled oscillator shown in FIG. As shown in FIG. 2, the control voltage generator 34 includes an inverter circuit 41, a current source (PMOS transistor) 42 connected to a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) of the inverter circuit 41, and an inverter circuit 41. Current source (NMOS transistor) 43 connected to the N channel MOS transistor (hereinafter referred to as NMOS transistor) and a capacitor 44 for adjusting the time constant. The time constant adjusting capacitor 44 is connected between the output terminal (OUT) of the inverter circuit 41 and the ground point.

  The switching signal (CT0, CT1, CT2, CT3) is input from the capacitance switching unit 33 to the input terminal (IN) of the inverter circuit 41. When the switching signals (CT0, CT1, CT2, CT3) are switched from the high level to the low level, the NMOS transistor and the PMOS transistor of the inverter circuit 41 are switched to the off state and the on state, respectively. As a result, the time constant adjusting capacitor 44 is charged by the current Ib flowing from the current source 42. Therefore, switching signals (CT0 ', CT1', CT2 ', CT3') having a dull waveform whose voltage gradually rises due to the charging are output from the output terminal (OUT) of the inverter circuit 41.

  On the other hand, when the switching signals (CT0, CT1, CT2, CT3) are switched from the low level to the high level, the PMOS transistor and the NMOS transistor of the inverter circuit 41 are switched to the off state and the on state, respectively. As a result, the electric charge charged in the time constant adjusting capacitor 44 becomes the current Ib and flows through the current source 43 and is discharged. Accordingly, switching signals (CT0 ', CT1', CT2 ', CT3') having a dull waveform whose voltage gradually decreases due to the discharge are output from the output terminal (OUT) of the inverter circuit 41.

  FIG. 3 is a diagram showing a change in the output voltage of the control voltage generator shown in FIG. FIG. 3 shows a state where the output signal of the control voltage generator 34 transitions from a high level to a low level. As shown in FIG. 3, the fall time Tf of the switching signals (CT0 ′, CT1 ′, CT2 ′, CT3 ′) output from the control voltage generator 34 becomes longer, and the voltage gradually decreases. The state of transition from the low level to the high level is a line obtained by inverting the left and right sides of the broken line in the center portion of FIG.

The rise time Tr at this time is the same as the fall time Tf if the current Ib flowing from the current sources 42 and 43 is the same. The rise time Tr (fall time Tf) is given by the following equation.
Tr (= Tf) = C0 × VDD / Ib

  The capacitance value C0 of the time constant adjusting capacitor 44, the power supply potential VDD, and the current amount Ib flowing by the current sources 42 and 43 are selected so that a desired rise time Tr (fall time Tf) is obtained. The amount of current Ib flowing through the current sources 42 and 43 is controlled by the bias voltage.

  FIG. 4 is a diagram showing changes in the capacitance value of the voltage controlled oscillator shown in FIG. As shown in FIG. 4, the rising and falling edges of the switching signals CT0 ', CT1', CT2 ', CT3' for controlling the capacitance values of the coarse adjustment varactors 22, 23, 24, 25 become gentle. Therefore, even if the switching signals CT0 ′, CT1 ′, CT2 ′, and CT3 ′ are shifted in time, the total capacity obtained by adding the capacity values of the coarse adjustment varactors 22, 23, 24, and 25 changes sharply. It changes smoothly without waking up.

  FIG. 5 is a diagram illustrating the configuration of the control voltage generation unit of the voltage controlled oscillator according to the second embodiment of the present invention. In the second embodiment, the overall configuration of the voltage controlled oscillator is the same as that of the first embodiment, but the configuration of the control voltage generator is different from that of the first embodiment. As shown in FIG. 5, the control voltage generator 34 of the second embodiment includes a digital-analog converter circuit 51 and a comparison / addition / subtraction circuit 52.

  A switching signal (CT0, CT1, CT2, CT3) is input from the capacitance switching unit 33 to one input terminal (IN) of the comparison / addition / subtraction circuit 52. The output signal of the digital / analog conversion circuit 51 is input to the other input terminal of the comparison / addition / subtraction circuit 52. The comparison / addition / subtraction circuit 52 compares the two input signals and passes a digital code corresponding to the sign of the difference to the digital / analog conversion circuit 51. The timing for performing the comparison and the output of the digital code is synchronized with the rising edge for each clock of the clock signal CLK input to the comparison / addition / subtraction circuit 52 from the outside. The frequency of the clock signal CLK is a frequency according to a desired time constant.

  The digital-analog conversion circuit 51 outputs a potential of three or more values from its output terminal (OUT) in accordance with the digital code passed from the comparison / addition / subtraction circuit 52. This output potential is output to the coarse adjustment varactors 22, 23, 24, 25 as switching signals (CT 0 ′, CT 1 ′, CT 2 ′, CT 3 ′) having a dull waveform and fed back to the comparison / addition / subtraction circuit 52. The Thereby, the comparison / addition / subtraction circuit 52 converts the digital code so that the output potential of the digital-analog conversion circuit 51 gradually approaches the potential of the switching signals (CT0, CT1, CT2, CT3) input from the capacitance switching unit 33. Output.

  FIG. 6 is a diagram showing a change in the output voltage of the control voltage generator shown in FIG. As shown in FIG. 6, when the switching signal (CT0, CT1, CT2, CT3) input from the capacitance switching unit 33 to the comparison / addition / subtraction circuit 52 transits from high level to low level at a certain time, the digital-analog conversion circuit 51 In the output terminal (OUT), a signal that gradually changes from a high level to a low level appears in an output step determined by the multi-value number of the digital-analog conversion circuit 51 every clock cycle. This signal is a switching signal (CT0 ', CT1', CT2 ', CT3') having a dull waveform.

  The comparison / addition / subtraction circuit 52 includes switching signals (CT0, CT1, CT2, CT3) input from the capacitance switching unit 33 and switching signals (CT0 ′, CT1 ′, CT2 ′, CT3 ′) output from the digital-analog conversion circuit 51. ), The digital code is not changed even if the clock signal CLK is input. Therefore, the output potential of the digital-analog conversion circuit 51 is fixed at a high level or a low level.

  FIG. 7 is a diagram showing the configuration of the comparison / addition / subtraction circuit. As shown in FIG. 7, the comparison / addition / subtraction circuit 52 includes two comparators 61 and 62, a counter 63 capable of switching up / down, two operational amplifiers 64 and 65, two inverters 66 and 67, Two NAND gates 68 and 69, two AND gates 70 and 71, and, for example, a series connection body of seven resistance elements (hereinafter referred to as a resistance series connection body) for dividing the power supply voltage (power supply potential VDD-ground potential GND). 72).

  In the first operational amplifier 64, the switching signal (CT0, CT1, CT2, CT3) input from the capacitance switching unit 33 is input to the non-inverting input terminal, and the inverting input terminal of the digital-analog conversion circuit 51 is input. Output signal is input. In the second operational amplifier 65, the input signal is opposite to that of the first operational amplifier 64. The first comparator 61 compares the output potential of the digital-analog conversion circuit 51 with the power supply potential VDD and its potential 6/7. The first NAND gate 68 performs a NAND operation on the output signal BU of the first comparator 61 and the switching signals (CT0, CT1, CT2, CT3) input from the capacitance switching unit 33.

  The first AND gate 70 is the logic of the output signal AU of the first operational amplifier 64, the switching signals (CT0, CT1, CT2, CT3) input from the capacitance switching unit 33, and the output signal CU of the first NAND gate 68. A product operation is performed, and a signal UP (hereinafter referred to as a count up signal) UP that causes the counter 63 to perform a count up operation is output. On the other hand, the second comparator 62 compares the output potential of the digital-analog conversion circuit 51 with the potential 1/7 of the power supply potential VDD and the ground potential GND. The second NAND gate 69 is a negative logic of the signal obtained by inverting the output signal BD of the second comparator 62 and the switching signals (CT0, CT1, CT2, CT3) input from the capacitance switching unit 33 by the second inverter 67. Perform product operation.

  The second AND gate 71 includes an output signal AD of the second operational amplifier 65, a signal obtained by inverting the switching signals (CT 0, CT 1, CT 2, CT 3) input from the capacitance switching unit 33 by the first inverter 66, 2 performs an AND operation on the output signal CD of the NAND gate 69 and outputs a signal (hereinafter referred to as a countdown signal) DOWN for causing the counter 63 to perform a countdown operation. The counter 63 increments or decrements every CLK input in response to the input of the count up signal UP or the count down signal DOWN. For example, the counter 63 outputs a 3-bit digital code QD.

  FIG. 8 is a diagram showing the operation of the counter of the comparison / addition / subtraction circuit shown in FIG. As shown in FIG. 8, when the count-up signal UP is at a high level, the value of the digital code QD is incremented, and when the count-down signal DOWN is at a high level, the value of the digital code QD is decremented. When both the count-up signal UP and the count-down signal DOWN are at a low level, the value of the digital code QD does not change even if there is a CLK input.

  FIG. 9 is a diagram showing a configuration of a comparator of the comparison / addition / subtraction circuit shown in FIG. Since the first comparator 61 and the second comparator 62 have the same configuration, the configuration of the first comparator 61 will be described here. As shown in FIG. 9, the first comparator 61 includes two operational amplifiers 76 and 77 and an AND gate 78. In the third operational amplifier 76, the power supply potential VDD is applied to the non-inverting input terminal, and the output signal of the digital-analog conversion circuit 51 is input to the inverting input terminal. In the fourth operational amplifier 77, a 6/7 potential of the power supply potential VDD is applied to the inverting input terminal, and the output signal of the digital-analog conversion circuit 51 is input to the non-inverting input terminal.

  The third AND gate 78 performs an AND operation on the output signal XH of the third operational amplifier 76 and the output signal XL of the fourth operational amplifier 77. The output signal WC of the third AND gate 78 becomes the output signal BU of the first comparator 61 described above. When the comparator shown in FIG. 9 is the second comparator 62, a potential 1/7 of the power supply potential VDD is applied to the non-inverting input terminal of the third operational amplifier 76 and the fourth operational amplifier 77 is inverted. The ground potential GND is applied to the input terminal, and the output signal WC becomes the output signal BD of the second comparator 62.

  FIG. 10 is a diagram illustrating the operation of the comparator shown in FIG. As shown in FIG. 10, when the output potential (IN in the table) of the digital-analog conversion circuit 51 is higher than the potential (RH in the table) of the non-inverting input terminal of the third operational amplifier 76, the output of the fourth operational amplifier 77. The potential of the signal XL and the potential of the output signal XH of the third operational amplifier 76 become high level (H) and low level (L), respectively, and the potential of the output signal WC becomes low level. In addition, when the output potential (IN in the table) of the digital-analog conversion circuit 51 is lower than the potential (RL in the table) of the inverting input terminal of the fourth operational amplifier 77, the potential of the output signal XL and the potential of the output signal XH. Become low level and high level, respectively, and the potential of the output signal WC becomes low level. On the other hand, the output potential (IN in the table) of the digital-analog conversion circuit 51 is the potential of the inverting input terminal of the fourth operational amplifier 77 (RL in the table) and the potential of the non-inverting input terminal of the third operational amplifier 76 (in the table). RH), the potential of the output signal XL and the potential of the output signal XH are both high, and the potential of the output signal WC is high.

  FIG. 11 is a diagram showing the operation timing of the comparison / addition / subtraction circuit shown in FIG. In FIG. 11, during the period indicated by t1, the output potential of the digital-analog converter circuit 51 is between 1/7 of the ground potential GND and the power supply potential VDD, and the switching signal (CT0, This is when CT1, CT2, CT3) are at a low level. The state immediately after the switching signals (CT0, CT1, CT2, CT3) are switched to the high level from that state is a period indicated by t2. Increment of the value of the digital code QD starts in synchronization with the rising edge of the clock signal CLK immediately after the switching signals (CT0, CT1, CT2, CT3) are switched.

  The subsequent period indicated by t3 is a stage in which the increment of the value of the digital code QD is continued in synchronization with the rising edge of the subsequent clock signal CLK, and the output potential of the digital-analog conversion circuit 51 is gradually increased. During the period indicated by t4, the output potential of the digital-analog conversion circuit 51 rises to a potential between 6/7 of the power supply potential VDD and the power supply potential VDD, and is equal to the high level of the switching signals (CT0, CT1, CT2, CT3). And it is in a stable state. A state immediately after the switching signals (CT0, CT1, CT2, CT3) are switched to a low level from that state is a period indicated by t5.

  Decrementing the value of the digital code QD starts in synchronization with the rising edge of the clock signal CLK immediately after the switching signals (CT0, CT1, CT2, CT3) are switched. The subsequent period indicated by t6 is a stage in which the decrement of the value of the digital code QD is continued in synchronization with the rising edge of the subsequent clock signal CLK and the output potential of the digital-analog conversion circuit 51 is gradually lowered. Then, when the output potential of the digital-analog conversion circuit 51 drops to between 1/7 of the ground potential GND and the power supply potential VDD, it becomes stable in accordance with the low level of the switching signals (CT0, CT1, CT2, CT3). It becomes a state (period: t1).

  FIG. 12 is a diagram illustrating the configuration of the control voltage generator of the voltage controlled oscillator according to the third embodiment of the present invention. In the third embodiment, the overall configuration of the voltage controlled oscillator is the same as that of the first embodiment, but the configuration of the control voltage generator is different from that of the first embodiment. As shown in FIG. 12, the control voltage generator 34 according to the third embodiment includes a self-state determination counter 56 and a digital analog conversion circuit 57 with a CLK trigger.

  The switching signal (CT0, CT1, CT2, CT3) is input from the capacitance switching unit 33 to the input terminal (IN) of the self-state determination counter 56. A clock signal CLK having a frequency corresponding to a desired time constant is externally input to the CLK terminal of the self-state determination counter 56. The own state determination counter 56 performs an increment operation or a decrement operation in synchronization with, for example, the rising edge of the clock signal CLK. The own state determination counter 56 switches between the increment operation and the decrement operation based on the switching signal (CT0, CT1, CT2, CT3) and its own state. Then, the self state determination counter 56 outputs the count value as a digital code.

  FIG. 13 is a diagram showing the operation of the self-state determination counter of the control voltage generation unit shown in FIG. As shown in FIG. 13, the operation of the self-state determination counter 56 is divided into the following four, for example. (1) When the values of all bits of the counter are 1, that is, the digital code Q is “111... 1”, if the potential of the switching signal (CT0, CT1, CT2, CT3) is high level (H) The current digital code value Q (“111... 1”) is held. (2) If the value Q of the digital code is not “111... 1” and the potential of the switching signal (CT0, CT1, CT2, CT3) is high level (H), the counter is incremented and the digital code value The value is updated to [Q + 1].

  (3) When the values of all the bits of the counter are not 0, that is, the value Q of the digital code is not “000... 0”, the potential of the switching signal (CT0, CT1, CT2, CT3) is low level (L). If there is, the counter is decremented and the value of the digital code is updated to [Q-1]. (4) When the digital code Q is “000... 0” and the potential of the switching signal (CT0, CT1, CT2, CT3) is low level (L), the current digital code value Q (“ 000... 0 ”).

  The CLK trigger digital-to-analog conversion circuit 57 acquires a digital code from the self-state determination counter 56 with a clock signal CLK having a frequency corresponding to a desired time constant input from the outside as a trigger. The CLK trigger digital-to-analog conversion circuit 57 holds the acquired digital code until the next digital code acquisition timing, and at least three potentials from the output terminal (OUT) according to the held digital code. Is output. This output potential is output to the coarse adjustment varactors 22, 23, 24, 25 as switching signals (CT 0 ′, CT 1 ′, CT 2 ′, CT 3 ′) having a dull waveform.

  The clock signal CLK for determining the operation timing of the self-state determination counter 56 and the CLK trigger digital-analog conversion circuit 57, the input terminal (IN) of the self-state determination counter 56, and the output terminal (OUT) of the CLK-trigger digital analog conversion circuit 57 The signal appearing at is exactly the same as in FIG. That is, at the output terminal (OUT) of the CLK-triggered digital / analog conversion circuit 57, as in the switching signal (CT0 ′, CT1 ′, CT2 ′, CT3 ′) having a dull waveform, one clock cycle as in the second embodiment. A gradually changing signal appears. In the third embodiment, since an analog circuit such as a comparator (comparator) is not necessary, the control voltage generator 34 or the voltage controlled oscillator 21 including the control voltage generator 34 is suitable for being realized by a digital circuit.

  FIG. 14 is a diagram illustrating a configuration of the voltage controlled oscillator according to the fourth embodiment of the present invention. The voltage-controlled oscillator 81 according to the fourth embodiment is different from the first embodiment in that the coarse frequency adjustment capacitance assembly includes a plurality of capacitors 82, 83, 84, 85 having fixed capacitance values, and capacitors 82, 83, 84, 85, and switches 86, 87, 88, 89 for controlling connection and disconnection to the resonance circuit. Further, each control voltage generator 34 blunts the waveforms of the switching signals CT0, CT1, CT2, CT3 input from the capacitance switching unit 33, and the switching signals CT0 ′, CT1 ′, CT2 ′, CT3 ′ having blunt waveforms. Is to control the opening and closing of the switches 86, 87, 88, 89.

  FIG. 15 is a diagram showing a configuration of a control voltage generation unit of the voltage controlled oscillator shown in FIG. As shown in FIG. 15, the control voltage generator 34 includes an input terminal (IN) to which the switching signals (CT0, CT1, CT2, CT3) are input from the capacitance switching unit 33, and a switching signal (CT0 ′, An RC filter composed of a resistor element and a capacitor element is connected to a signal line between output terminals (OUT) for outputting CT1 ′, CT2 ′, CT3 ′). The resistance element of the RC filter is constituted by, for example, a MOS transistor 91 excellent in integration.

  The capacitive element of the RC filter is composed of a plurality of capacitors 92 and 93. Each of the capacitors 92 and 93 is connected in parallel to the signal line of the switching signal via MOS transistors 94 and 95 serving as switches. In the fourth embodiment, a time constant setting unit 96 for controlling on / off of the MOS transistors 94 and 95 is provided. A desired time constant can be obtained by controlling the number of capacitors 92 and 93 connected to the signal line of the switching signal by the time constant setting unit 96. Note that the number of capacitors of the RC filter may be three or more.

  FIG. 16 is a diagram showing another configuration of the control voltage generator of the voltage controlled oscillator shown in FIG. In the control voltage generation unit 34 shown in FIG. 16, a plurality of MOS transistors 91 and 97 serving as resistance elements of the RC filter are connected in parallel to the signal line of the switching signal. In this example, the time constant setting unit 96 controls on / off of the MOS transistors 91 and 97, and controls the number of the MOS transistors 91 and 97 connected to the signal line of the switching signal, whereby a desired time constant is set. Is obtained. Note that the number of MOS transistors serving as resistance elements of the RC filter may be three or more. A plurality of RC filter capacitance elements and resistance elements may be provided, and a desired time constant may be obtained by controlling connection and disconnection thereof.

  FIG. 17 is a diagram illustrating the configuration of the synthesizer circuit according to the fifth embodiment of the present invention. As illustrated in FIG. 17, the synthesizer circuit 101 includes the voltage controlled oscillator 21, the frequency dividing circuit 102, the phase comparison circuit 103, the charge pump circuit 104, a filter 105 such as a loop filter, and a control circuit 106 according to the first embodiment. . The output signal (output CLK) of the voltage controlled oscillator 21 is frequency-divided to a desired frequency by the frequency dividing circuit 102. The output signal of the frequency dividing circuit 102 is compared with the phase of the reference clock signal (reference CLK) input from the outside in the phase comparison circuit 103.

  The phase comparison circuit 103 outputs a voltage signal corresponding to the phase difference. The output voltage of the phase comparison circuit 103 is converted into a desired voltage by the charge pump circuit 104. The output signal of the charge pump circuit 104 is smoothed by the filter 105 and passed to the voltage controlled oscillator 21 as the fine adjustment signal Vcntrl. Further, the potential of the fine adjustment signal Vcntrl is monitored by the control circuit 106. The control circuit 106 monitors the potential of the fine adjustment signal Vcntrl with a comparator or the like. When the control circuit 106 is out of the range set at the time of design as an adjustment value, the control circuit 106 sends the switching signals CT0, CT1, CT1 to the capacitance switching unit 33 of the voltage controlled oscillator 21. It is composed of a logic circuit that increments or decrements a value for switching the potentials of CT2 and CT3.

  For example, the control circuit 106 increments when the fine adjustment signal Vcntrl is lower than a potential 0.2V higher than the ground potential GND, and when the fine adjustment signal Vcntrl is higher than a potential 0.2V lower than the power supply potential VDD, Decrement. Based on the value for switching the potentials of the switching signals CT0, CT1, CT2, and CT3, the potentials of the switching signals CT0, CT1, CT2, and CT3 are determined. In the synthesizer circuit 101, the time constant of the frequency change is set to a value equal to or larger than the PLL loop time constant.

  According to the first embodiment, the second embodiment, or the third embodiment, in the voltage controlled oscillator 21, the capacitance values of the coarse adjustment varactors 22, 23, 24, and 25 are gradually decreased with the time constant of the switching signal having a dull waveform. Since it changes, the total capacitance value of the resonance circuit changes slowly. According to the fourth embodiment, the opening / closing of the switches 86, 87, 88, 89 for controlling the connection and disconnection of the coarse adjustment capacitors 82, 83, 84, 85 to the resonance circuit is the time constant of the switching signal having a dull waveform. Therefore, the total capacitance value of the resonance circuit changes gradually. Further, according to the fourth embodiment, even after the semiconductor circuit is created, the time constant setting unit 96 is operated from the outside to select the number of capacitive elements or resistance elements that are effective as RC filters. Adjustment can be made freely. Further, the third or fourth embodiment has an advantage that it can be realized more easily than the first or second embodiment. According to the fifth embodiment, there is an effect that the phase synchronization of the synthesizer circuit is not lost at the transition between the voltage-frequency characteristic curves of the voltage controlled oscillator having a plurality of voltage-frequency characteristic curves.

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary note 1) In a voltage controlled oscillator that adjusts an oscillation frequency by changing a capacitance value with a voltage signal,
A variable capacitance element whose capacitance value is changed by an adjustment signal whose potential continuously changes;
A switching signal;
Capacitance switching means for outputting the switching signal and controlling the capacitive element by the switching signal;
Control voltage generating means for adjusting a time constant of potential change of the switching signal input from the capacitance switching means;
A voltage-controlled oscillator comprising:

(Supplementary note 2) The capacitive element includes one or more variable capacitive elements, and the variable capacitive element changes a capacitance value with a time constant of the switching signal adjusted by the control voltage generating means. The voltage controlled oscillator according to Supplementary Note 1, wherein the voltage controlled oscillator is characterized.

(Supplementary Note 3) The control voltage generating means has a current value for controlling the amount of current, a capacitance value determined by the amount of current flowing through the current source and a desired time constant, and the input from the capacitance switching means. When the switching signal is at one of a high level having a relatively high potential and a low level having a relatively low potential, the current flowing from the current source is charged and is at the other level. And a capacitor for adjusting the time constant that discharges to
The voltage-controlled oscillator according to claim 2, wherein the waveform of the switching signal input from the capacitance switching unit is blunted by charging and discharging of the capacitor for adjusting the time constant.

(Supplementary Note 4) The control voltage generation means includes an inverter circuit that uses the switching signal input from the capacity switching means as an input signal, and the time constant adjusting capacitance element is connected in parallel to the output terminal of the inverter circuit. 4. The voltage controlled oscillator according to appendix 3, wherein the voltage controlled oscillator is connected.

(Supplementary Note 5) The control voltage generation means includes a digital-analog conversion means that outputs a potential of three or more values according to an input signal and a clock signal having a frequency corresponding to a desired time constant input from the outside. Comparison / addition / subtraction means for comparing the output potential of the digital-analog conversion means and the potential of the switching signal input from the capacitance switching means to change the input signal to the digital-analog conversion means stepwise,
The voltage controlled oscillator according to appendix 2, wherein the output potential is changed stepwise by feedback control of the output potential of the digital-analog conversion means until it matches the input potential from the switching signal.

(Supplementary Note 6) The control voltage generation means performs an increment operation or a decrement operation in synchronization with a clock signal having a frequency corresponding to a desired time constant input from the outside, and the switching signal input from the capacitance switching means The counter means for switching between the increment operation and the decrement operation based on its own state, and the count value of the counter means is acquired and held for each clock of a clock signal having a frequency corresponding to a desired time constant input from the outside. Digital-analog conversion means for outputting a potential according to the count value,
3. The voltage controlled oscillator according to appendix 2, wherein the output potential of the digital-analog conversion means is changed stepwise by a change in count value due to an increment operation or a decrement operation of the counter means.

(Supplementary note 7) The voltage controlled oscillator according to supplementary note 6, wherein when the count value reaches a predetermined value, the counter means continues to hold the predetermined value even when the clock signal is input.

(Supplementary note 8) The capacitive assembly controls connection and disconnection of the capacitive element to and from the resonance circuit based on the capacitive element having one or more fixed capacitance values and the switching signal input from the capacitive switching means. And a switch to
The control voltage generating unit includes an RC filter connected to a signal line of the switching signal input from the capacitance switching unit, and the RC filter blunts the waveform of the switching signal input from the capacitance switching unit. The voltage controlled oscillator according to appendix 1, characterized by:

(Supplementary note 9) The RC filter according to Supplementary note 8, wherein the RC filter includes a plurality of capacitive elements that can be connected or disconnected in parallel to a signal line of the switching signal input from the capacitance switching means. .

(Supplementary note 10) The RC filter according to supplementary note 8, wherein the RC filter includes a plurality of resistance elements that can be connected or disconnected in parallel to a signal line of the switching signal input from the capacitance switching means. .

(Supplementary Note 11) The RC filter includes a plurality of capacitive elements that can be connected or disconnected in parallel to the signal line of the switching signal input from the capacitance switching means, and a plurality of capacitors that can be connected or disconnected in parallel to the signal line. The voltage controlled oscillator according to claim 8, further comprising: a resistive element.

(Supplementary note 12) A voltage-controlled oscillator that adjusts the oscillation frequency by changing a capacitance value with a voltage signal, a frequency-dividing circuit that divides the output signal of the voltage-controlled oscillator, and a phase of the output signal of the frequency-dividing circuit; A phase comparison circuit that compares the phase of a reference clock signal input from the outside and outputs a voltage signal corresponding to the phase difference; and a filter that smoothes the output signal of the phase comparison circuit. In a synthesizer circuit that supplies a smoothed voltage signal to the voltage controlled oscillator as a voltage signal that changes a capacitance value of the voltage controlled oscillator,
The voltage-controlled oscillator includes a fine-adjustment variable capacitance element whose capacitance value is changed by a fine-adjustment signal whose potential changes continuously, and one or two or more for coarse adjustment controlled by one or more switching signals. A capacitance assembly composed of a capacitive element, a capacitance switching means for outputting the switching signal, and a control voltage generating means for adjusting a time constant of a potential change of the switching signal input from the capacitance switching means, and having a frequency A synthesizer circuit characterized in that the time constant of change is set to a value equal to or greater than the loop time constant of the PLL.

(Supplementary note 13) The capacitance assembly includes one or more variable capacitance elements, and the variable capacitance elements change a capacitance value with a time constant of the switching signal adjusted by the control voltage generating means. 14. The synthesizer circuit according to appendix 12.

(Supplementary Note 14) The control voltage generating means has a current value for controlling the amount of current, a capacity value determined by the amount of current flowing through the current source and a desired time constant, and the input from the capacity switching means. When the switching signal is at one of a high level having a relatively high potential and a low level having a relatively low potential, the current flowing from the current source is charged and is at the other level. And a capacitor for adjusting the time constant that discharges to
14. The synthesizer circuit according to appendix 13, wherein the waveform of the switching signal input from the capacitance switching means is blunted by charging / discharging of the time constant adjusting capacitance element.

(Supplementary Note 15) The control voltage generation means includes an inverter circuit that uses the switching signal input from the capacitance switching means as an input signal, and the time constant adjusting capacitance element is connected in parallel to the output terminal of the inverter circuit. The synthesizer circuit according to appendix 14, wherein the synthesizer circuit is connected.

(Supplementary Note 16) The control voltage generation means includes a digital-analog conversion means that outputs a potential of three or more values according to an input signal, and a clock signal having a frequency according to a desired time constant input from the outside. Comparison / addition / subtraction means for comparing the output potential of the digital-analog conversion means and the potential of the switching signal input from the capacitance switching means to change the input signal to the digital-analog conversion means stepwise,
14. The synthesizer circuit according to appendix 13, wherein the output potential is changed stepwise by feedback control of the output potential of the digital-analog conversion means until it matches the input potential from the switching signal.

(Supplementary Note 17) The control voltage generation unit performs an increment operation or a decrement operation in synchronization with a clock signal having a frequency corresponding to a desired time constant input from the outside, and the switching signal input from the capacitance switching unit The counter means for switching between the increment operation and the decrement operation based on its own state, and the count value of the counter means is acquired and held for each clock of a clock signal having a frequency corresponding to a desired time constant input from the outside. Digital-analog conversion means for outputting a potential according to the count value,
14. The synthesizer circuit according to appendix 13, wherein the output potential of the digital-analog conversion means is changed stepwise by a change in count value due to an increment operation or a decrement operation of the counter means.

(Supplementary note 18) The synthesizer circuit according to supplementary note 17, wherein when the count value reaches a predetermined value, the counter means continues to hold the predetermined value even if the clock signal is input.

(Supplementary note 19) The capacitive assembly controls connection and disconnection of the capacitive element to and from the resonance circuit based on the capacitive element having one or more fixed capacitance values and the switching signal input from the capacitive switching means. And a switch to
The control voltage generating unit includes an RC filter connected to a signal line of the switching signal input from the capacitance switching unit, and the RC filter blunts the waveform of the switching signal input from the capacitance switching unit. 14. The synthesizer circuit according to appendix 12.

(Supplementary note 20) The synthesizer circuit according to supplementary note 19, wherein the RC filter includes a plurality of capacitive elements that can be connected or disconnected in parallel to a signal line of the switching signal input from the capacitance switching means.

(Supplementary note 21) The synthesizer circuit according to supplementary note 19, wherein the RC filter includes a plurality of resistance elements that can be connected or disconnected in parallel to a signal line of the switching signal input from the capacitance switching means.

(Appendix 22) The RC filter includes a plurality of capacitive elements that can be connected or disconnected in parallel to the signal line of the switching signal input from the capacitance switching means, and a plurality of capacitors that can be connected or disconnected in parallel to the signal line. The synthesizer circuit according to appendix 19, wherein the synthesizer circuit is provided.

  As described above, the voltage-controlled oscillator and the synthesizer circuit according to the present invention are useful in the field of wireless communication such as television broadcasting and mobile phones, and are particularly suitable for wireless data communication terminals.

21, 81 Voltage controlled oscillator 22, 23, 24, 25 Coarse adjustment varactor 30 Fine adjustment varactor 33 Capacitance switching unit 34 Control voltage generation unit 41 Inverter circuit 42, 43 Current source 44 Time constant adjustment capacitor 51 Digital analog conversion circuit 52 Comparison / Addition / Subtraction Circuit 56 Self-State Determination Counter 57 CLK Triggered Digital / Analog Conversion Circuit 82, 83, 84, 85 Coarse Adjustment Capacitor 86, 87, 88, 89 Switch 91, 92, 93, 97 RC Filter 101 Synthesizer Circuit 102 Frequency divider 103 Phase comparator 105 Filter

Claims (8)

In the voltage controlled oscillator for adjusting the oscillation frequency by changing the capacitance value,
Capacity switching means for outputting a plurality of switching signals;
A plurality of control voltage generating means for outputting a plurality of adjustment signals each of which adjusts the potential change time so that the potential change times of the plurality of switching signals output by the capacitance switching means are long;
A plurality of variable capacitance elements whose capacitance values change according to voltage values of the plurality of adjustment signals output by the plurality of control voltage generating means;
A voltage-controlled oscillator comprising: The control voltage generating means is
A current source for controlling the amount of current;
A capacitive element that charges current flowing by the current source when the switching signal is at a first level and discharges when the switching signal is at a second level;
Wherein the charging and discharging of the capacitor, the voltage controlled oscillator according to claim 1, characterized in also be output from the adjustment signal blunted waveform of the switching signal. The control voltage generating means is
Digital-to-analog conversion means for outputting the adjustment signal having a potential of three or more values according to an input signal;
The digital-to-analog conversion is performed by comparing the output potential of the digital-analog conversion means with the potential of the switching signal input from the capacitance switching means for each clock of a clock signal having a frequency corresponding to a desired time constant input from the outside. Comparison / addition / subtraction means for stepwise changing the input signal to the means,
2. The voltage controlled oscillator according to claim 1 , wherein the adjustment signal is changed stepwise by feedback control of the adjustment signal which is an output of the digital-analog conversion means. The control voltage generation means performs an increment operation or a decrement operation in synchronization with a clock signal having a frequency corresponding to a desired time constant input from the outside, and is in the state of the switching signal input from the capacitance switching means and its own state. a counter means for switching the increment operation and the decrement operation on the basis, for each clock of a frequency of the clock signal corresponding to the desired time constant to be input from the outside, and acquires and holds the count value of said counter means, said count Digital-to-analog conversion means for outputting a potential corresponding to the value,
2. The voltage controlled oscillator according to claim 1 , wherein the adjustment signal , which is an output of the digital-analog conversion means , is changed in a stepwise manner by a change in count value caused by an increment operation or a decrement operation of the counter means. A frequency divider that divides the input signal;
A phase comparison circuit that compares the phase of the output signal of the frequency divider circuit with the phase of a reference clock signal input from the outside and outputs a first voltage signal corresponding to the phase difference;
A filter for smoothing the first voltage signal of the phase comparison circuit;
A voltage-controlled oscillator that supplies an output signal whose oscillation frequency is adjusted based on the second voltage signal smoothed by the filter to the frequency divider as the input signal,
The voltage controlled oscillator is:
Capacity switching means for outputting a plurality of switching signals;
A plurality of control voltage generating means for outputting a plurality of adjustment signals each of which adjusts the potential change time so that the potential change times of the plurality of switching signals output by the capacitance switching means are long;
A first fine-tuning variable capacitance element whose capacitance value is changed by the second voltage signal;
A plurality of second coarse adjustment variable capacitance elements whose capacitance values change according to the voltage values of the plurality of adjustment signals output by the plurality of control voltage generating means;
A synthesizer circuit comprising: The control voltage generating means is
A current source for controlling the amount of current;
A capacitive element that charges current flowing by the current source when the switching signal is at a first level and discharges when the switching signal is at a second level;
The charging and discharging of the capacitor, the synthesizer circuit of claim 5, wherein also be output from the adjustment signal blunted waveform of the switching signal. The control voltage generation means includes a digital-to-analog conversion means for outputting the adjustment signal having a potential of three or more values according to an input signal, and a clock signal having a frequency corresponding to a desired time constant input from the outside. Comparison / addition / subtraction means for comparing the output potential of the digital / analog conversion means with the potential of the switching signal input from the capacitance switching means to change the input signal to the digital / analog conversion means stepwise. ,
6. The synthesizer circuit according to claim 5 , wherein the adjustment signal is changed stepwise by feedback control of the adjustment signal which is an output of the digital-analog conversion means. The control voltage generation means performs an increment operation or a decrement operation in synchronization with a clock signal having a frequency corresponding to a desired time constant input from the outside, and is in the state of the switching signal input from the capacitance switching means and its own state. a counter means for switching the increment operation and the decrement operation on the basis, for each clock of a frequency of the clock signal corresponding to the desired time constant to be input from the outside, and acquires and holds the count value of said counter means, said count Digital-to-analog conversion means for outputting a potential corresponding to the value,
6. The synthesizer circuit according to claim 5 , wherein the adjustment signal , which is an output of the digital-analog conversion means , is changed stepwise in accordance with a change in count value caused by an increment operation or a decrement operation of the counter means.

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