JP2008206010A5 - - Google Patents
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- JP2008206010A5 JP2008206010A5 JP2007041971A JP2007041971A JP2008206010A5 JP 2008206010 A5 JP2008206010 A5 JP 2008206010A5 JP 2007041971 A JP2007041971 A JP 2007041971A JP 2007041971 A JP2007041971 A JP 2007041971A JP 2008206010 A5 JP2008206010 A5 JP 2008206010A5
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- signal
- frequency
- oscillation signal
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- time
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- 238000006243 chemical reaction Methods 0.000 claims 7
- 238000000605 extraction Methods 0.000 claims 2
- 238000001514 detection method Methods 0.000 claims 1
- 238000005259 measurement Methods 0.000 claims 1
Claims (6)
前記発振回路からの発振信号を受け入れ、当該発振信号を分周して、局部発振信号を生成するとともに、当該発振信号を分周して、フィルタ制御用のクロック信号を生成する分周器と、
前記局部発振信号および受信信号を受け入れて、これらの信号を混合して中間周波数の信号を出力するミキサと、
前記クロック信号に応じて、通過させる信号の周波数を変更可能な可変型フィルタと、を備え、
前記可変型フィルタにおける前記周波数と、前記中間周波数とがほぼ一致するように、前記分周器における分周比が決定されることを特徴とする周波数変換回路。 An oscillation circuit that outputs a reference signal or a signal obtained by multiplying the reference signal as an oscillation signal;
A frequency divider that receives an oscillation signal from the oscillation circuit, divides the oscillation signal, generates a local oscillation signal, divides the oscillation signal, and generates a clock signal for filter control;
A mixer that receives the local oscillation signal and the received signal, mixes these signals, and outputs an intermediate frequency signal;
A variable filter capable of changing the frequency of a signal to be passed according to the clock signal,
The frequency conversion circuit according to claim 1, wherein a frequency division ratio in the frequency divider is determined so that the frequency in the variable filter and the intermediate frequency substantially coincide.
前記第１の局部発振信号および受信信号を受け入れて、これらの信号を混合して第１の中間周波数の信号を出力する第１のミキサと、
前記第２の局部発振信号および前記第１のミキサの出力信号を受け入れて、これらの信号を混合して第２の中間周波数の信号を出力する第２のミキサと、を備え、
前記可変型フィルタにおける前記周波数と、前記第２の中間周波数とがほぼ一致するように、前記分周器における分周比が決定されることを特徴とする請求項１に記載の周波数変換回路。 The frequency divider generates a first local oscillation signal obtained by dividing the oscillation signal by N1, and a second local oscillation signal obtained by dividing the oscillation signal by N2.
A first mixer that receives the first local oscillation signal and the received signal, mixes these signals, and outputs a first intermediate frequency signal;
A second mixer that receives the second local oscillation signal and an output signal of the first mixer, mixes these signals, and outputs a signal of a second intermediate frequency, and
2. The frequency conversion circuit according to claim 1, wherein a frequency division ratio in the frequency divider is determined so that the frequency in the variable filter and the second intermediate frequency substantially coincide with each other.
前記第１の局部発振信号および受信信号を受け入れて、これらの信号を混合して第１の中間周波数の信号を出力する第１のミキサと、第ｉの局部発振信号（ただし、ｉ＝２〜ｎ）および第（ｉ−１）の中間周波数信号を受け入れて、これらの信号を混合して第ｉの局部発振信号を、それぞれ出力する第ｉのミキサと、を備え、
前記可変型フィルタにおける前記周波数と、前記第ｎの中間周波数とがほぼ一致するように、前記分周器における分周比が決定されることを特徴とする請求項１に記載の周波数変換回路。 The frequency divider generates each of the jth local oscillation signals obtained by dividing the oscillation signal by Nj (j = 1 to n).
A first mixer that receives the first local oscillation signal and the reception signal, mixes these signals and outputs a first intermediate frequency signal, and an i-th local oscillation signal (where i = 2 to 2). n) and (i-1) intermediate frequency signals are received, and these signals are mixed to output an i th local oscillation signal, respectively, and an i th mixer, respectively.
2. The frequency conversion circuit according to claim 1, wherein a frequency division ratio in the frequency divider is determined so that the frequency in the variable filter substantially matches the n-th intermediate frequency.
一定の周波数の基準信号を発生する基準信号発生器と、A reference signal generator for generating a reference signal of constant frequency;
制御電圧にしたがった周波数の信号を発生する電圧制御発振器と、A voltage controlled oscillator that generates a signal of a frequency according to the control voltage; and
電圧制御発振器から出力される発振信号を分周する分周器と、A frequency divider for dividing the oscillation signal output from the voltage controlled oscillator;
前記分周器から出力された分周信号と、前記基準信号とを比較して位相差を示す信号を出力する位相比較器と、A phase comparator that outputs a signal indicating a phase difference by comparing the frequency-divided signal output from the frequency divider and the reference signal;
位相比較器からの信号に基づいて前記電圧制御発振器の制御電圧を出力するループフィルタと、を有することを特徴とする請求項１ないし３の何れか一項に記載の周波数変換回路。4. The frequency conversion circuit according to claim 1, further comprising: a loop filter that outputs a control voltage of the voltage controlled oscillator based on a signal from the phase comparator. 5.
前記アンテナ回路により得られた受信信号を増幅する増幅回路と、An amplifier circuit for amplifying the received signal obtained by the antenna circuit;
請求項１ないし４の何れか一項に記載された周波数変換回路であって、前記増幅回路から出力された信号を周波数変換して中間周波数信号を出力する周波数変換回路と、A frequency conversion circuit according to any one of claims 1 to 4, wherein the frequency conversion circuit outputs the intermediate frequency signal by frequency-converting the signal output from the amplifier circuit;
前記周波数変換回路から出力された中間周波数信号を検波する検波回路と、を備えたことを特徴とする受信回路。And a detection circuit for detecting an intermediate frequency signal output from the frequency conversion circuit.
前記受信回路により受信および復調された、時刻情報を含む標準時刻電波の信号から、時刻情報を抽出する時刻情報抽出手段と、Time information extraction means for extracting time information from a standard time radio wave signal including time information received and demodulated by the receiving circuit;
時刻を計時する計時手段と、A time measuring means for measuring time;
当該計時手段により計時された時刻を表示する時刻表示手段と、Time display means for displaying the time measured by the time measuring means;
前記時刻情報抽出手段により抽出された時刻情報に基づいて、前記計時手段により計時された時刻を修正する時刻修正手段と、を備えたことを特徴とする電波時計。A radio timepiece comprising: time correction means for correcting the time measured by the time measurement means based on the time information extracted by the time information extraction means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007041971A JP2008206010A (en) | 2007-02-22 | 2007-02-22 | Frequency converting circuit, reception circuit, and radio clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007041971A JP2008206010A (en) | 2007-02-22 | 2007-02-22 | Frequency converting circuit, reception circuit, and radio clock |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2008206010A JP2008206010A (en) | 2008-09-04 |
| JP2008206010A5 true JP2008206010A5 (en) | 2010-03-11 |
Family
ID=39782977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007041971A Pending JP2008206010A (en) | 2007-02-22 | 2007-02-22 | Frequency converting circuit, reception circuit, and radio clock |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2008206010A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8606209B2 (en) * | 2009-06-24 | 2013-12-10 | Intel Corporation | Apparatus and methods for efficient implementation of tuners |
| JP7375447B2 (en) * | 2019-10-15 | 2023-11-08 | セイコーエプソン株式会社 | How to adjust the time of a radio-controlled watch and a radio-controlled watch |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06284037A (en) * | 1993-03-26 | 1994-10-07 | Casio Comput Co Ltd | Digital moving body communication device |
| JPH09298482A (en) * | 1996-05-08 | 1997-11-18 | Hitachi Ltd | Digital portable telephone set |
| JPH11196016A (en) * | 1998-01-05 | 1999-07-21 | Matsushita Electric Ind Co Ltd | Frequency converter and frequency conversion method therefor |
| JP4316198B2 (en) * | 2002-07-24 | 2009-08-19 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor device, receiver, and control method of semiconductor device |
| JP2004080073A (en) * | 2002-08-09 | 2004-03-11 | Casio Comput Co Ltd | Radio wave receiver and radio-controlled timepiece |
| JP2006339868A (en) * | 2005-05-31 | 2006-12-14 | Alps Electric Co Ltd | Terrestrial digital broadcast reception tuner |
-
2007
- 2007-02-22 JP JP2007041971A patent/JP2008206010A/en active Pending
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