JP2008205266A - Led package - Google Patents

Led package Download PDF

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Publication number
JP2008205266A
JP2008205266A JP2007040673A JP2007040673A JP2008205266A JP 2008205266 A JP2008205266 A JP 2008205266A JP 2007040673 A JP2007040673 A JP 2007040673A JP 2007040673 A JP2007040673 A JP 2007040673A JP 2008205266 A JP2008205266 A JP 2008205266A
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Prior art keywords
led chip
substrate
circuit patterns
led
package
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JP2007040673A
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JP4687665B2 (en
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Masahiro Sato
正博 佐藤
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Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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Priority to JP2007040673A priority Critical patent/JP4687665B2/en
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to PCT/JP2008/052154 priority patent/WO2008099784A1/en
Priority to US12/527,069 priority patent/US20100032189A1/en
Priority to KR1020097016780A priority patent/KR20090104860A/en
Priority to CN200880005314A priority patent/CN101617412A/en
Priority to EP08711033A priority patent/EP2110866A4/en
Priority to TW097105404A priority patent/TW200901512A/en
Publication of JP2008205266A publication Critical patent/JP2008205266A/en
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Publication of JP4687665B2 publication Critical patent/JP4687665B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

<P>PROBLEM TO BE SOLVED: To provide an LED package that prevents poor conduction by preventing breakage of solder while effectively reducing a stress developed due to a difference in linear expansion coefficient in-between a mounting substrate. <P>SOLUTION: The LED package includes a three-dimensional substrate 12 mounted onto a mounting substrate, which is mounted with an LED chip 11 so as to be electrically connected with the LED chip 11, and a plurality of circuit patterns 14A, 14B that are respectively connected with the LED chip 11 and each circuit pattern on the mounting substrate via solder and formed along the outer wall of the three-dimensional substrate 12. A plurality of the circuit patterns 14A, 14B are respectively formed on each side face adjacent to each other in a plurality of side faces of the three-dimensional substrate 12. Alternatively, a plurality of the circuit patterns 14A, 14B may be respectively formed on the single side face in a plurality of the side faces of the three-dimensional substrate 12. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、発光ダイオード（Light Emitting Diode；以下、ＬＥＤという。）チップをパッケージ本体に実装したＬＥＤパッケージに関する。   The present invention relates to an LED package in which a light emitting diode (hereinafter referred to as LED) chip is mounted on a package body.

従来から、ＬＥＤチップを所定のパッケージ本体に実装し、これをプリント回路基板等の実装基板に実装するＬＥＤパッケージが提案されている。かかるＬＥＤパッケージは、ハンダによってＬＥＤチップを実装基板に実装する際に、電極間でハンダ量に差があると、ハンダが溶融したときの表面張力の差やハンダが固化するときの収縮応力等に起因して、一方の電極が浮き上がる、いわゆる、マンハッタン現象を生じるという問題がある。これを解決するために、特許文献１に記載された技術が提案されている。   Conventionally, an LED package in which an LED chip is mounted on a predetermined package body and mounted on a mounting board such as a printed circuit board has been proposed. Such an LED package has a difference in surface tension when the solder is melted or a shrinkage stress when the solder is solidified when there is a difference in the amount of solder between the electrodes when the LED chip is mounted on the mounting substrate by solder. As a result, there is a problem that a so-called Manhattan phenomenon occurs in which one electrode floats. In order to solve this, the technique described in Patent Document 1 has been proposed.

この特許文献１には、一方の面が素子取付面とされて素子用電極が設けられ他方の面が取付面とされて端子用電極が設けられる板状基板を有する発光ダイオードが開示されている。特に、この発光ダイオードは、板状基板に一方の面から他方の面に達するスルーホール電極を設け、このスルーホール電極によって素子用電極と端子用電極との電気的接続を行うことにより、ハンダ量に不均一を生じているときであっても、板状基板に一方の端部を浮き上がらせるような応力を生じることをなくし、導通不良を防止することができるとしている。
特開２０００−２１６４４０号公報 This Patent Document 1 discloses a light emitting diode having a plate-like substrate in which one surface is an element mounting surface and an element electrode is provided, and the other surface is a mounting surface and a terminal electrode is provided. . In particular, this light-emitting diode is provided with a through-hole electrode that extends from one surface to the other surface on a plate-like substrate, and by making electrical connection between the element electrode and the terminal electrode by this through-hole electrode, the amount of solder Even when non-uniformity occurs, stress that lifts one end of the plate-like substrate is eliminated, and poor conduction can be prevented.
JP 2000-216440 A

ところで、ＬＥＤパッケージにおいては、実装基板にハンダ実装した場合には、実装基板の線膨張率がＬＥＤパッケージの線膨張率よりも大きい。熱履歴によってＬＥＤパッケージと実装基板上の配線パターンとの接続部分に応力が集中した場合、当該現象を起因として、ヒートサイクル試験等の際にハンダが破壊することがあり、導通不良を起こすという問題があった。この問題は、パッケージ本体がセラミックス材などで形成されていることに起因し、使用時のみならず、はんだ実装時においても問題になることがある。   By the way, in the LED package, when solder mounting is performed on the mounting substrate, the linear expansion coefficient of the mounting substrate is larger than the linear expansion coefficient of the LED package. When stress concentrates on the connection part between the LED package and the wiring pattern on the mounting board due to the thermal history, the solder may break down during the heat cycle test, etc. due to this phenomenon, causing a conduction failure was there. This problem is caused by the fact that the package body is formed of a ceramic material or the like, and may become a problem not only during use but also during solder mounting.

そこで、本発明は、上述したような問題を解決するために案出されたものであり、実装基板との線膨張率の違いに起因して発生する応力によるハンダの破壊を防止し、導通不良を防止することができるＬＥＤパッケージを提供することを目的とする。   Therefore, the present invention has been devised to solve the above-described problems, and prevents solder breakage due to stress generated due to a difference in linear expansion coefficient from the mounting substrate, and poor conduction. It aims at providing the LED package which can prevent.

本発明は、ＬＥＤチップが実装されて、当該ＬＥＤチップと電気的に接続される実装基板上に実装される立体型基板と、前記ＬＥＤチップ及び前記実装基板上の回路パターンとハンダを介して接続され、前記立体型基板の外壁に沿って形成される複数の回路パターンとを備える。   The present invention provides a three-dimensional substrate mounted on a mounting substrate on which an LED chip is mounted and electrically connected to the LED chip, and the LED chip and the circuit pattern on the mounting substrate are connected via solder. And a plurality of circuit patterns formed along the outer wall of the three-dimensional substrate.

このようなＬＥＤパッケージは、上述の課題を解決するために、複数の回路パターンは、前記立体型基板の複数の側面のうちの隣接する側面に、それぞれ形成される。また、ＬＥＤパッケージは、上述の課題を解決するために、複数の回路パターンは、前記立体型基板の複数の側面のうちの単一の側面に、それぞれ形成されていても良い。   In such an LED package, in order to solve the above-described problems, a plurality of circuit patterns are respectively formed on adjacent side surfaces of the plurality of side surfaces of the three-dimensional substrate. In the LED package, in order to solve the above-described problem, the plurality of circuit patterns may be respectively formed on a single side surface among the plurality of side surfaces of the three-dimensional substrate.

本発明によれば、複数の回路パターンを、立体型基板の複数の側面のうちの隣接する側面又は単一の側面に、それぞれ形成し、当該複数の回路パターン間の距離を近くする。これによって、立体型基板と実装基板との線膨張率の違いに起因して応力が発生しても、回路パターン間の距離が小さいので、絶対的に膨張する量が少なく、立体型基板と実装基板とを接続するハンダの破壊を防止し、導通不良を防止することができる。   According to the present invention, a plurality of circuit patterns are formed on adjacent side surfaces or a single side surface among a plurality of side surfaces of a three-dimensional substrate, and the distance between the plurality of circuit patterns is reduced. As a result, even if stress occurs due to the difference in linear expansion coefficient between the three-dimensional board and the mounting board, the distance between the circuit patterns is small, so the amount of absolute expansion is small, and the three-dimensional board and the mounting board are mounted. It is possible to prevent breakage of solder connecting to the substrate and to prevent poor conduction.

以下、本発明の実施の形態について図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１及び図２に、ＬＥＤチップ１１を実装するパッケージ本体１０の外観構成を示す斜視図を示す。   1 and 2 are perspective views showing the external configuration of the package body 10 on which the LED chip 11 is mounted.

図１及び図２に示すパッケージ本体１０は、ＬＥＤチップ１１の正端子が接続される回路パターン１４Ａと、ＬＥＤチップ１１の負端子が接続される回路パターン１４Ｂとを近接して配置したことを特徴としたものである。図１に示すパッケージ本体１０は、立体状の本体部１２の４側面のうちの隣接する２つの側面に回路パターン１４Ａ，１４Ｂを配設した状態を示している。図２に示すパッケージ本体１０は、立体状の本体部１２の４側面のうちの単一の側面に回路パターン１４Ａ，１４Ｂを配設した状態を示している。   The package body 10 shown in FIGS. 1 and 2 is characterized in that a circuit pattern 14A to which the positive terminal of the LED chip 11 is connected and a circuit pattern 14B to which the negative terminal of the LED chip 11 is connected are arranged close to each other. It is what. The package body 10 shown in FIG. 1 shows a state in which circuit patterns 14A and 14B are disposed on two adjacent side surfaces of the four side surfaces of the three-dimensional body portion 12. The package main body 10 shown in FIG. 2 shows a state in which circuit patterns 14A and 14B are arranged on a single side surface among the four side surfaces of the three-dimensional main body portion 12.

このように、ＬＥＤチップ１１に接続する回路パターンが複数存在しても、当該複数の回路パターンを近接して配設する。回路パターン１４Ａ，１４Ｂと実装基板とをハンダ付けで固定し、それ以外をフリーにして、パッケージ本体１０を実装基板に対して固定させる。これにより、ＬＥＤチップ１１が発熱した時の、ハンダ付けされている回路パターン１４Ａ，１４Ｂ間の本体部１２の絶対的な膨張量を小さくし、ハンダにクラックが発生することを防止する。   Thus, even if there are a plurality of circuit patterns connected to the LED chip 11, the plurality of circuit patterns are arranged close to each other. The circuit patterns 14A and 14B and the mounting board are fixed by soldering, and the other parts are made free to fix the package body 10 to the mounting board. As a result, the absolute expansion amount of the main body 12 between the soldered circuit patterns 14A and 14B when the LED chip 11 generates heat is reduced, and cracks are prevented from occurring in the solder.

パッケージ本体１０は、例えばセラミック焼結体からなる本体部１２を有する。セラミックス材としては、アルミナ、窒化アルミ、窒化珪素などがある。セラミック焼結体の製造方法としては、射出成形、圧縮成形（プレス成形）、鋳込み成形等があるが、パッケージ本体１０を製造するにあたっては、いずれの方法を用いてもよい。本体部１２は、中央部分に頭切円錐状の窪みが形成され、底面にＬＥＤチップ１１が実装されるように構成されている。   The package main body 10 has a main body 12 made of, for example, a ceramic sintered body. Examples of the ceramic material include alumina, aluminum nitride, and silicon nitride. As a method for manufacturing the ceramic sintered body, there are injection molding, compression molding (press molding), casting molding, and the like. Any method may be used for manufacturing the package body 10. The main body portion 12 is configured such that a truncated cone-shaped depression is formed in the central portion, and the LED chip 11 is mounted on the bottom surface.

この頭切円錐状の窪みの底面は、ＬＥＤチップ１１を実装するＬＥＤチップ１１の実装面として用いられる。このＬＥＤチップ１１の実装面には、回路パターン１４Ａ，１４Ｂの一部を構成するＬＥＤチップ実装部１３Ａ，１３Ｂが形成されている。ＬＥＤチップ実装部１３Ａには、ＬＥＤチップ１１が取り付けられる。ＬＥＤチップ実装部１３Ｂには、ＬＥＤチップ１１と接続されたワイヤ１６がハンダ付けされる。ＬＥＤチップ実装部１３Ａは、回路パターン１４Ａを介して、ＬＥＤチップ１１の駆動電流が供給される。ＬＥＤチップ実装部１３Ｂは、回路パターン１４Ｂを介して接地端子（図示せず）が接続される。これにより、パッケージ本体１０は、このＬＥＤチップ１１の実装面から本体部１２の側面にかけて所定の回路パターン（配線）１４Ａ，１４Ｂが設けられた立体型基板（Molded Interconnect Device;MID）として機能することになる。   The bottom surface of the truncated cone-shaped recess is used as a mounting surface of the LED chip 11 on which the LED chip 11 is mounted. On the mounting surface of the LED chip 11, LED chip mounting portions 13A and 13B constituting part of the circuit patterns 14A and 14B are formed. The LED chip 11 is attached to the LED chip mounting portion 13A. A wire 16 connected to the LED chip 11 is soldered to the LED chip mounting portion 13B. The LED chip mounting portion 13A is supplied with the drive current of the LED chip 11 via the circuit pattern 14A. The LED chip mounting portion 13B is connected to a ground terminal (not shown) via the circuit pattern 14B. Thereby, the package body 10 functions as a three-dimensional substrate (Molded Interconnect Device; MID) provided with predetermined circuit patterns (wirings) 14A and 14B from the mounting surface of the LED chip 11 to the side surface of the body portion 12. become.

また、頭切円錐状の窪みの円錐面は、ＬＥＤチップ１１から放射された光を反射する反射板１５として機能する。ＬＥＤパッケージは、反射板１５をこのような円錐面とすることにより、高い信頼性及び光取り出し効率を実現することができる。なお、パッケージ本体１０においては、反射板１５の部分に高反射率の金属膜を形成するようにしてもよい。これにより、ＬＥＤパッケージにおいては、より高い信頼性及び光取り出し効率を実現することができる。   The conical surface of the truncated cone-shaped depression functions as a reflecting plate 15 that reflects light emitted from the LED chip 11. The LED package can achieve high reliability and light extraction efficiency by using the reflector 15 as such a conical surface. In the package body 10, a highly reflective metal film may be formed on the reflecting plate 15. Thereby, higher reliability and light extraction efficiency can be realized in the LED package.

このようなＬＥＤパッケージにおいては、薄膜輪郭除去法により、ＬＥＤチップ１１の実装面と反射板１５とを一体化したような立体回路基板を容易に形成することができる。この薄膜輪郭除去法は、以下のようなプロセスからなる。   In such an LED package, a three-dimensional circuit board in which the mounting surface of the LED chip 11 and the reflecting plate 15 are integrated can be easily formed by a thin film outline removing method. This thin film outline removing method includes the following processes.

まず、薄膜輪郭除去法においては、加熱処理プロセスを実行し、焼結体を温度１０００℃、保持時間１時間の条件で加熱処理し、表面を清浄化する。   First, in the thin film contour removal method, a heat treatment process is performed, and the sintered body is heat treated under the conditions of a temperature of 1000 ° C. and a holding time of 1 hour to clean the surface.

続いて、薄膜輪郭除去法は、導電性薄膜形成プロセスを実行する。このプロセスは、真空蒸着装置やＤＣマグネトロンスパッタリング装置等を使用した物理的蒸着法や無電解めっき等の湿式法等により、導電性薄膜を基板材料表面に形成するものである。具体的には、基板材料をプラズマ処理装置のチャンバ内にセットし、チャンバ内を１０−４Ｐａ程度に減圧した後、温度１００〜２００℃で３分間程度、焼結体を予備加熱する。その後、チャンバ内に窒素やアルゴンなどのガスを流通させるとともに、チャンバ内のガス圧を１０Ｐａ程度に制御する。そして、電極間に１００〜１０００Ｗの高周波電圧（ＲＦ：１３．５６ＭＨｚ）を１０〜３００秒間印加することにより、プラズマ処理を行う。続いて、チャンバ内の圧力を１０−４Ｐａ以下に制御し、この状態でチャンバ内にアルゴンガスをガス圧が０．６Ｐａ程度になるように導入した後、さらに３００〜６００Ｖの直流電圧を印加することにより、金属ターゲットをボンバートし、焼結体表面に膜厚が１００〜１０００ｎｍ程度の導電性薄膜を形成する。なお、導電性材料としては、銅、ニッケル、クロム、チタン等が用いられる。 Subsequently, the thin film outline removing method executes a conductive thin film forming process. In this process, a conductive thin film is formed on the surface of a substrate material by a physical vapor deposition method using a vacuum vapor deposition apparatus or a DC magnetron sputtering apparatus, or a wet method such as electroless plating. Specifically, the substrate material is set in the chamber of the plasma processing apparatus, the inside of the chamber is depressurized to about 10 −4 Pa, and then the sintered body is preheated at a temperature of 100 to 200 ° C. for about 3 minutes. Thereafter, a gas such as nitrogen or argon is circulated in the chamber, and the gas pressure in the chamber is controlled to about 10 Pa. Then, a plasma treatment is performed by applying a high-frequency voltage of 100 to 1000 W (RF: 13.56 MHz) between the electrodes for 10 to 300 seconds. Subsequently, the pressure in the chamber is controlled to 10 −4 Pa or less, and in this state, argon gas is introduced into the chamber so that the gas pressure is about 0.6 Pa, and then a DC voltage of 300 to 600 V is applied. By doing so, the metal target is bombarded, and a conductive thin film having a thickness of about 100 to 1000 nm is formed on the surface of the sintered body. Note that copper, nickel, chromium, titanium, or the like is used as the conductive material.

続いて、薄膜輪郭除去法においては、回路パターン形成プロセスを実行し、例えば図３中（ａ）に示すように、大気中でＹＡＧレーザーの第３高調波（ＴＨＧ−ＹＡＧレーザー）を使用して回路パターンの輪郭に沿ってレーザーを走査し、アルミナ基板３３上に形成された導電性薄膜３２のうち、回路パターン３１の輪郭部の薄膜のみを除去した薄膜除去部３０を形成する。   Subsequently, in the thin film contour removal method, a circuit pattern forming process is executed, and for example, as shown in FIG. 3A, the third harmonic of a YAG laser (THG-YAG laser) is used in the atmosphere. A laser is scanned along the contour of the circuit pattern to form a thin film removing portion 30 in which only the thin film at the contour portion of the circuit pattern 31 is removed from the conductive thin film 32 formed on the alumina substrate 33.

続いて、薄膜輪郭除去法においては、めっきプロセスを実行し、例えば図３中（ｂ）に示すように、焼結体表面の電気回路部のみに電解めっきによって銅めっき３４を施して厚膜化し、厚さが５〜１５μｍの銅膜を形成する。その後、例えば図３中（ｃ）に示すように、全面をエッチングすることによって、非電気回路部に残存している導電性薄膜３２をエッチングによって完全に除去する。このとき、銅めっき３４は、導電性薄膜３２よりも厚く形成されているために、残存する。そして、例えば図３中（ｄ）に示すように、電気回路部に電気めっきによってニッケルめっきや金めっき３５を施す。   Subsequently, in the thin film contour removal method, a plating process is performed, and, for example, as shown in FIG. 3B, only the electric circuit portion on the surface of the sintered body is subjected to copper plating 34 by electrolytic plating to increase the thickness. A copper film having a thickness of 5 to 15 μm is formed. Thereafter, for example, as shown in FIG. 3C, the entire surface is etched to completely remove the conductive thin film 32 remaining in the non-electric circuit portion by etching. At this time, since the copper plating 34 is formed thicker than the conductive thin film 32, it remains. Then, for example, as shown in FIG. 3D, nickel plating or gold plating 35 is applied to the electric circuit portion by electroplating.

ＬＥＤパッケージは、このような薄膜輪郭除去法によって容易に形成することができる。なお、ＬＥＤパッケージを薄膜輪郭除去法によって製造する場合には、上述した銅めっき、エッチング、ニッケルめっきまでのプロセスについては同様に行った上で、電気回路部のみに給電して金めっきを施すとともに、反射板１５のみに給電して例えば銀めっきを施せばよい。   The LED package can be easily formed by such a thin film outline removing method. In addition, when manufacturing an LED package by the thin film outline removing method, the above-described processes up to copper plating, etching, and nickel plating are performed in the same manner, and then only the electric circuit portion is supplied with gold plating. For example, silver plating may be performed by supplying power only to the reflector 15.

このようにして形成されるＬＥＤパッケージは、図４（ｄ）に示すように、ハンダ２１を介して所定の回路パターン２２が形成された実装基板２０上に実装される。このようなＬＥＤパッケージは、以下のようにして形成することができる。すなわち、ＬＥＤパッケージを製造するにあたっては、例えば図４中（ａ）に示すように、焼結体（本体部１２）を形成する。続いて、ＬＥＤパッケージを製造するにあたっては、例えば図４中（ｂ）に示すように、上述した薄膜輪郭除去法によって焼結体の表面に回路パターン１４Ａ，１４Ｂを形成し、図４中（ｃ）に示すように、ＬＥＤチップ実装面上に形成されたＬＥＤチップ実装部１３Ａ，１３ＢにＬＥＤチップ１１を実装する。この時、回路パターン１４Ａ，１４Ｂは、図１に示すように、本体部１２の４つの側面のうちの隣接する２つの側面に形成されても良く、図２に示すように、単一の側面のみに形成されることになる。その後に、図４（ｄ）に示すように、本体部１２のうちの回路パターン１４Ａ，１４Ｂと実装基板２０上の回路パターン２２とを接触させるように本体部１２を所定位置に配置する。その後、回路パターン１４Ａ，１４Ｂと回路パターン２２とをハンダ２１によってハンダ付けすることによって、本体部１２を実装基板２０上に固定する。   The LED package formed in this way is mounted on a mounting substrate 20 on which a predetermined circuit pattern 22 is formed via solder 21, as shown in FIG. 4 (d). Such an LED package can be formed as follows. That is, in manufacturing the LED package, for example, as shown in FIG. 4A, a sintered body (main body portion 12) is formed. Subsequently, in manufacturing the LED package, as shown in FIG. 4B, for example, the circuit patterns 14A and 14B are formed on the surface of the sintered body by the above-described thin film outline removing method. ), The LED chip 11 is mounted on the LED chip mounting portions 13A and 13B formed on the LED chip mounting surface. At this time, the circuit patterns 14A and 14B may be formed on two adjacent side surfaces of the four side surfaces of the main body 12 as shown in FIG. 1, or as shown in FIG. Will be formed only. After that, as shown in FIG. 4D, the main body 12 is arranged at a predetermined position so that the circuit patterns 14A and 14B in the main body 12 and the circuit pattern 22 on the mounting substrate 20 are brought into contact with each other. Thereafter, the circuit patterns 14 </ b> A and 14 </ b> B and the circuit pattern 22 are soldered with the solder 21, thereby fixing the main body 12 on the mounting substrate 20.

以上のように、本発明を適用したパッケージ本体１０によれば、複数の回路パターン１４Ａ，１４Ｂを近接させることによって、当該複数の回路パターン１４Ａ，１４Ｂ以外の部分を固定しないようにする。このようなパッケージ本体１０は、回路パターン１４Ａ，１４Ｂのハンダ２１の距離が短く、本体部１２が膨張しても、当該距離が短いために、絶対的なハンダ２１間の膨張量を小さくできる。これによって、ハンダ２１のクラックを防止でき、導通不良を防止することができる。   As described above, according to the package body 10 to which the present invention is applied, the portions other than the plurality of circuit patterns 14A and 14B are not fixed by bringing the plurality of circuit patterns 14A and 14B close to each other. In such a package main body 10, the distance between the solder 21 of the circuit patterns 14 </ b> A and 14 </ b> B is short, and even if the main body 12 expands, the distance between the solder main bodies 12 is short. Thereby, cracks in the solder 21 can be prevented, and poor conduction can be prevented.

なお、上述の実施の形態は本発明の一例である。このため、本発明は、上述の実施形態に限定されることはなく、この実施の形態以外であっても、本発明に係る技術的思想を逸脱しない範囲であれば、設計等に応じて種々の変更が可能であることは勿論である。   The above-described embodiment is an example of the present invention. For this reason, the present invention is not limited to the above-described embodiment, and various modifications can be made depending on the design and the like as long as the technical idea according to the present invention is not deviated from this embodiment. Of course, it is possible to change.

本発明の実施形態として示すＬＥＤパッケージにおけるパッケージ本体の外観構成を示す斜視図である。It is a perspective view which shows the external appearance structure of the package main body in the LED package shown as embodiment of this invention. 本発明の実施形態として示すＬＥＤパッケージにおけるパッケージ本体の他の外観構成を示す斜視図である。It is a perspective view which shows the other external appearance structure of the package main body in the LED package shown as embodiment of this invention. ＬＥＤパッケージを製造するための薄膜輪郭除去法の各プロセスについて説明するための図である。It is a figure for demonstrating each process of the thin film outline removal method for manufacturing a LED package. 本発明の実施形態として示すＬＥＤパッケージを製造する様子を説明するための図である。It is a figure for demonstrating a mode that the LED package shown as embodiment of this invention is manufactured.

符号の説明Explanation of symbols

１０ パッケージ本体
１１ ＬＥＤチップ
１２ 本体部
１３Ａ，１３Ｂ ＬＥＤチップ実装部
１４Ａ，１４Ｂ 回路パターン
１５ 反射板
１６ ワイヤ
２０ 実装基板
２１ ハンダ
２２ 回路パターン
３０ 薄膜除去部
３１ 回路パターン
３２ 導電性薄膜
３３ アルミナ基板 DESCRIPTION OF SYMBOLS 10 Package main body 11 LED chip 12 Main body part 13A, 13B LED chip mounting part 14A, 14B Circuit pattern 15 Reflector 16 Wire 20 Mounting board 21 Solder 22 Circuit pattern 30 Thin film removal part 31 Circuit pattern 32 Conductive thin film 33 Alumina substrate

Claims (2)

ＬＥＤチップが実装されて、当該ＬＥＤチップと電気的に接続される実装基板上に実装される立体型基板と、
前記ＬＥＤチップ及び前記実装基板上の回路パターンとハンダを介して接続され、前記立体型基板の外壁に沿って形成される複数の回路パターンとを備え、
前記複数の回路パターンは、前記立体型基板の複数の側面のうちの隣接する側面に、それぞれ形成されること
を特徴とするＬＥＤパッケージ。 A three-dimensional substrate mounted on a mounting substrate on which an LED chip is mounted and electrically connected to the LED chip;
A plurality of circuit patterns that are connected to the LED chip and the circuit pattern on the mounting substrate via solder and are formed along the outer wall of the three-dimensional substrate;
The LED package, wherein the plurality of circuit patterns are respectively formed on adjacent side surfaces of the plurality of side surfaces of the three-dimensional substrate. ＬＥＤチップが実装されて、当該ＬＥＤチップと電気的に接続される実装基板上に実装される立体型基板と、
前記ＬＥＤチップ及び前記実装基板上の回路パターンとハンダを介して接続され、前記立体型基板の外壁に沿って形成される複数の回路パターンとを備え、
前記複数の回路パターンは、前記立体型基板の複数の側面のうちの単一の側面に、それぞれ形成されること
を特徴とするＬＥＤパッケージ。 A three-dimensional substrate mounted on a mounting substrate on which an LED chip is mounted and electrically connected to the LED chip;
A plurality of circuit patterns that are connected to the LED chip and the circuit pattern on the mounting substrate via solder and are formed along the outer wall of the three-dimensional substrate;
The LED package, wherein the plurality of circuit patterns are respectively formed on a single side surface of the plurality of side surfaces of the three-dimensional substrate.
JP2007040673A 2007-02-15 2007-02-21 LED package Expired - Fee Related JP4687665B2 (en)

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JP2007040673A JP4687665B2 (en) 2007-02-21 2007-02-21 LED package
US12/527,069 US20100032189A1 (en) 2007-02-15 2008-02-08 Led package and attachment structure of molded circuit component
KR1020097016780A KR20090104860A (en) 2007-02-15 2008-02-08 Led package and structure for mounting three-dimensional circuit component
CN200880005314A CN101617412A (en) 2007-02-15 2008-02-08 The mounting structure of LED packaging part and three-dimensional circuit component
PCT/JP2008/052154 WO2008099784A1 (en) 2007-02-15 2008-02-08 Led package and structure for mounting three-dimensional circuit component
EP08711033A EP2110866A4 (en) 2007-02-15 2008-02-08 Led package and structure for mounting three-dimensional circuit component
TW097105404A TW200901512A (en) 2007-02-15 2008-02-15 Led package

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US11820884B2 (en) 2021-07-06 2023-11-21 Hyundai Motor Company Thermoplastic resin composition having high rigidity and low coefficient of linear thermal expansion and molded article comprising same
US11905402B2 (en) 2021-07-06 2024-02-20 Hyundai Motor Company Polyolefin resin composition having high rigidity and low coefficient of linear thermal expansion and weight-reduced automobile part comprising same

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JPH077159U (en) * 1993-06-30 1995-01-31 シャープ株式会社 Optical semiconductor device for surface mounting
JPH11330131A (en) * 1998-05-20 1999-11-30 Rohm Co Ltd Semiconductor device
JP2001177156A (en) * 1999-12-14 2001-06-29 Koha Co Ltd Side emitting led lamp

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH077159U (en) * 1993-06-30 1995-01-31 シャープ株式会社 Optical semiconductor device for surface mounting
JPH11330131A (en) * 1998-05-20 1999-11-30 Rohm Co Ltd Semiconductor device
JP2001177156A (en) * 1999-12-14 2001-06-29 Koha Co Ltd Side emitting led lamp

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11820884B2 (en) 2021-07-06 2023-11-21 Hyundai Motor Company Thermoplastic resin composition having high rigidity and low coefficient of linear thermal expansion and molded article comprising same
US11905402B2 (en) 2021-07-06 2024-02-20 Hyundai Motor Company Polyolefin resin composition having high rigidity and low coefficient of linear thermal expansion and weight-reduced automobile part comprising same

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