JP2008205076A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2008205076A
JP2008205076A JP2007037618A JP2007037618A JP2008205076A JP 2008205076 A JP2008205076 A JP 2008205076A JP 2007037618 A JP2007037618 A JP 2007037618A JP 2007037618 A JP2007037618 A JP 2007037618A JP 2008205076 A JP2008205076 A JP 2008205076A
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rectangle
semiconductor device
resin layer
resin
joined
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JP4582347B2 (en
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Yuzo Neishi
裕三 根石
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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Abstract

<P>PROBLEM TO BE SOLVED: To form a resin layer free from height unevenness, and to form wiring on the resin layer. <P>SOLUTION: Thermosetting resin precursor layers 40 are formed on a surface forming electrodes 14 for a semiconductor substrate 10. Resin layers 20 are formed by curing the resin precursor layers 40 by a heat. Wiring 30 is formed on the resin layers 20 so as to be electrically connected to the electrode 14. The resin precursor layers 40 are formed so as to contain top faces 22 and side faces 23 erected so as to be connected to the top faces 22. The shape of the top face 22 can be divided into a rectangle 24 inscribed to the top face 22 and a projecting section 28 with a plurality of end sections 26 joined with the rectangle 24. A pair of end sections 26 are joined at least both ends of either one side of the rectangle 24. The projecting sections 28 are projected from the side in a width narrower than the length of the side joining a pair of the end sections 26. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

能動面に形成された電極パッド及び樹脂層と、電極パッドの表面から樹脂層の表面にかけて配設された配線と、を備える半導体装置が知られている（特許文献１）。樹脂層とその表面の配線は外部端子を構成している。この外部端子は、ハンダボールで形成する外部端子よりも狭いピッチで形成することができ、樹脂層によって応力の吸収も可能である。図７に示すように、樹脂層９００は、樹脂前駆体層を形成してこれを硬化して形成するが、特に、１つの樹脂層９００に多数の配線を形成できるように長尺状に樹脂前駆体を形成した場合、これを硬化するとその両端部９０２が盛り上がっていた。このような盛り上がった端部９０２及びそれ以外の部分に配線を形成すると、外部端子の高さが不均一になってしまうという問題があった。これを避けるには、同じ高さの部分のみを使用しなければならず、樹脂層９００の一部が無駄になっていた。
特開２００５−３５３９８３号公報 There is known a semiconductor device including an electrode pad and a resin layer formed on an active surface, and wiring disposed from the surface of the electrode pad to the surface of the resin layer (Patent Document 1). The resin layer and the wiring on the surface constitute an external terminal. The external terminals can be formed with a narrower pitch than the external terminals formed of solder balls, and stress can be absorbed by the resin layer. As shown in FIG. 7, the resin layer 900 is formed by forming a resin precursor layer and curing the resin precursor layer. When the precursor was formed, both ends 902 were raised when it was cured. When wiring is formed in such a raised end portion 902 and other portions, there is a problem that the height of the external terminals becomes non-uniform. In order to avoid this, only the part of the same height must be used, and a part of the resin layer 900 was wasted.
JP-A-2005-353983

本発明の目的は、高さの不均一を解消した樹脂層を形成してその上に配線を形成することにある。   An object of the present invention is to form a resin layer in which unevenness in height is eliminated and form wiring thereon.

（１）本発明に係る半導体装置の製造方法は、
半導体基板の電極が形成された面に、熱硬化性の樹脂前駆体層を形成する工程と、
前記樹脂前駆体層に熱を加えて硬化させ、樹脂層を形成する工程と、
前記樹脂層上に、前記電極と電気的に接続する配線を形成する工程と、
を含み、
前記樹脂前駆体層は、前記半導体基板と向かい合う第１の面と、前記第１の面とは反対側の第２の面と、を含むように形成し、
前記第２の面の形状は、前記第２の面に内接する矩形と、前記矩形に接合される複数の端部を有する凸部と、に分けることができ、
前記矩形のいずれかの一辺の少なくとも両端に一対の前記端部が接合し、
前記凸部は、前記一対の端部が接合する前記辺の長さよりも狭い幅で前記辺から突出する。本発明によれば、樹脂層前駆体層には、矩形の一辺から狭い幅で突出するように凸部が形成されており、矩形の一辺から下がる側面よりも、凸部の側面の方が大きい。したがって、樹脂前駆体層を加熱するときに、単位体積当りの表面積が大きいため、熱量が増大するので、硬化前の一時的な軟化が一層進み、高さを低くすることができる。これにより、従来は高くなっていた樹脂層の端部を低くすることができるので、全体的にその高さの不均一を解消することができる。
（２）この半導体装置の製造方法において、
前記矩形は、長方形であって、前記長方形の短辺に前記端部が接合されてもよい。
（３）この半導体装置の製造方法において、
前記凸部は、分岐を形成してもよい。
（４）この半導体装置の製造方法において、
前記樹脂前駆体層を、貫通穴を有するように形成し、
前記凸部を、前記貫通穴の周囲に配置してもよい。
（５）本発明に係る半導体装置は、
集積回路が形成され、前記集積回路に電気的に接続された電極を有する半導体基板と、
前記半導体基板の前記電極が形成された面に形成された樹脂層と、
前記電極に電気的に接続され、前記樹脂層上に形成された配線と、
を有し、
前記樹脂層は、前記半導体基板と向かい合う第１の面と、前記第１の面とは反対側の第２の面と、を含み、
前記第２の面の形状は、前記第２の面に内接する矩形と、前記矩形に接合される複数の端部を有する凸部と、に分けることができ、
前記矩形のいずれかの一辺の少なくとも両端に一対の前記端部が接合し、
前記凸部は、前記一対の端部が接合する前記辺の長さよりも狭い幅で前記辺から突出する。本発明によれば、樹脂層は、中間部と端部の高さが異なっているとしても、上面が矩形になった部分と、上面が矩形に接続される凸部である部分と、に明確に分けられるのでその区別が容易であり、上面が矩形になった部分の全体を、配線の支持層として利用することができる。
（６）この半導体装置において、
前記矩形は、長方形であって、前記長方形の短辺に前記端部が接合されてもよい。
（７）この半導体装置において、
前記凸部は、分岐を形成してもよい。
（８）この半導体装置において、
前記樹脂層は、貫通穴を有し、
前記凸部は、前記貫通穴の周囲に配置されてもよい。 (1) A method of manufacturing a semiconductor device according to the present invention includes:
Forming a thermosetting resin precursor layer on the surface of the semiconductor substrate on which the electrodes are formed;
A step of applying heat to the resin precursor layer to cure and forming a resin layer;
Forming a wiring electrically connected to the electrode on the resin layer;
Including
The resin precursor layer is formed to include a first surface facing the semiconductor substrate and a second surface opposite to the first surface,
The shape of the second surface can be divided into a rectangle inscribed in the second surface and a convex portion having a plurality of ends joined to the rectangle,
A pair of the end portions are joined to at least both ends of one side of the rectangle,
The convex portion protrudes from the side with a width narrower than the length of the side where the pair of end portions are joined. According to the present invention, the resin layer precursor layer has a convex portion that protrudes with a narrow width from one side of the rectangle, and the side surface of the convex portion is larger than the side surface that descends from one side of the rectangle. . Accordingly, since the surface area per unit volume is large when the resin precursor layer is heated, the amount of heat increases, so that temporary softening before curing further proceeds and the height can be lowered. Thereby, since the edge part of the resin layer which was conventionally high can be made low, the nonuniformity of the height can be eliminated as a whole.
(2) In this method of manufacturing a semiconductor device,
The rectangle may be a rectangle, and the end may be joined to a short side of the rectangle.
(3) In this method of manufacturing a semiconductor device,
The convex portion may form a branch.
(4) In this method of manufacturing a semiconductor device,
Forming the resin precursor layer to have a through hole;
The convex portion may be arranged around the through hole.
(5) A semiconductor device according to the present invention includes:
A semiconductor substrate having an electrode formed thereon and electrically connected to the integrated circuit;
A resin layer formed on the surface of the semiconductor substrate on which the electrodes are formed;
A wiring electrically connected to the electrode and formed on the resin layer;
Have
The resin layer includes a first surface facing the semiconductor substrate, and a second surface opposite to the first surface,
The shape of the second surface can be divided into a rectangle inscribed in the second surface and a convex portion having a plurality of ends joined to the rectangle,
A pair of the end portions are joined to at least both ends of one side of the rectangle,
The convex portion protrudes from the side with a width narrower than the length of the side where the pair of end portions are joined. According to the present invention, the resin layer is clearly divided into a portion where the top surface is rectangular and a portion where the top surface is a convex portion connected to the rectangle even if the height of the intermediate portion and the end portion are different. Therefore, the distinction is easy, and the entire portion having a rectangular upper surface can be used as a wiring support layer.
(6) In this semiconductor device,
The rectangle may be a rectangle, and the end may be joined to a short side of the rectangle.
(7) In this semiconductor device,
The convex portion may form a branch.
(8) In this semiconductor device,
The resin layer has a through hole,
The convex portion may be disposed around the through hole.

（第１の実施の形態）
図１（Ａ）は、本発明の第１の実施の形態に係る半導体装置を示す平面図であり、図１（Ｂ）は、半導体装置の、図１（Ａ）に示すＩＢ−ＩＢ線断面の一部を示す拡大図である。半導体装置は、半導体基板１０を有する。半導体基板１０は、図１（Ａ）に示す最終製品としての半導体装置においては半導体チップであるが、最終製品を得る前の段階では、半導体ウエハである。半導体ウエハを切断して半導体チップが得られる。半導体基板１０には、集積回路１２（半導体チップには１つの集積回路１２／半導体ウエハには複数の集積回路１２）が形成されている。半導体基板１０は、内部配線（図示せず）を介して集積回路１２に電気的に接続された電極１４を有する。図１（Ａ）の例では、半導体基板１０が一方向に長い形状（平面形状が長方形）であって、長い方の辺に沿って、複数の電極１４が配列されている。半導体基板１０には、電極１４の少なくとも一部が露出する様にパッシベーション膜１６が形成されている。パッシベーション膜１６は、例えば、ＳｉＯ２やＳｉＮ等の無機材料のみで形成されていてもよい。 (First embodiment)
FIG. 1A is a plan view showing a semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view of the semiconductor device taken along line IB-IB shown in FIG. It is an enlarged view which shows a part of. The semiconductor device has a semiconductor substrate 10. The semiconductor substrate 10 is a semiconductor chip in the semiconductor device as the final product shown in FIG. 1A, but is a semiconductor wafer in a stage before obtaining the final product. A semiconductor chip is obtained by cutting the semiconductor wafer. An integrated circuit 12 (one integrated circuit 12 for a semiconductor chip / a plurality of integrated circuits 12 for a semiconductor wafer) is formed on the semiconductor substrate 10. The semiconductor substrate 10 has an electrode 14 that is electrically connected to the integrated circuit 12 via internal wiring (not shown). In the example of FIG. 1A, the semiconductor substrate 10 has a shape that is long in one direction (planar shape is rectangular), and a plurality of electrodes 14 are arranged along the longer side. A passivation film 16 is formed on the semiconductor substrate 10 so that at least a part of the electrode 14 is exposed. The passivation film 16 may be formed of only an inorganic material such as SiO 2 or SiN.

図２は、本発明の第１の実施の形態に係る半導体装置の樹脂層の一部を拡大した平面図である。半導体基板１０の電極１４が形成された面（パッシベーション膜１６上）には、樹脂層２０が形成されている。例えば樹脂層２０の材料としては、ポリイミド樹脂、シリコーン変性ポリイミド樹脂、エポキシ樹脂、シリコーン変性エポキシ樹脂、ベンゾシクロブテン（ＢＣＢ；benzocyclobutene）、ポリベンゾオキサゾール（ＰＢＯ；polybenzoxazole）、フェノール系樹脂等の樹脂を用いてもよい。樹脂層２０の形状は、半導体基板１０と向かい合う下面と、下面とは反対側の上面２２と、を含む。上面２２の形状は、上面２２に内接する矩形２４（例えば長方形）と、矩形２４（例えば長方形の短辺）に接合される複数の端部２６を有する凸部２８と、に分けることができる。「上面２２に内接する矩形２４」とは、上面２２の中心から輪郭に接するまで拡大して得られた矩形であって最大面積を有するものをいう。また、上面２２の形状とは、図１（Ａ）のように半導体基板１０及び樹脂層２０を平面図であらわした際の、樹脂層２０の形状を指す。矩形２４のいずれかの一辺（図２では左右端の縦辺）の少なくとも両端（図２は上下の両端）に一対の端部２６が接合している。凸部２８は分岐を形成している。凸部２８は、一対の端部２６が接合する辺（図２では矩形２４の左右端の縦辺）の長さよりも狭い幅でその辺から突出する。   FIG. 2 is an enlarged plan view of a part of the resin layer of the semiconductor device according to the first embodiment of the present invention. A resin layer 20 is formed on the surface of the semiconductor substrate 10 on which the electrode 14 is formed (on the passivation film 16). For example, the material of the resin layer 20 includes resins such as polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO), and phenolic resin. It may be used. The shape of the resin layer 20 includes a lower surface facing the semiconductor substrate 10 and an upper surface 22 opposite to the lower surface. The shape of the upper surface 22 can be divided into a rectangle 24 (for example, a rectangle) inscribed in the upper surface 22 and a convex portion 28 having a plurality of end portions 26 joined to the rectangle 24 (for example, a short side of the rectangle). The “rectangle 24 inscribed in the upper surface 22” refers to a rectangle obtained by enlarging from the center of the upper surface 22 until it touches the contour and having the maximum area. Further, the shape of the upper surface 22 refers to the shape of the resin layer 20 when the semiconductor substrate 10 and the resin layer 20 are shown in a plan view as shown in FIG. A pair of end portions 26 are joined to at least both ends (upper and lower ends in FIG. 2) of any one side of the rectangle 24 (the vertical sides at the left and right ends in FIG. 2). The convex portion 28 forms a branch. The convex portion 28 protrudes from the side with a width narrower than the length of the side where the pair of end portions 26 are joined (the vertical sides at the left and right ends of the rectangle 24 in FIG. 2).

樹脂層２０上には配線３０が形成されている。配線３０は、電極１４上で電極１４に電気的に接続している。配線３０と電極１４は直接接触していてもよいし、両者間に導電膜（図示せず）が介在していてもよい。配線３０は、電極１４から樹脂層２０上に延びている。配線３０は、電極１４と樹脂層２０の間でパッシベーション膜１６の表面に接触している。配線３０は、樹脂層２０の、電極１４とは反対側の端部２６を越えて、パッシベーション膜１６上に至るように形成されていてもよい。   A wiring 30 is formed on the resin layer 20. The wiring 30 is electrically connected to the electrode 14 on the electrode 14. The wiring 30 and the electrode 14 may be in direct contact, or a conductive film (not shown) may be interposed therebetween. The wiring 30 extends from the electrode 14 onto the resin layer 20. The wiring 30 is in contact with the surface of the passivation film 16 between the electrode 14 and the resin layer 20. The wiring 30 may be formed so as to extend over the passivation film 16 beyond the end portion 26 of the resin layer 20 on the side opposite to the electrode 14.

本実施の形態によれば、樹脂層２０は、中間部（矩形２４に対応する部分）と端部（凸部２８に対応する部分）の高さが異なっているとしても、上面２２が矩形２４になった部分と、上面２２が矩形２４に接続される凸部２８である部分と、に明確に分けられるのでその区別が容易であり、矩形２４に対応する部分の全体を、配線３０の支持層として利用することができる。   According to the present embodiment, even if the resin layer 20 has different heights at the intermediate portion (the portion corresponding to the rectangle 24) and the end portion (the portion corresponding to the convex portion 28), the upper surface 22 has the rectangular shape 24. And the portion where the upper surface 22 is the convex portion 28 connected to the rectangle 24 is clearly divided, so that the distinction is easy, and the entire portion corresponding to the rectangle 24 is supported by the wiring 30. Can be used as a layer.

図３（Ａ）は、本発明の第１の実施の形態に係る樹脂前駆体層の形成工程を示す平面図であり、図３（Ｂ）は、樹脂前駆体層の、図３（Ａ）に示すIIIＢ−IIIＢ線断面図である。   FIG. 3A is a plan view showing a resin precursor layer forming step according to the first embodiment of the present invention, and FIG. 3B is a diagram of the resin precursor layer shown in FIG. It is a IIIB-IIIB sectional view taken on the line.

半導体装置の製造方法では、半導体基板１０の電極１４が形成された面に、例えばポリイミド樹脂前駆体からなる熱硬化性の樹脂前駆体層４０を形成する。樹脂前駆体層４０は、半導体基板１０と向かい合う下面と、下面とは反対側の上面４２と、上面４２に接続されるように立ち上がる側面４３と、を含むように形成する。上面４２の形状は、上面４２に内接する矩形４４（例えば長方形）と、矩形４４（例えば長方形の短辺）に接合される複数の端部４６を有する凸部４８と、に分けることができる。矩形４４のいずれかの一辺の少なくとも両端に一対の端部４６が接合している。凸部４８は、分岐を形成している。凸部４８は、一対の端部４６が接合する、矩形４４の一辺の長さよりも狭い幅で辺から突出する。   In the method for manufacturing a semiconductor device, a thermosetting resin precursor layer 40 made of, for example, a polyimide resin precursor is formed on the surface of the semiconductor substrate 10 on which the electrodes 14 are formed. The resin precursor layer 40 is formed so as to include a lower surface facing the semiconductor substrate 10, an upper surface 42 opposite to the lower surface, and a side surface 43 rising so as to be connected to the upper surface 42. The shape of the upper surface 42 can be divided into a rectangle 44 (for example, a rectangle) inscribed in the upper surface 42 and a convex portion 48 having a plurality of end portions 46 joined to the rectangle 44 (for example, a short side of the rectangle). A pair of end portions 46 are joined to at least both ends of one side of the rectangle 44. The convex portion 48 forms a branch. The convex portion 48 projects from the side with a width narrower than the length of one side of the rectangle 44 to which the pair of end portions 46 are joined.

図４は、図３（Ｂ）に示す樹脂前駆体層から形成された樹脂層を示す図である。樹脂前駆体層４０を熱によって硬化して樹脂層２０を形成する。樹脂前駆体が熱によって化学反応（重合反応・架橋反応）し、硬化して樹脂になる。樹脂前駆体は、硬化前には、熱によって一時的に軟化する。本実施の形態によれば、樹脂前駆体層４０には、矩形４４の一辺（短辺）から狭い幅で突出するように凸部４８が形成されており、従来技術のような矩形４４の一辺（短辺）から下がる側面よりも、凸部４８の側面の方が大きい。したがって、樹脂前駆体層４０を加熱するときに、単位体積当りの表面積が大きいために熱量が増大するので、硬化前の一時的な軟化が一層進み、高さを低くすることができる。これにより、従来は高くなっていた樹脂層２０の端部２６を、高くならないようにすることができるので、全体的にその高さの不均一を解消することができる。   FIG. 4 is a view showing a resin layer formed from the resin precursor layer shown in FIG. The resin precursor layer 40 is cured by heat to form the resin layer 20. The resin precursor undergoes a chemical reaction (polymerization reaction / crosslinking reaction) by heat and is cured to become a resin. The resin precursor is temporarily softened by heat before curing. According to the present embodiment, the resin precursor layer 40 is formed with the convex portion 48 so as to protrude from one side (short side) of the rectangle 44 with a narrow width, and one side of the rectangle 44 as in the prior art. The side surface of the convex portion 48 is larger than the side surface descending from the (short side). Therefore, when the resin precursor layer 40 is heated, the amount of heat increases because the surface area per unit volume is large, so that temporary softening before curing further proceeds and the height can be lowered. Thereby, since the end part 26 of the resin layer 20 that has been conventionally high can be prevented from becoming high, unevenness in the height can be eliminated as a whole.

そして、図１（Ａ）に示すように、電極１４に電気的に接続するように樹脂層２０上に配線３０を形成する。その他の詳細は、上述した半導体装置の構造から自明な製造方法であるため説明を省略する。   Then, as shown in FIG. 1A, a wiring 30 is formed on the resin layer 20 so as to be electrically connected to the electrode 14. Since other details are a manufacturing method that is obvious from the structure of the semiconductor device described above, description thereof is omitted.

（第２の実施の形態）
図５は、本発明の第２の実施の形態に係る半導体装置を示す平面図であり、図６は、樹脂層の拡大図である。本実施の形態で、樹脂層６０は、貫通穴６２を有する。貫通穴６２は、樹脂層６０の端部に形成されている。樹脂層６０の上面７２の形状は、上面７２に内接する矩形７４と、矩形７４に接合される複数の端部７６を有する凸部７８と、に分けることができる。矩形７４は、貫通穴６２に接する。凸部７８は、貫通穴６２の周囲に配置されている。構成について、その他の詳細は、第１の実施の形態で説明した内容が該当する。本実施の形態でも第１の実施の形態で説明した効果を達成することができる。 (Second Embodiment)
FIG. 5 is a plan view showing a semiconductor device according to the second embodiment of the present invention, and FIG. 6 is an enlarged view of a resin layer. In the present embodiment, the resin layer 60 has a through hole 62. The through hole 62 is formed at the end of the resin layer 60. The shape of the upper surface 72 of the resin layer 60 can be divided into a rectangle 74 inscribed in the upper surface 72 and a convex portion 78 having a plurality of end portions 76 joined to the rectangle 74. The rectangle 74 is in contact with the through hole 62. The convex part 78 is arranged around the through hole 62. Regarding the configuration, the details described in the first embodiment correspond to the other details. The effects described in the first embodiment can also be achieved in this embodiment.

本実施の形態に係る半導体装置の製造方法では、樹脂層６０の形状に対応するように樹脂前駆体層を形成する。製造方法について、その他の詳細は、第１の実施の形態で説明した内容が該当する。本実施の形態でも第１の実施の形態で説明した効果を達成することができる。   In the semiconductor device manufacturing method according to the present embodiment, the resin precursor layer is formed so as to correspond to the shape of the resin layer 60. Regarding the manufacturing method, the details described in the first embodiment correspond to the other details. The effects described in the first embodiment can also be achieved in this embodiment.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。   The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

図１（Ａ）は、本発明の第１の実施の形態に係る半導体装置を示す平面図であり、図１（Ｂ）は、半導体装置の、図１（Ａ）に示すＩＢ−ＩＢ線断面の一部を示す拡大図である。FIG. 1A is a plan view showing a semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view of the semiconductor device taken along line IB-IB shown in FIG. It is an enlarged view which shows a part of. 図２は、本発明の第１の実施の形態に係る半導体装置の樹脂層の拡大平面図である。FIG. 2 is an enlarged plan view of a resin layer of the semiconductor device according to the first embodiment of the present invention. 図３（Ａ）は、本発明の第１の実施の形態に係る樹脂前駆体層の形成工程を示す平面図であり、図３（Ｂ）は、樹脂前駆体層の、図３（Ａ）に示すIIIＢ−IIIＢ線断面図である。FIG. 3A is a plan view showing a resin precursor layer forming step according to the first embodiment of the present invention, and FIG. 3B is a diagram of the resin precursor layer shown in FIG. It is a IIIB-IIIB sectional view taken on the line. 図４は、図３（Ｂ）に示す樹脂前駆体層から形成された樹脂層を示す図である。FIG. 4 is a view showing a resin layer formed from the resin precursor layer shown in FIG. 図５は、本発明の第２の実施の形態に係る半導体装置を示す平面図である。FIG. 5 is a plan view showing a semiconductor device according to the second embodiment of the present invention. 図６は、図５に示す樹脂層の拡大図である。FIG. 6 is an enlarged view of the resin layer shown in FIG. 図７は、従来技術に係る樹脂層を示す断面図である。FIG. 7 is a cross-sectional view showing a resin layer according to the prior art.

符号の説明Explanation of symbols

１０…半導体基板、 １２…集積回路、 １４…電極、 １６…パッシベーション膜、 ２０…樹脂層、 ２２…上面、 ２４…矩形、 ２６…端部、 ２８…凸部、 ３０…配線、 ４０…樹脂前駆体層、 ４２…上面、 ４４…矩形、 ４６…端部、 ４８…凸部、 ６０…樹脂層、 ６２…貫通穴、 ７２…上面、 ７４…矩形、 ７６…端部、 ７８…凸部   DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 12 ... Integrated circuit, 14 ... Electrode, 16 ... Passivation film, 20 ... Resin layer, 22 ... Top surface, 24 ... Rectangular, 26 ... End part, 28 ... Convex part, 30 ... Wiring, 40 ... Resin precursor Body layer 42... Upper surface 44. Rectangle 46. End portion 48. Projection portion 60. Resin layer 62. Through hole 72. Upper surface 74. Rectangular shape 76 ... End portion 78 ... Projection portion

Claims (8)

半導体基板の電極が形成された面に、熱硬化性の樹脂前駆体層を形成する工程と、
前記樹脂前駆体層に熱を加えて硬化させ、樹脂層を形成する工程と、
前記樹脂層上に、前記電極と電気的に接続する配線を形成する工程と、
を含み、
前記樹脂前駆体層は、前記半導体基板と向かい合う第１の面と、前記第１の面とは反対側の第２の面と、を含むように形成し、
前記第２の面の形状は、前記第２の面に内接する矩形と、前記矩形に接合される複数の端部を有する凸部と、に分けることができ、
前記矩形のいずれかの一辺の少なくとも両端に一対の前記端部が接合し、
前記凸部は、前記一対の端部が接合する前記辺の長さよりも狭い幅で前記辺から突出する半導体装置の製造方法。 Forming a thermosetting resin precursor layer on the surface of the semiconductor substrate on which the electrodes are formed;
A step of applying heat to the resin precursor layer to cure and forming a resin layer;
Forming a wiring electrically connected to the electrode on the resin layer;
Including
The resin precursor layer is formed to include a first surface facing the semiconductor substrate and a second surface opposite to the first surface,
The shape of the second surface can be divided into a rectangle inscribed in the second surface and a convex portion having a plurality of ends joined to the rectangle,
A pair of the end portions are joined to at least both ends of one side of the rectangle,
The method of manufacturing a semiconductor device, wherein the convex portion protrudes from the side with a width narrower than a length of the side to which the pair of end portions are joined. 請求項１に記載された半導体装置の製造方法において、
前記矩形は、長方形であって、前記長方形の短辺に前記端部が接合されてなる半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the rectangle is a rectangle, and the end portion is bonded to a short side of the rectangle. 請求項１又は２に記載された半導体装置の製造方法において、
前記凸部は、分岐を形成してなる半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the convex portion forms a branch. 請求項１又は２に記載された半導体装置の製造方法において、
前記樹脂前駆体層を、貫通穴を有するように形成し、
前記凸部を、前記貫通穴の周囲に配置する半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1 or 2,
Forming the resin precursor layer to have a through hole;
The manufacturing method of the semiconductor device which arrange | positions the said convex part around the said through-hole. 集積回路が形成され、前記集積回路に電気的に接続された電極を有する半導体基板と、
前記半導体基板の前記電極が形成された面に形成された樹脂層と、
前記電極に電気的に接続され、前記樹脂層上に形成された配線と、
を有し、
前記樹脂層は、前記半導体基板と向かい合う第１の面と、前記第１の面とは反対側の第２の面と、を含み、
前記第２の面の形状は、前記第２の面に内接する矩形と、前記矩形に接合される複数の端部を有する凸部と、に分けることができ、
前記矩形のいずれかの一辺の少なくとも両端に一対の前記端部が接合し、
前記凸部は、前記一対の端部が接合する前記辺の長さよりも狭い幅で前記辺から突出する半導体装置。 A semiconductor substrate having an electrode formed thereon and electrically connected to the integrated circuit;
A resin layer formed on the surface of the semiconductor substrate on which the electrodes are formed;
A wiring electrically connected to the electrode and formed on the resin layer;
Have
The resin layer includes a first surface facing the semiconductor substrate, and a second surface opposite to the first surface,
The shape of the second surface can be divided into a rectangle inscribed in the second surface and a convex portion having a plurality of ends joined to the rectangle,
A pair of the end portions are joined to at least both ends of one side of the rectangle,
The convex portion is a semiconductor device that protrudes from the side with a width narrower than the length of the side to which the pair of end portions are joined. 請求項５に記載された半導体装置において、
前記矩形は、長方形であって、前記長方形の短辺に前記端部が接合されてなる半導体装置。 The semiconductor device according to claim 5,
The said rectangle is a rectangle, Comprising: The said edge part is joined to the short side of the said rectangle, The semiconductor device. 請求項５又は６に記載された半導体装置において、
前記凸部は、分岐を形成してなる半導体装置。 The semiconductor device according to claim 5 or 6,
The convex portion is a semiconductor device formed by forming a branch. 請求項５又は６に記載された半導体装置において、
前記樹脂層は、貫通穴を有し、
前記凸部は、前記貫通穴の周囲に配置されてなる半導体装置。 The semiconductor device according to claim 5 or 6,
The resin layer has a through hole,
The convex portion is a semiconductor device arranged around the through hole.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005353983A (en) * 2004-06-14 2005-12-22 Seiko Epson Corp Semiconductor device, circuit board, electrooptic device, and electronic device
JP2006191141A (en) * 2006-03-08 2006-07-20 Seiko Epson Corp Semiconductor device
JP2006196570A (en) * 2005-01-12 2006-07-27 Seiko Epson Corp Semiconductor device, method for manufacturing the same, circuit board, electro-optical device, and electronic apparatus
JP2007027208A (en) * 2005-07-12 2007-02-01 Seiko Epson Corp Method of manufacturing semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005353983A (en) * 2004-06-14 2005-12-22 Seiko Epson Corp Semiconductor device, circuit board, electrooptic device, and electronic device
JP2006196570A (en) * 2005-01-12 2006-07-27 Seiko Epson Corp Semiconductor device, method for manufacturing the same, circuit board, electro-optical device, and electronic apparatus
JP2007027208A (en) * 2005-07-12 2007-02-01 Seiko Epson Corp Method of manufacturing semiconductor device
JP2006191141A (en) * 2006-03-08 2006-07-20 Seiko Epson Corp Semiconductor device

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