JP2008198691A - Nitride semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor device capable of preventing current collapse. <P>SOLUTION: A buffer layer (GaN) 12, a channel layer (GaN) 13, a carrier supply layer (n-AlGaN) 14 and a Schottky layer (AlGaN) 15 are sequentially laminated on a sapphire substrate 11, and a cap layer (GaN) 16 is laminated on the Schottky layer 15. The cap layer 16 is of a polycrystalline structure in which a half width of an X-ray diffraction rocking curve on a (004) plane is within an angle range of 4,000-12,000 seconds. This cap layer 16 reduces electrons trapped in a surface level or surface level density of the cap layer 16. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nitride semiconductor device using a group III-V nitride semiconductor as an active layer, and in particular, a high electron mobility transistor (HEMT), a field effect transistor (FET), and the like. The present invention relates to a nitride semiconductor device having a protective film on its surface.

  FIG. 6 shows a cross-sectional view of a conventional nitride semiconductor device using a group III-V nitride semiconductor. The nitride semiconductor device shown in FIG. 6 has a so-called HEMT structure, on a substrate 21 made of a sapphire substrate, a buffer layer 22 made of non-doped gallium nitride (GaN), and a channel made of non-doped gallium nitride (GaN). The layer 23, the carrier supply layer 24 made of n-type aluminum gallium nitride (AlGaN), and the Schottky layer 25 made of non-doped aluminum gallium nitride (AlGaN) are sequentially stacked. The channel layer 23 and the carrier supply layer A two-dimensional electron gas layer consisting of a potential well and having a very high electron mobility is formed in the vicinity of the heterojunction interface with 24. In the nitride semiconductor device having such a structure, by controlling the voltage applied to the gate electrode 27 (control electrode) in Schottky contact with the Schottky layer 25, carriers flowing between the source electrode 28 and the drain electrode 29 (2 Dimensional electron gas).

For this type of nitride semiconductor device, various structures as disclosed in, for example, Patent Document 1 have been proposed in addition to the above structure.
Japanese Patent Laid-Open No. 10-335637

  However, in a semiconductor device in which a gate electrode is formed on a nitride semiconductor layer such as an aluminum gallium nitride (AlGaN) layer or a gallium nitride (GaN) layer, electrons trapped in the surface level of the nitride semiconductor layer Phenomenon in which drain current decreases due to fluctuations in surface potential during quasi-static operation with high drain voltage (linear operation with small signals such as RF signals and pulse signals) (hereinafter referred to as current collapse) There was a problem that occurred.

  An object of the present invention is to provide a nitride semiconductor device provided with a surface protective film so that current collapse can be suppressed.

In order to achieve the above object, a nitride semiconductor device according to the first aspect of the present invention includes a group III element consisting of at least one of the group consisting of gallium, aluminum, boron, and indium, nitrogen, phosphorus, and A nitride semiconductor device comprising a group III-V nitride semiconductor layer composed of a group V element containing at least nitrogen in the group consisting of arsenic, comprising the group III-V nitride semiconductor layer stacked on a substrate. A first nitride semiconductor layer, a second nitride semiconductor layer made of the group III-V nitride semiconductor layer not containing aluminum and laminated on the first nitride semiconductor layer; A control electrode that is in Schottky contact with the nitride semiconductor layer, and the second nitride semiconductor layer has an angle range in which a half width of an X-ray diffraction rocking curve on the (004) plane is 4000 seconds to 12000 seconds Characterized in that it is a polycrystalline structure included.
According to a second aspect of the present invention, there is provided a nitride semiconductor device comprising at least one group III element selected from the group consisting of gallium, aluminum, boron, and indium, and at least one selected from the group consisting of nitrogen, phosphorus, and arsenic. In a nitride semiconductor device including a group III-V nitride semiconductor layer composed of a group V element containing nitrogen, a first nitride semiconductor layer including the group III-V nitride semiconductor layer stacked on a substrate; A second nitride semiconductor layer made of the group III-V nitride semiconductor layer not containing aluminum and formed on the first nitride semiconductor layer, and the second nitride semiconductor layer formed on the second nitride semiconductor layer. A control electrode in Schottky contact with the first nitride semiconductor layer from the recess, and the second nitride semiconductor layer has an X-ray diffraction rocking curve half-value width of 4000 seconds to 120 in the (004) plane. Characterized in that it is a multi-crystal structure of the angle range of 0 seconds.
According to a third aspect of the present invention, in the nitride semiconductor device according to the first or second aspect, a source electrode and a drain electrode that are in ohmic contact with the second nitride semiconductor layer are disposed so as to sandwich the control electrode. It is characterized by that.

According to the nitride semiconductor device of the present invention, the surface of the second nitride semiconductor layer having a polycrystalline structure defined by the full width at half maximum of the rocking curve obtained by X-ray diffraction (angle range of 4000 seconds to 12000 seconds) is protected. By forming a film, the electron trapped in the surface level of the surface protective film or the density of the surface level can be reduced, and the current collapse phenomenon can occur even during quasi-static operation at a high drain voltage. It is suppressed and the high frequency characteristics are improved.
In addition, according to the nitride semiconductor device of the present invention, the polycrystalline structure can be controlled by controlling normal film formation conditions (film formation temperature, V / III ratio, growth rate, etc.) in a normal nitride semiconductor device manufacturing process. Since the second nitride semiconductor layer can be formed, a nitride semiconductor device with good controllability of the manufacturing process and excellent characteristics can be manufactured with a high yield.

  Hereinafter, the nitride semiconductor device of the present invention will be described in detail by taking a HEMT as a group III-V nitride semiconductor device as an example.

<First embodiment>
FIG. 1 shows a sectional view of a HEMT which is a group III-V nitride semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1, the nitride semiconductor device of the present embodiment has a buffer layer 12 made of non-doped gallium nitride (GaN) having a thickness of about 30 nm on a substrate 11 made of sapphire, and energy of a carrier supply layer to be described later. A channel layer 13 made of non-doped gallium nitride (GaN) having an energy gap smaller than the gap and having a thickness of 2 μm, and a two-dimensional electron gas layer serving as a carrier at the interface with the channel layer 13 are formed. Carrier supply layer 14 made of aluminum gallium nitride (AlGaN), Schottky layer 15 made of 3 nm thick non-doped aluminum gallium nitride (AlGaN), cap made of 10 nm thick non-doped gallium nitride (GaN) serving as a surface protective film The layers 16 are sequentially stacked.

  The buffer layer 12, the channel layer 13, the carrier supply layer 14, and the Schottky layer 15 constitute the first nitride semiconductor layer of the claims, and the cap layer 16 constitutes the second nitride semiconductor layer of the claims.

  A gate electrode 17 composed of a nickel (Ni) / gold (Au) laminate having nickel (Ni) as a base layer is formed in the gate electrode formation scheduled region on the cap layer 16. Schottky contact is formed. Further, the source electrode and drain electrode formation scheduled regions on the cap layer 16 are made of a laminate of titanium (Ti) / aluminum (Al) / titanium (Ti) / gold (Au) with titanium (Ti) as an underlayer. The source electrode 18 and the drain electrode 19 are formed, and ohmic contact is formed between the cap layer 16 and the source electrode 18 and the drain electrode 19, respectively. The ohmic contact is a very low resistance contact.

  The cap layer 16 serving as a surface protective film is formed by using a MOCVD (metal organic chemical vapor deposition) method, an MBE (electron beam epitaxial) method, or the like under conditions such as a growth temperature, a growth rate, and a V / III ratio. By adjusting, the crystallinity (crystal structure) can be adjusted.

  Since the cap layer 16 to be formed on the Schottky layer 15 described in FIG. 1 is a thin film having a thickness of about 10 nm, it is difficult to directly evaluate the cap layer 16. A thick film is formed under the various film formation conditions described above, and its crystallinity is evaluated.

  FIG. 2 shows (004) plane X-ray diffraction when 1 μm gallium nitride (GaN) is deposited on the C plane of the sapphire substrate (plane perpendicular to the c-axis of the hexagonal crystal) by MOCVD under various deposition conditions. The rocking curve at is shown. In FIG. 2, the vertical axis represents the X-ray diffraction intensity, and the horizontal axis represents the X-ray incident angle. The rocking curve is measured by rotating only the sapphire substrate with the thick X-ray film fixed to the direction of the incident X-ray and the detector. The peak width of the obtained characteristic curve is the fluctuation of the surface orientation. It is proportional to the degree (mosaic degree). That is, the larger the peak width, the worse the crystallinity.

  Therefore, this peak width is represented by a half-value width (FWHM: an angle width of a half value of the peak value). In FIG. 2, the thick film of characteristic A has a half width of 600 seconds, the thick film of characteristic B is 2100 seconds, the thick film of characteristic C is 4000 seconds, the thick film of characteristic D is 12000 seconds, and the thick film of characteristic E is 12000. More than a second. Although the thick film having the characteristic A is a single crystal, the thick film having the characteristics B to D is polycrystalline, and the thick film having the characteristic E is amorphous.

  3A and 3B show drain current-voltage characteristics of the HEMT that is the nitride semiconductor device having the structure shown in FIG. 1 by DC measurement and pulse measurement. In the pulse measurement, a pulse having a pulse width of 10 ms, a pulse period of 100 ms, and a duty of 10% was applied. Here, a plurality of gate voltages are described.

  FIGS. 3A and 3B show a plurality of half-layers in which the gallium nitride (GaN) cap layer 16 of the nitride semiconductor device of FIG. 1 is formed on the Schottky layer 15 under the same film formation conditions as those for collecting characteristics in FIG. It experimented about the thing of a value range (FWHM), The half value width is 600 second, 2100 second, 4000 second, and 12000 second. In (a) and (b) when the full width at half maximum of the cap layer 16 is 600 seconds and 2100 seconds, the drain current is decreased by pulse measurement as compared with DC measurement, and the characteristics are deteriorated due to current collapse. I understand. On the other hand, in (c) and (d) when the half-value width is 4000 seconds and 12000 seconds, the drain current in DC measurement and pulse measurement shows almost the same characteristics, and current collapse is suppressed. I understand.

  In the drain current-voltage characteristics of FIGS. 3A and 3B, FIG. 4 shows the correlation between the pulse ratio of the maximum drain current at the drain voltage of 10 V, the current ratio of DC measurement, and the half width. When the cap layer 16 is formed under the film forming conditions that satisfy the angle range of the full width at half maximum of 4000 seconds or more and 12000 seconds or less, the current of 95% or more is maintained, and the cap layer 16 that satisfies this half width is satisfied. It can be seen that the effect of suppressing current collapse is greatly increased by using.

  From the above, as the cap layer 16 in FIG. 1, a thin film having a polycrystalline structure exhibiting a characteristic curve included in an angular range having a half width of 4000 seconds or more and 12000 seconds or less is a III-V group nitride film. It is desirable to form a film with a film thickness of about 10 nm under film formation conditions. The growth conditions that can be adjusted include growth temperature, V / III ratio, growth rate, and the like. In the case of the growth temperature, it is lower than the temperature at which the other films (13 to 15) are formed (about 1000 ° C., which is the temperature for forming a single crystal), for example, the growth temperature is 600 ° C., 550 ° C., 500 By decreasing the temperature to ° C., the full width at half maximum increases to 2100 seconds, 4000 seconds, and 12000 seconds. Note that the half width can also be increased by lowering the V / III ratio or increasing the growth rate.

<Second embodiment>
FIG. 5 shows a cross section of a HEMT which is a III-V nitride semiconductor device according to the second embodiment of the present invention. As shown in FIG. 5, the nitride semiconductor device has a buffer layer 12 made of non-doped gallium nitride (GaN) having a thickness of about 30 nm on a substrate 11 made of sapphire, and smaller than the energy gap of a carrier supply layer described later. A channel layer 13 made of non-doped gallium nitride (GaN) having an energy gap and a thickness of 2 μm, and an n-type aluminum gallium nitride having a thickness of 15 nm forming a two-dimensional electron gas layer serving as a carrier at the interface with the channel layer 13 A carrier supply layer 14 made of (AlGaN), a Schottky layer 15 made of non-doped aluminum gallium nitride (AlGaN) having a thickness of 3 nm, and a cap layer 16 made of non-doped gallium nitride (GaN) serving as a surface protective film having a thickness of 10 nm. The layers are sequentially stacked.

  In this embodiment, the gate electrode formation region of the cap layer 16 is removed by etching to form a recess, and titanium (Ti) / titanium (Ti) / underlayer is formed on the Schottky layer 15 exposed on the surface of the recess. A gate electrode 17A made of a platinum (Pt) / gold (Au) laminate or a nickel (Ni) / gold (Au) laminate having an underlying layer of nickel (Ni) is formed, and between the Schottky layer 15 A Schottky contact is formed. On the cap layer 16, a source electrode 18A made of titanium (Ti) / aluminum (Al) / titanium (Ti) / gold (Au) with titanium (Ti) in ohmic contact with the cap layer 16 as an underlayer. The drain electrode 19A is formed.

  As in the first embodiment, the cap layer 16 as the surface protective film has an angle range in which the full width at half maximum (FWHM) of the rocking curve in the (004) plane X-ray diffraction is 4000 seconds or more and 12000 seconds or less. The film is formed with a film thickness of about 10 nm under the film forming conditions for forming the included III-V group nitride semiconductor layer having a polycrystalline structure. Also in the group III-V nitride semiconductor device shown in the present embodiment, current collab can be suppressed as in the first embodiment.

<Other examples>
In the first and second embodiments described above, the cap layer 16 of gallium nitride (GaN) is non-doped. However, in order to control crystallinity, iron (Fe), magnesium (Mg), carbon ( C) or the like may be added. In addition, as a group III element of a group III-V nitride semiconductor, an element including at least one of the group consisting of gallium (Ga), aluminum (Al), boron (B), and indium (In) is used. As the group V element, at least one element containing at least nitrogen in the group consisting of nitrogen (N), phosphorus (P), and arsenic (As) is used. The cap layer 16 does not contain aluminum.

  Further, instead of a nitride semiconductor layer having a HEMT structure, a nitride semiconductor layer to which an impurity is added may be used as an active layer (channel layer), and an FET structure having a structure in which the cap layer described above is formed thereon. it can.

1 is a cross-sectional view of a nitride semiconductor device according to a first embodiment of the present invention. It is a characteristic view which shows the X-ray diffraction rocking curve in a GaN (004) surface. (a), (b) is a characteristic view showing drain current-voltage characteristics when the half width of the cap layer is varied in the first embodiment. (c), (d) is a characteristic diagram showing drain current-voltage characteristics when the full width at half maximum of the cap layer is varied in the first embodiment. FIG. 4 is a characteristic diagram of a drain current ratio with respect to a half-value width in FIGS. It is sectional drawing of the nitride semiconductor device of the 2nd Example of this invention. It is sectional drawing of the conventional nitride semiconductor device.

Explanation of symbols

11: sapphire substrate, 12: buffer layer, 13: channel layer, 14: carrier supply layer, 15: Schottky layer, 16: cap layer, 17, 17A: gate electrode, 18, 18A: source electrode, 19, 19A: drain Electrode 21: Sapphire substrate, 22: Buffer layer, 23: Channel layer, 24: Carrier supply layer, 25: Schottky layer, 27: Gate electrode, 28: Source electrode, 29: Drain electrode

Claims (3)

III-V composed of a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium and a group V element containing at least nitrogen within the group consisting of nitrogen, phosphorus and arsenic In a nitride semiconductor device comprising a group nitride semiconductor layer,
A first nitride semiconductor layer made of the group III-V nitride semiconductor layer laminated on a substrate, and the group III-V nitride semiconductor not containing aluminum laminated on the first nitride semiconductor layer A second nitride semiconductor layer comprising a layer and a control electrode in Schottky contact with the second nitride semiconductor layer,
The nitride semiconductor device, wherein the second nitride semiconductor layer has a polycrystalline structure in which a half width of an X-ray diffraction rocking curve in the (004) plane is included in an angle range of 4000 seconds to 12000 seconds. III-V composed of a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium and a group V element containing at least nitrogen within the group consisting of nitrogen, phosphorus and arsenic In a nitride semiconductor device comprising a group nitride semiconductor layer,
A first nitride semiconductor layer made of the group III-V nitride semiconductor layer laminated on a substrate, and the group III-V nitride semiconductor not containing aluminum laminated on the first nitride semiconductor layer A second nitride semiconductor layer comprising a layer, and a control electrode in Schottky contact with the first nitride semiconductor layer from a recess formed in the second nitride semiconductor layer,
The nitride semiconductor device, wherein the second nitride semiconductor layer has a polycrystalline structure in which a half width of an X-ray diffraction rocking curve in the (004) plane is included in an angle range of 4000 seconds to 12000 seconds. The nitride semiconductor device according to claim 1 or 2,
A nitride semiconductor device, wherein a source electrode and a drain electrode that are in ohmic contact with the second nitride semiconductor layer are disposed so as to sandwich the control electrode.

Images