JP2008187346A - Waveform shaping circuit, and radio receiving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a waveform shaping circuit capable of improving characteristics in rise while suppressing the deterioration in waveform shaping. <P>SOLUTION: The waveform shaping circuit 1 generates an output signal Vout obtained by shaping an input signal Vin into a binary waveform on the basis of a reference signal Vref. The circuit 1 is provided with a reference signal generator 2 for generating the reference signal Vref, and a comparator COMP1 for generating an output signal Vout depending on a result of comparison between the input signal Vin and the reference signal Vref. The reference signal generator 2 outputs an intermediate voltage Vc between a peak hold value (Vp) and a bottom hold value (Vb) in the input signal Vin to the comparator COMP1, and then, outputs a voltage obtained by integrating the input signal Vin as a reference signal Vref into the comparator COMP1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a waveform shaping circuit that shapes an input signal into a binary waveform based on a reference signal and outputs the same, and a radio reception apparatus including the waveform shaping circuit.

  2. Description of the Related Art Conventionally, a wireless receiver that demodulates data from a received wireless signal has a waveform shaping circuit that shapes an analog waveform input signal into a binary waveform. In such a waveform shaping circuit, a comparator (comparator) that compares an input signal and a reference signal is used (see, for example, Patent Document 1).

  FIG. 7 shows a conventional waveform shaping circuit 100. In the figure, an input signal Vin is input to a non-inverting input terminal and an inverting input terminal of a comparator COMP100 via resistors R100 and R101, respectively.

  Here, the capacitive element C100 is connected between the inverting input terminal of the comparator COMP100 and the ground voltage (ground), and an integrating circuit is formed between the resistor R101 and the capacitive element C100. The signal generated by this integration circuit becomes the reference signal Vref and is compared with the input signal Vin.

  That is, the input signal Vin is compared on the basis of a signal obtained by integrating the input signal Vin by an integrating circuit including the resistor R101 and the capacitive element C100. The high level output signal Vout is compared when the input signal Vin is larger than the reference signal Vref by a predetermined value or more, and the low level output signal Vout is compared when the input signal Vin is smaller than the reference signal Vref by a predetermined value or more. Is output from the COMP100. The comparator COMP100 has a predetermined hysteresis characteristic.

  Note that the time constant of the integration circuit (values of the resistor R101 and the capacitive element C100) is set so that the reference signal Vref generated by the integration circuit is in the vicinity of the operating point voltage of the input signal Vin.

JP 2002-135340 A

  However, in the waveform shaping circuit described in Patent Document 1, since the reference signal Vref is generated by the integration circuit, it takes time until the reference signal Vref becomes the operating point voltage Vdc of the input signal Vin. The desired output signal Vout cannot be output, and the waveform shaping characteristics deteriorate.

  Therefore, as shown in FIG. 8, it is conceivable to add a charge circuit 201 that rapidly charges the voltage of the capacitive element of the integration circuit. FIG. 8 is a diagram showing a configuration of the waveform shaping circuit 200 provided with the charge circuit 201.

  The charge circuit 201 is a circuit having a comparator (comparator) COMP200 and a diode D200, and inputs the input signal Vin to the inverting input terminal of the comparator COMP200, and compares the output of the comparator COMP200 via the diode D200. Is input to the non-inverting input terminal of the COMP200.

  When the input signal Vin is lower than the capacitive element C100 of the integrating circuit 101, the output of the comparator COMP200 becomes a high level, current flows into the capacitive element C100 via the diode D200, and the reference signal Vref is rapidly increased. I am doing so. At this time, the comparator so that the high level signal output from the comparator COMP200 is higher than the operating point voltage Vdc of the input signal Vin (the voltage of the DC component of the input signal Vin) by the forward voltage of the diode D200. By adjusting the power supply voltage of the COMP 200, the time during which the voltage of the capacitive element C100 becomes the operating point voltage Vdc of the input signal Vin can be shortened.

  However, when an input signal Vin whose operating point voltage Vdc of the input signal Vin varies greatly is input, an error may occur between the reference signal Vref and the operating point voltage Vdc of the input signal Vin. When this error is large, it takes time until the reference signal Vref shifts to the operating point voltage Vdc of the input signal Vin. FIG. 9 shows state transitions of the input signal Vin and the reference signal Vref when the waveform shaping circuit 200 starts to operate. This figure shows a state in which the charge circuit 201 is controlled to operate only during the period ta when the waveform shaping circuit 200 starts operating by a control unit (not shown). The period tb shows a state in which the reference signal Vref is shifted to the operating point voltage Vdc of the input signal Vin when the input signal Vin is input to the integrating circuit 101. When the period tb starts, the charge circuit 201 stops its operation and does not affect the integration circuit 101.

  Here, in the period tb, the time until the reference signal Vref shifts to the operating point voltage Vdc of the input signal Vin depends on the time constant of the integrating circuit 101. Therefore, by reducing the time constant of the integrating circuit 101, the time until the reference signal Vref shifts to the operating point voltage Vdc of the input signal Vin can be shortened.

  However, when the time constant of the integrating circuit 101 is reduced, the fluctuation of the reference signal Vref with respect to the input signal Vin increases, and the waveform shaping characteristics in the waveform shaping circuit 200 are degraded.

  Therefore, an object of the present invention is to provide a waveform shaping circuit and a radio receiving apparatus that can improve the rising characteristics while suppressing the deterioration of the waveform shaping characteristics.

  The invention according to claim 1 is a waveform shaping circuit that generates an output signal obtained by shaping an input signal into a binary waveform based on a reference signal, a reference signal generator that generates the reference signal, the input signal, and the input signal A comparator that generates the output signal according to a comparison result with a reference signal, and the reference signal generator uses the intermediate voltage between a peak hold value and a bottom hold value in the input signal as the reference signal. After being output to the comparator, a voltage obtained by integrating the input signal is output to the comparator as the reference signal.

  According to a second aspect of the present invention, in the first aspect of the present invention, the reference signal generator holds a peak hold unit that holds and outputs a peak value of the input signal, and holds a bottom value of the input signal. A bottom hold unit for output, an intermediate voltage generation unit for outputting an intermediate voltage between the output of the peak hold unit and the output of the bottom hold unit, a capacitive element connected to the input of the comparator, and the input signal A switching unit that selects any one of the intermediate voltage output from the intermediate voltage generation unit and the input signal input to the resistor and connects the input signal to the capacitive element, The voltage of the capacitive element is used as the reference signal.

  The invention according to claim 3 is the invention according to claim 2, wherein the peak hold unit outputs a minimum output voltage in an initial state, and the bottom hold unit outputs a maximum output voltage in an initial state. It is characterized by.

  According to a fourth aspect of the present invention, in the third aspect of the present invention, the peak hold unit can adjust the minimum output voltage.

  According to a fifth aspect of the present invention, in the third or fourth aspect of the present invention, the bottom hold unit can adjust the maximum output voltage.

  According to a sixth aspect of the present invention, in the wireless reception device including a wireless reception unit that receives and demodulates a modulated wireless signal, the wireless reception unit generates binary data from the received wireless signal. A waveform shaping circuit that performs a reference signal generator that generates the reference signal, and a comparator that generates an output signal according to a comparison result between the input signal and the reference signal. The reference signal generator outputs an intermediate voltage between a peak hold value and a bottom hold value in the input signal to the comparator as the reference signal, and then uses a voltage obtained by integrating the input signal as the reference signal. It outputs to the said comparator, It is characterized by the above-mentioned.

  According to the waveform shaping circuit and the wireless reception device of the present invention, the intermediate voltage between the peak hold value and the bottom hold value of the input signal is used as a reference signal for comparison with the input signal. Characteristics can be improved.

  The radio reception apparatus according to the present embodiment includes a radio reception unit that receives and demodulates a modulated radio signal, and operates based on a signal (data) demodulated by the radio reception unit. When the wireless reception device is a mobile phone or the like, the signal demodulated by the wireless reception unit includes an audio signal in addition to the control signal.

  The wireless reception unit includes a waveform shaping circuit that generates an output signal obtained by shaping the input signal into a binary waveform based on the reference signal. The waveform shaping circuit includes a reference signal generator that generates a reference signal and a comparator that generates an output signal in accordance with a comparison result between the input signal and the reference signal.

  In addition, the reference signal generator outputs an intermediate voltage between the peak hold value and the bottom hold value in the input signal as a reference signal to the comparator, and then outputs a voltage obtained by integrating the input signal as a reference signal to the comparator.

  Therefore, at the start of operation, an intermediate voltage between the input signal that has been peak-held and the input signal that has been bottom-held can be used as a reference signal. The waveform shaping characteristic at the time of rising can be improved while suppressing the above.

  In particular, the reference signal generator includes a peak hold unit that holds and outputs the peak value of the input signal with a predetermined time constant, a bottom hold unit that holds and outputs the bottom value of the input signal with a predetermined time constant, An intermediate voltage generator that outputs an intermediate voltage between the output of the peak hold unit and the output of the bottom hold unit, a capacitive element connected to the input of the comparator, a resistor that inputs an input signal, and an output from the intermediate voltage generator A switching unit that selects either the intermediate voltage or the input signal input to the resistor and connects to the capacitor, and uses the voltage of the capacitor as a reference signal.

  That is, charging of the capacitive element in the CR integrating circuit that integrates the input signal is first performed by the intermediate voltage generated by the intermediate voltage generating unit, and then the intermediate voltage generating unit is disconnected from the capacitive element, and a resistor is connected to the capacitive element. Thus, a CR integration circuit is configured, and an input signal is input to the capacitive element via this resistor to charge / discharge the capacitive element.

  Therefore, when the reference voltage is generated by switching to the CR integration circuit, the capacitor of the CR integration circuit is already at a voltage close to the operating point voltage of the input signal. An output signal can be generated.

  The peak hold unit outputs the minimum output voltage in the initial state, and the bottom hold unit outputs the maximum output voltage in the initial state. When the waveform shaping circuit starts operating, the minimum output voltage and the maximum output are output. An intermediate voltage with respect to the voltage can be used as a reference signal, and an output signal can be generated based on a reference signal close to the operating point voltage of the input signal immediately after the start of operation. Here, the “minimum output voltage” in the peak hold unit means the minimum voltage that the peak hold unit can output during its operation, and the “maximum output voltage” in the bottom hold unit means that the bottom hold unit during its operation. The maximum voltage that can be output.

  In addition, the peak hold unit can adjust the minimum output voltage, and the bottom hold unit can adjust the maximum output voltage, thereby adjusting the intermediate voltage and providing a versatile waveform shaping circuit. Can do.

  Hereinafter, the waveform shaping circuit 1 in the wireless reception device A of the present embodiment will be described based on the drawings. FIG. 1 is a diagram showing a specific configuration of a waveform shaping circuit 1 in the present embodiment.

  As shown in FIG. 1, the waveform shaping circuit 1 in the present embodiment has a reference signal generator 2 that generates a reference signal Vref, a hysteresis characteristic, and according to a comparison result between the input signal Vin and the reference signal Vref. The comparator COMP1 that generates the output signal Vout and the input resistor R1 that inputs the input signal Vin and outputs the input signal Vin to the non-inverting input terminal of the comparator 3 are provided.

  The reference signal generator 2 outputs the intermediate voltage Vc between the peak hold value (Vp) and the bottom hold value (Vb) in the input signal Vin as the reference signal Vref to the inverting input terminal of the comparator COMP1, and then integrates the input signal Vin. This voltage is output as a reference signal Vref to the inverting input terminal of the comparator COMP1, and has the following configuration.

  That is, the reference signal generator 2 has a peak hold value obtained by holding the peak value of the input signal Vin with a predetermined time constant in order to output the intermediate voltage Vc as the reference signal Vref to the inverting input terminal of the comparator COMP1. Peak hold unit 10 for outputting hold signal Vp, bottom hold unit 11 for outputting bottom hold signal Vb having a bottom hold value obtained by holding the bottom value of input signal Vin with a predetermined time constant, and output of peak hold unit 10 And an intermediate voltage generation unit 12 that outputs an intermediate voltage Vc between the peak hold signal Vp and the bottom hold signal Vb that is the output of the bottom hold unit 11. Note that the peak hold unit 10 and the bottom hold unit 11 have a comparator, a capacitive element, a resistor, and the like inside, and a time constant for holding the peak value and the bottom value includes a capacitive element C1 and a resistor R2, which will be described later. The time constant is smaller than the time constant of the integration circuit.

  Here, the peak hold unit 10 is configured to output the minimum output voltage Vpmin in the initial state and the bottom hold unit 11 can output the maximum output voltage Vbmax in the initial state under the control of the control unit 14 described later. is doing. For example, when the waveform shaping circuit 1 is operating at the power supply voltage Vcc with reference to the ground voltage (ground), the minimum output voltage Vpmin can be the ground voltage, and the maximum output voltage Vbmax can be the power supply voltage Vcc. The intermediate voltage Vc is {maximum output voltage Vbmax−minimum output voltage Vpmin} / 2, which is the power supply voltage Vcc / 2.

  Since the peak hold unit 10 and the bottom hold unit 11 are thus configured, the intermediate voltage Vc can be set to {maximum output voltage Vbmax−minimum output voltage Vpmin} / 2 when the waveform shaping circuit 1 starts to operate. Therefore, the intermediate voltage Vc can be made equal to the operating point voltage Vdc of the input signal Vin by setting the maximum output voltage Vbmax and the minimum output voltage Vpmin.

  Further, the peak hold unit 10 can adjust the minimum output voltage Vpmin, whereby the intermediate voltage Vc in the initial state can be easily adjusted. Similarly, the bottom hold unit 11 can adjust the maximum output voltage Vbmax, and this can also easily adjust the intermediate voltage Vc in the initial state.

  The intermediate voltage generation unit 12 is provided with resistors R3 and R4 having the same resistance value connected in series between the output of the peak hold unit 10 and the output of the bottom hold unit 11, and a connection point between the resistors R3 and R4. Is an intermediate potential between the peak hold signal Vp and the bottom hold signal Vb. The voltage at the connection point between the resistors R3 and R4 is output as the intermediate voltage Vc by the buffer amplifier IC2.

  Further, the reference signal generator 2 is connected to the inverting input terminal of the comparator COMP1 via the first switch SW1 in order to output the voltage obtained by integrating the input signal Vin as the reference signal Vref to the inverting input terminal of the comparator COMP1. The capacitive element C1 and a resistor R2 for inputting the input signal Vin are provided.

  In order to switch the reference signal Vref to either “intermediate voltage Vc” or “voltage obtained by integrating the input signal Vin”, the intermediate voltage Vc output from the intermediate voltage generator 12 and the input signal Vin input to the resistor R2 And a first switch SW1 that is a switching unit that connects to the capacitive element C1. The voltage of the capacitive element C1 becomes the reference signal Vref.

  The first switch SW1 is controlled by a control signal Vcont from the switching control unit 13 that operates based on the input signal Vin.

  The switching control unit 13 includes comparators COMP2 and COMP3 having hysteresis and a negative OR (NOR) circuit IC1. The input signal Vin is input to the inverting input terminal of the comparator COMP2 and the non-inverting input terminal of the comparator COMP3, and the bottom hold signal Vb output from the bottom hold unit 11 is input to the non-inverting input terminal of the comparator COMP2. The peak hold signal Vp output from the peak hold unit 10 is input to the inverting input terminal of the comparator COMP3. Further, the signals output from the comparators COMP2 and COMP3 are input to the negative OR circuit IC1, the logical operation is performed by the negative OR circuit IC1, and the control signal Vcont is output from the negative OR circuit IC1.

  Therefore, when the peak hold signal Vp becomes a voltage higher than the input signal Vin and the bottom hold signal Vb becomes a voltage lower than the input signal Vin, the control signal Vcont becomes a high level, otherwise the control signal Vcont goes low.

  The operation of the waveform shaping circuit 1 configured as described above will be specifically described with reference to FIG. FIG. 2 is a diagram for explaining the operation of the waveform shaping circuit 1 in the present embodiment. The input signal Vin, the reference signal Vref, and the output signal in the operation stop state, the initial state, the first operation state, and the second operation state. A state such as Vout is shown.

  First, when the waveform shaping circuit 1 is in an operation stop state (until “t0” in FIG. 2), both the input signal Vin and the reference signal Vref are 0 V (ground voltage). The output signal Vout is at a low level.

  After that, when the operation of the waveform shaping circuit 1 starts (“t1” in FIG. 2), the control unit 14 keeps the peak hold unit 10 and the bottom hold unit 11 in the initial state until the input signal Vin is input. To do. That is, a high level control signal Vout2 is output from the control unit 14, the peak hold unit 10 outputs the minimum output voltage Vpmin, and the bottom hold unit 11 outputs the maximum output voltage Vbmax. Accordingly, in the initial state, the intermediate voltage generator 12 outputs a voltage intermediate between the maximum output voltage Vbmax and the minimum output voltage Vpmin as the intermediate voltage Vc.

  In the initial state, since the control signal Vcont output from the switching control unit 13 is at a low level, the first switch SW1 is connected to the capacitive element C1 and the intermediate voltage generation unit 12. The intermediate voltage Vc output from the intermediate voltage generator 12 is applied to the capacitive element C1. Accordingly, the capacitive element C1 is rapidly charged, and the voltage level thereof is the same as the intermediate voltage Vc.

  Thereafter, when the input of the input signal Vin is started (“t2” in FIG. 2), the control unit 14 cancels the initial states of the peak hold unit 10 and the bottom hold unit 11 and shifts to the first operation state. Thus, the peak hold signal Vp is output from the peak hold unit 10 and the bottom hold signal Vb is output from the bottom hold unit 11 in accordance with the input signal Vin. Then, an intermediate voltage Vc between the peak hold signal Vp and the bottom hold signal Vb corresponding to the input signal Vin is applied to the capacitive element C1.

  Thereafter, when the input signal Vin becomes lower than the peak hold signal Vp and higher than the bottom hold signal Vb, the switching control unit 13 outputs a high level control signal Vcont to enter the second operation state. The first switch SW1 is switched from a state in which the capacitive element C1 and the intermediate voltage generating unit 12 are connected to a state in which the capacitive element C1 and the resistor R2 are connected, and the input signal Vin is switched to the capacitive element C1 via the resistor R2. To be applied. Therefore, an integrating circuit composed of the resistor R2 and the capacitive element C1 is configured, and the input signal Vin is integrated by this integrating circuit.

  In this way, after the first switch SW1 is switched to the intermediate voltage generation unit 12 side, the capacitor C1 is rapidly charged, and then the first switch SW1 is switched to the resistor R2 side, whereby the reference signal Vref is changed to the resistor R2. In addition, the waveform shaping characteristic at the start of the operation of the waveform shaping circuit 1 can be improved, and the waveform shaping characteristic can be continuously stabilized thereafter. . Further, since the intermediate voltage Vc between the peak hold signal Vp and the bottom hold signal Vb is set as the reference signal Vref, the error when the intermediate voltage generator 12 is disconnected from the capacitive element C1 is also less than about 1/4 of the signal amplitude. Therefore, the waveform shaping characteristic can be improved even for the problem that the operating point voltage fluctuates in the input signal Vin.

  Further, instead of the reference signal generator 2, a reference signal generator 2 'to which an initial voltage adjusting circuit 15 is added may be used as shown in FIG. FIG. 3 is a diagram showing a specific configuration of another waveform shaping circuit 1 'in the present embodiment. In the waveform shaping circuit 1 ′, the same parts as those of the waveform shaping circuit 1 are denoted by the same reference numerals, and the parts different from the waveform shaping circuit 1 will be described here.

  As shown in FIG. 3, the initial voltage adjusting circuit 15 includes a switch SW5, a resistor R5, a resistor R6, and a diode D1 between the power supply voltage Vcc of the waveform shaping circuit 1 ′ and the ground voltage (ground). The resistor R7 and the switch SW6 are connected in series. The anode side of the diode D1 is connected to the resistor R6, and the cathode side is connected to the resistor R7.

  Further, a switch SW3 is provided between the connection point of the resistors R5 and R6 and the output of the bottom hold unit 11, and between the connection point of the resistor R6 and the diode D1 and the peak hold unit 10. A switch SW4 is provided.

  The switches SW3 to SW6 are controlled by a control signal Vout2 output from the control unit 14. That is, when the high-level control signal Vout2 is output from the control unit 14, the switches SW3 to SW6 are closed (short-circuited), and the intermediate voltage Vc in the intermediate voltage generation unit 12 is adjusted by the initial voltage adjustment circuit 15. The Further, the peak hold unit 10 and the bottom hold unit 11 stop the operation (the output is stopped and the output is set to high impedance) by the high level control signal Vout2 output from the control unit 14.

  The operation of the waveform shaping circuit 1 'configured as described above will be specifically described with reference to FIG. FIG. 4 is a diagram for explaining the operation of the waveform shaping circuit 1 ′ in the present embodiment. The input signal Vin, the reference signal Vref, and the output in the operation stop state, the initial state, the first operation state, and the second operation state. The state of the signal Vout and the like is shown.

  Since this waveform shaping circuit 1 ′ operates in the same manner as the waveform shaping circuit 1 except that the initial state operation is different from that of the above-described waveform shaping circuit 1, the initial state operation will be described here.

  During the period from the start of the operation of the waveform shaping circuit 1 ′ (“t1” in FIG. 4) until the input signal Vin is input (that is, “initial state”), the control unit 14 includes the peak hold unit 10 and the bottom The hold unit 11 is deactivated and the initial voltage adjustment circuit 15 is operated. That is, a high level control signal Vout2 is output from the control unit 14, and the peak hold unit 10 and the bottom hold unit 11 stop outputting. On the other hand, in the initial voltage adjusting circuit 15, the switches SW3 to SW6 are closed, the peak hold unit 10 is connected to the ground voltage via the diode D1 and the resistor R7, and the bottom hold unit 11 is connected to the power supply voltage Vcc via the resistor R5. Connected to.

  Therefore, the voltage (Vp) on the output side of the peak hold unit 10 becomes a predetermined voltage output from the initial voltage adjustment circuit 15 (see “Initial voltage High” in FIG. 4), and the voltage on the output side of the bottom hold unit 11 The voltage (Vb) is a predetermined voltage output from the initial voltage adjustment circuit 15 (see “initial voltage Low” in FIG. 4). Therefore, the intermediate voltage Vc output from the intermediate voltage generator 12 is an intermediate voltage between the initial voltage High and the initial voltage Low.

  In the initial state, since the control signal Vcont output from the switching control unit 13 is at a low level, the first switch SW1 is connected to the capacitive element C1 and the intermediate voltage generating unit 12. The intermediate voltage Vc output from the intermediate voltage generator 12 is applied to the capacitive element C1. Accordingly, the capacitive element C1 is rapidly charged, and the voltage level thereof is the same as the intermediate voltage Vc.

  As described above, in the waveform shaping circuit 1 ′, the voltage of the capacitive element C1 (reference signal Vref) is brought close to the operating point voltage Vdc of the input signal Vin by the initial voltage adjustment circuit 15, and the peak hold unit 10 is obtained from the voltage. And by starting the hold operation in the bottom hold unit 11, the charging time of the capacitive element C1 can be further shortened, and the waveform shaping characteristics at the rise can be improved.

  In the above-described embodiment, the first switch SW1 is switched when the high-level control signal Vcont is output from the switching control unit 13, but the control unit 14 is not provided without providing the switching control unit 13. The first switch SW1 may be switched to the resistor R2 side at a timing after a predetermined time has elapsed from the timing of releasing the initial state ("t2" in FIG. 2) or the timing of releasing the initial state. By doing so, the configuration becomes simple, and the mounting area of the waveform shaping circuit 1 can be reduced.

  Note that the present invention is not limited to the determination of the comparison reference of the comparator, and can be applied to a circuit in which the operating point of the circuit needs to be changed according to the signal level of the input signal Vin.

  Next, the configuration of the wireless reception device A including the waveform shaping circuit 1 described above will be specifically described with reference to the drawings. FIG. 5 is a configuration diagram showing a wireless receiver A provided with the waveform shaping circuit 1 in the present embodiment. Note that the radio receiving apparatus including the waveform shaping circuit 1 ′ has the same configuration, and thus the description thereof is omitted here.

  The radio receiving apparatus A according to the present embodiment includes an antenna 20 that receives a modulated radio signal, a radio receiving unit 30 that demodulates a signal output from the antenna 20, and a signal demodulated by the radio receiving unit 30. It comprises a signal processing unit 40 for processing.

  The radio receiving unit 30 includes a low noise amplifier (LNA) 31 that amplifies a signal output from the antenna 20 and a signal (RF Local signal) output from an oscillator via a PLL (Phase Locked Loop). And a mixer 32 for mixing the output from the low noise amplifier circuit 31, an IF filter 33 for filtering the signal output from the mixer 32, and a LIM amplifier (limiter amplifier) for amplifying the signal output from the IF filter 33 ) 34, a detector 35 for detecting the output from the LIM amplifier, an LPF (Low Pass Filter) 36 for filtering a signal output from the detector 35, and the waveform shaping circuit 1 described above.

  The radio signal received by the antenna 20 is input to the waveform shaping circuit 1 as the input signal Vin via the respective blocks 31 to 36, and this input signal Vin is binary waveform based on the reference signal Vref by the waveform shaping circuit 1. And then output to the signal processing unit 40.

  Here, the amplitude and operating point voltage of the signal output from the detector 35 vary depending on the frequency of the signal input to the detector 35 (see, for example, FIG. 6). Therefore, the amplitude of the signal output from the detector 35 and the operating point voltage vary depending on the frequency of the radio signal received by the antenna 20 and the characteristics of the circuit preceding the detector 35. However, by providing the above-described waveform shaping circuit 1 in the wireless reception unit 30, even when there is a change in the operating point voltage or the like, it is possible to suppress a decrease in waveform shaping characteristics, and the reception sensitivity in the wireless reception unit 30 can be reduced. There is also an advantage that deterioration can be prevented.

  In addition to the wireless receiver using FSK (Frequency Shift Keying) and ASK (Amplitude Shift Keying), the wireless receiver according to the present embodiment includes a mobile phone device, a keyless entry device, and a TPMS for monitoring tire pressure ( It can be applied to tire pressure measurement system) devices, infrared remote control devices, non-contact IC card devices, weak power wireless devices, and the like.

  The wireless reception device of the present invention may be created as an IC in which each function is integrated, or may be created by mounting components having each function on a substrate.

It is a figure which shows the structure of the waveform shaping circuit in embodiment of this invention. It is a figure for demonstrating operation | movement of the waveform shaping circuit in FIG. It is a figure which shows the structure of the other waveform shaping circuit in embodiment of this invention. It is a figure for demonstrating operation | movement of the waveform shaping circuit in FIG. It is a figure which shows the basic composition of the radio | wireless receiving apparatus in embodiment of this invention. It is a figure which shows the characteristic of the FM detector of the radio | wireless receiver in embodiment of this invention. It is a figure which shows the structure of the conventional waveform shaping circuit. It is a figure which shows the structure which added the charge circuit to the conventional waveform shaping circuit. It is a figure for demonstrating operation | movement of the waveform shaping circuit in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Waveform shaping circuit 2 Reference signal generator 3 Comparator 10 Peak hold part 11 Bottom hold part 12 Intermediate voltage generation part 13 Switching control part 14 Control part 15 Initial voltage adjustment circuit 20 Antenna 30 Radio | wireless reception part 40 Signal processing part COMP1-COMP3 Comparator IC1 NAND circuit IC2 Buffer amplifier C1 Capacitance elements R1 to R7 Resistors SW1 to SW6 Switch

Claims (6)

In a waveform shaping circuit that generates an output signal obtained by shaping an input signal into a binary waveform based on a reference signal,
A reference signal generator for generating the reference signal;
A comparator that generates the output signal according to a comparison result between the input signal and the reference signal;
The reference signal generator is
An intermediate voltage between a peak hold value and a bottom hold value in the input signal is output to the comparator as the reference signal, and then a voltage obtained by integrating the input signal is output to the comparator as the reference signal. Waveform shaping circuit. The reference signal generator is
A peak hold unit for holding and outputting a peak value of the input signal;
A bottom hold unit for holding and outputting the bottom value of the input signal;
An intermediate voltage generator for outputting an intermediate voltage between the output of the peak hold unit and the output of the bottom hold unit;
A capacitive element connected to the input of the comparator;
A resistor for inputting the input signal;
A switching unit that selects either the intermediate voltage output from the intermediate voltage generation unit and the input signal input to the resistor and connects to the capacitive element;
The waveform shaping circuit according to claim 1, wherein the voltage of the capacitive element is used as the reference signal. The peak hold unit outputs a minimum output voltage in an initial state,
The waveform shaping circuit according to claim 2, wherein the bottom hold unit outputs a maximum output voltage in an initial state. The waveform shaping circuit according to claim 3, wherein the peak hold unit is capable of adjusting the minimum output voltage. The waveform shaping circuit according to claim 3, wherein the bottom hold unit is capable of adjusting the maximum output voltage. In a wireless reception device including a wireless reception unit that receives and demodulates a modulated wireless signal,
The wireless reception unit has a waveform shaping circuit that generates binarized data from the received wireless signal,
The waveform shaping circuit is
A reference signal generator for generating the reference signal;
A comparator that generates an output signal according to a comparison result between the input signal and the reference signal;
The reference signal generator is
An intermediate voltage between a peak hold value and a bottom hold value in the input signal is output to the comparator as the reference signal, and then a voltage obtained by integrating the input signal is output to the comparator as the reference signal. Wireless receiver.

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