JP2008187027A - Design method of semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the different route clock skew by delay fluctuation caused by the variation. <P>SOLUTION: A plurality of cells and a clock tree 2 are arranged in a coordinate region 1. Clock buffers 4-1, 4-2, 12 and 22 are disposed on the clock tree 2. Dummy clock buffers 18 and 28 for adjusting clock skew which occurs between non-common nets are connected to first and second non-common nets (13, 15-1, 15-2 and 17) and (23, 25-1 to 25-3 and 27) of the clock tree 2. For transferring data between the cells 16-2 and 26-1, the different route clock skew may arise since the cells 16-2 and 26-1 are connected to the first and second non-common nets. Thus, a connection change dummy clock buffer 29 is connected to the second non-common nets (23, 25-1 to 25-3 and 27) instead of the cell 26-1, and the cell 26-1 is connected to the dummy clock buffer 18. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a design method for designing a semiconductor integrated circuit.

  Computers for designing semiconductor integrated circuits have been developed. The computer arranges a plurality of cells (flip-flops) constituting a semiconductor integrated circuit in a predetermined coordinate area (X, Y), and a clock from an input end is supplied to each of the plurality of cells. The clock tree in which the wiring is routed is arranged in a predetermined coordinate area (X, Y). The computer also arranges a clock buffer for driving the clock on the clock tree.

  For example, the clock is supplied to the first and second cell groups of the plurality of cells. In this case, the first delay time until the clock is transmitted from the input end to the first cell group may be the same as the second delay time until the clock is transmitted from the input end to the second cell group. desirable. However, when the time difference between the first delay time and the second delay time is large, clock skew occurs. Japanese Patent Laid-Open No. 2001-306643 discloses a design method for adjusting the first delay time and the second delay time to the same delay time in order to reduce the clock skew.

  FIG. 1 shows the configuration of a design system to which a conventional semiconductor integrated circuit design method is applied. The design system includes a computer 140, an input device 143, an output device 144, and a design tool 145 that is software.

  The design tool 145 includes a control unit 150 that is a computer program, an arrangement information file 161, and a delay information file 162. The arrangement information file 161 has a predetermined coordinate area (X, Y) in which parts for configuring the semiconductor integrated circuit are arranged. In the arrangement information file 161, a name for identifying a part and coordinates (X, Y) when the part is arranged in a predetermined coordinate area are stored by the control unit 150. In the delay information file 162, the coordinates when the clock is transmitted from part to part and the delay time at that time are stored by the control unit 150.

  FIG. 2 shows a semiconductor integrated circuit arranged in a coordinate area 101 which is a predetermined coordinate area (X, Y).

  The control unit 150 newly creates an arrangement information file 161 in accordance with the operation of the input device 143 by the user, and displays the coordinate area 101 of the arrangement information file 161 on the output device 144 (display device). The control unit 150 arranges a plurality of cells 116-1, 116-2, 126-1 to 126-3,... In the coordinate area 101 as the above components in accordance with the operation of the input device 143 by the user. The plurality of cells 116-1, 116-2, 126-1 to 126-3,... Are circuits that operate according to the clock CLK.

  The control unit 150 places the clock tree 102 in the coordinate area 101. The clock tree 102 includes wiring (103, 105), a branch point 106, and a plurality of blocks 131 to 134 as the above components. One end of the wiring (103, 105) is connected to an input end IN to which a clock CLK is supplied. The other end of the wiring (103, 105) is connected to a plurality of blocks 131 to 134 via a branch point 106. Here, the block 131 among the plurality of blocks 131 to 134 will be described.

  The block 131 includes wiring (107, 108), a branch point 109, and a plurality of blocks 110, 120. The wiring (107, 108) has a branch point 106 connected to one end thereof, and a plurality of blocks 110, 120 connected to the other end via a branch point 109.

  The block 110 includes a wiring (111, 113), a branch point 114, a wiring group 115-1, 115-2, and the plurality of cells 116-1, 116-2, 126-1 to 126-3,. Cell groups 116-1 and 116-2. The wiring (111, 113) has a branch point 109 connected to one end thereof and a branch point 114 connected to the other end thereof. Each of the wiring groups 115-1 and 115-2 has a branch point 114 connected to one end thereof, and cell groups 116-1 and 116-2 connected to the other ends thereof. That is, the cell groups 116-1 and 116-2 are connected in parallel.

  The block 120 includes wiring (121, 123), a branch point 124, wiring groups 125-1 to 125-3, and the plurality of cells 116-1, 116-2, 126-1 to 126-3,. Cell groups 126-1 to 126-3. The wiring (121, 123) has a branch point 109 connected to one end thereof and a branch point 124 connected to the other end thereof. Each of the wiring groups 125-1 to 125-3 has a branch point 124 connected to one end thereof, and cell groups 126-1 to 126-3 connected to the other end thereof. That is, the cell groups 126-1 to 126-3 are connected in parallel.

  The control unit 150 refers to the clock tree 102 on the arrangement information file 161 and determines the number of stages of the clock buffer for driving the clock CLK. The control unit 150 requires three stages of clock buffers for the block 110 depending on the number of branch points (branch points 106, 109, and 114) arranged in the cell groups 116-1 and 116-2 from the input terminal IN. Recognize that there is. The control unit 150 connects the clock buffer 104-1 as the first clock buffer on the wiring (103, 105), and the clock buffer 104-2 as the second clock buffer on the wiring (107, 108). The clock buffer 112 is connected as a third clock buffer on the wiring (111, 113).

  Further, the control unit 150 has three stages of clock buffers for the block 120 depending on the number of branch points (branch points 106, 109, and 124) arranged in the cell groups 126-1 to 126-3 from the input terminal IN. Recognize that it is necessary. The first and second clock buffers correspond to the clock buffers 104-1 and 104-2, respectively. The control unit 150 connects the clock buffer 122 as a third clock buffer on the wiring (121, 123).

  The control unit 150 transmits the clock CLK from the branch point 109 to the cell groups 116-1 and 116-2 based on the delay caused by the wirings 111 and 113, the wiring groups 115-1 and 115-2, and the clock buffer 112. Until the delay time t110 is calculated. Further, the control unit 150 transmits the clock CLK from the branch point 109 to the cell groups 126-1 to 126-3 based on the delays caused by the wirings 121 and 123, the wiring groups 125-1 to 125-3, and the clock buffer 122. The delay time t120 until it is calculated is calculated.

  A known method is used as a method of calculating the delay times t110 and t120. For example, a preset delay time set in advance and a variation delay time due to variations in temperature, voltage, and manufacturing are taken into consideration for the wiring and clock buffer. The set delay time in the wiring is proportional to the length of the wiring.

  The control unit 150 stores the coordinates from the branch point 109 to the cell groups 116-1 and 116-2 and the delay time t110 in the delay information file 162. Further, the control unit 150 stores the coordinates from the branch point 109 to the cell groups 126-1 to 126-3 and the delay time t120 in the delay information file 162.

  The control unit 150 refers to the delay information file 162 and executes a skew adjustment process for adjusting the delay time t110 and the delay time t120 to the same delay time. In the skew adjustment processing, the control unit 150 connects the skew adjustment wirings 117 and 127 to the branch points 114 and 124, respectively, and connects the inputs of the dummy clock buffers 118 and 128 to the skew adjustment wirings 117 and 127, respectively. The outputs of the dummy clock buffers 118 and 128 are not connected.

  The skew adjusting wires 117 and 127 have a capacity for adjusting a clock skew generated between the branch points 114 and 124. For this reason, the clock skew can be reduced by executing the skew adjustment processing.

JP 2001-306643 A

  For example, as shown in FIG. 2, the target cell 116-2 as one cell of the cell groups 116-1 and 116-2 and the target cell as one of the cell groups 126-1 to 126-3. Assume that data is transferred to and from the cell 126-1. Since the target cells 116-2 and 126-1 are connected to the branch points 114 and 124, respectively, the delay time until the clock CLK is transmitted from the branch point 109 to the target cell 116-2 and the clock CLK are branched. The delay time from the point 109 to the target cell 126-1 is increased, and there is a case where a clock skew due to delay variation is increased. This clock skew is called a different path clock skew.

  The reason is that the common branch point is the branch point 109 for the target cells 116-2 and 126-1. In this case, the non-common part for each of the target cells 116-2 and 126-1 is from the branch point 109 to the wirings 115-2 and 125-1. Therefore, the target delay time until the clock CLK is transmitted from the branch point 109 to the target cell 116-2 and the target delay time until the clock CLK is transmitted from the branch point 109 to the target cell 126-1 are increased. End up.

  As described above, when the non-common part up to the target cells 116-2 and 126-1 is long, the above-mentioned different path clock skew due to different delay fluctuations occurs for each path.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added to clarify the correspondence between the description of [Claims] and the description of [Best Mode for Carrying Out the Invention]. It should not be used to interpret the technical scope of the invention described in “

A method for designing a semiconductor integrated circuit according to the present invention includes:
A cell placement step (S1) for placing a plurality of cells (16-1, 16-2, 26-1 to 26-3,...) Operating according to a clock (CLK) in the coordinate area (1);
Input nets (5, 7) to which the clock (CLK) is input, and first and second cell groups including the plurality of cells (16-1, 16-2, 26-1 to 26-3,...). The first and second non-common nets (13, 15-1, 15-2, 17) (23, 25-) in which (16-1, 16-2) (26-1 to 26-3) are connected in parallel, respectively. 1-25-3, 27), the input net (5, 7) and the first and second non-common nets (13, 15-1, 15-2, 17) (23, 25-1-25- A tree placement step (S2) for placing a clock tree (2) including a common net (8, 11, 21) connected to the coordinate region (1) between
Between the input net (5, 7) and the common net (8, 11, 21), the common net (8, 11, 21) and the first and second non-common nets (13, 15-1) , 15-2, 17) (23, 25-1 to 25-3, 27), a buffer arrangement step (S 3) for connecting the clock buffers (4-2), (12) and (22),
First and second for adjusting clock skew generated between the first and second non-common nets (13, 15-1, 15-2, 17) (23, 25-1 to 25-3, 27). Skew for connecting the dummy clock buffers (18) and (28) to the first and second non-common nets (13, 15-1, 15-2, 17) (23, 25-1 to 25-3, 27), respectively. An adjustment step (S5);
First and second target cells (16-2) and (26-1) as one cell in the first and second cell groups (16-1, 16-2) (26-1 to 26-3) (S6-YES), the first and second target cells (16-2) and (26-1) are respectively connected to the first and second non-common nets (13, 15-1, 15-2, 17) (23, 25-1 to 25-3, 27) in order to adjust the different path clock skew due to delay variation caused by being connected to
A first connection changing step of connecting a connection changing dummy clock buffer (29) to the second non-common net (23, 25-1 to 25-3, 27) instead of the second target cell (26-1). (S9),
A second connection changing step (S9) for connecting the second target cell (26-1) to the first dummy clock buffer (18).

  As described above, according to the semiconductor integrated circuit design method of the present invention, it is possible to reduce the different path clock skew caused by the delay variation.

The reason is that the path is different from that of the first and second target cells (16-2) and (26-1), and thus the above-mentioned different path clock skew is caused by the different delay variation for each path. Before the first and second connection changing steps (S9) are executed, the common nets are the common nets (8, 11, 11) with respect to the first and second target cells (16-2) (26-1). 21), and non-common nets are non-common nets (13, 15-1, 15-2, 17) (25-1 to 25-3, 27). In this case, the non-common part for each of the first and second target cells (16-2) and (26-1) is the non-common net (13, 15-1, 15-2, 17) (25-1 to 25). -3, 27). For this reason, the clock (CLK) is common to the target delay time (t10 _16-2 ) until the clock (CLK) is transmitted from the common net (8, 11, 21) to the first target cell (16-2). The target delay time (t20 _26-1 ) until it is transmitted from the net (8, 11, 21) to the second target cell ( _26-1 ) is increased.

On the other hand, when the first and second connection changing steps (S9) are executed, the common nets are common nets (8, 8) with respect to the first and second target cells (16-2) (26-1). 11, 21) and non-common nets (13, 15-1, 15-2, 17), and non-common nets are non-common nets (13, 15-1, 15-2, 17). In this case, the non-common part for each of the first target cells (16-2) and 26-1 is only the non-common net (13, 15-1, 15-2, 17). Therefore, the improvement target delay time (t10 _16-2 ′) from when the clock (CLK) is transmitted from the non-common net (13, 15-1, 15-2, 17) to the first target cell (16-2). ) And the improvement target delay time (t20 _26-1 ′) until the clock (CLK) is transmitted from the non-common net (13, 15-1, 15-2, 17) to the second target cell (26-1). ) Is significantly shorter than the above delay time. As described above, the connection change that shortens the non-common part is performed on the first and second target cells (16-2) and (26-1), thereby causing different delay fluctuations with respect to the non-common part. Different path clock skew can be reduced.

  Hereinafter, a method for designing a semiconductor integrated circuit according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 3 shows the configuration of a design system to which the semiconductor integrated circuit design method of the present invention is applied. The design system includes a computer 40, an input device 43, and an output device 44. The input device 43 and the output device 44 are connected to the computer 40. The input device 43 includes a keyboard and a pointing device, and the output device 44 includes a display device.

  The computer 40 includes a storage unit 41 that stores a computer program, and a CPU (Central Processing Unit) 42 that is an execution unit that executes the computer program.

  The design system further includes a design tool 45 that is software. The design tool 45 is installed in the storage unit 41. The design tool 45 includes a computer program 50 and a file 60. The file 60 includes an arrangement information file 61 and a delay information file 62.

  FIG. 4 shows the arrangement information file 61. The arrangement information file 61 has a predetermined coordinate area (X, Y) in which parts for configuring the semiconductor integrated circuit are arranged. The arrangement information file 61 stores a name for identifying a part and coordinates (X, Y) when the part is arranged in a predetermined coordinate area by the computer program 50.

  FIG. 5 shows the delay information file 62. In the delay information file 62, the coordinates when the clock is transmitted from part to part and the delay time at that time are stored by the computer program 50.

  The computer program 50 includes a cell placement unit 51, a tree placement unit 52, a buffer placement unit 53, a delay time calculation unit 54, a skew adjustment unit 55, a target delay time calculation unit 56, and a connection change unit 57, which will be described later. The cell placement unit 51, the tree placement unit 52, the buffer placement unit 53, the delay time calculation unit 54, and the skew adjustment unit 55 correspond to the control unit 150 that is the above-described computer program. For example, the cell placement unit 51, the tree placement unit 52, the buffer placement unit 53, the delay time calculation unit 54, and the skew adjustment unit 55 are assumed to be installed in the storage unit 41 in advance as the existing computer program 150. In this case, the target delay time calculation unit 56 and the connection change unit 57 are additionally installed in the storage unit 41 as the connection change computer program 50 for the existing computer program 150.

  6 and 7 show a semiconductor integrated circuit arranged in the coordinate area 1 which is a predetermined coordinate area (X, Y).

  As shown in FIG. 6, the cell placement unit 51 newly creates a placement information file 61 in accordance with the operation of the input device 43 by the user, and outputs the coordinate area 1 of the placement information file 61 to the output device 44 (display). Displayed on the device. The cell arrangement unit 51 arranges a plurality of cells 16-1, 16-2, 26-1 to 26-3,... In the coordinate area 1 as the above components in accordance with the operation of the input device 43 by the user. The plurality of cells 16-1, 16-2, 26-1 to 26-3,... Operate in response to the clock CLK, and examples of the circuit include flip-flops and registers. In this embodiment, it is assumed to be a flip-flop.

  The tree placement unit 52 places the clock tree 2 in the coordinate area 1. The clock tree 2 includes common wires (3, 5), a branch point 6, and a plurality of blocks 31 to 34 as the above components. One end of the common wiring (3, 5) is connected to an input end IN to which a clock CLK is supplied. The other end of the common wiring (3, 5) is connected to a plurality of blocks 31 to 34 via a branch point 6. Here, the block 31 among the plurality of blocks 31 to 34 will be described.

  The block 31 includes common wiring (7, 8), a common branch point 9, and a plurality of blocks 10, 20. The common wiring (7, 8) has a branch point 6 connected to one end thereof, and a plurality of blocks 10, 20 connected to the other end via a common branch point 9.

  The block 10 includes a relay wiring (11, 13), a branch point 14, a wiring group 15-1, 15-2, and the plurality of cells 16-1, 16-2, 26-1 to 26-3, Of the cell groups 16-1 and 16-2. The relay wiring (11, 13) has a common branch point 9 connected to one end thereof and a branch point 14 connected to the other end thereof. Each of the wiring groups 15-1 and 15-2 has a branch point 14 connected to one end thereof, and cell groups 16-1 and 16-2 connected to the other ends thereof. That is, the cell groups 16-1 and 16-2 are connected in parallel.

  The block 20 includes a relay wiring (21, 23), a branch point 24, a wiring group 25-1 to 25-3, and the plurality of cells 16-1, 16-2, 26-1 to 26-3, Of the cell groups 26-1 to 26-3. The relay wiring (21, 23) has a common branch point 9 connected to one end thereof and a branch point 24 connected to the other end thereof. Each of the wiring groups 25-1 to 25-3 has a branch point 24 connected to one end thereof, and cell groups 26-1 to 26-3 connected to the other ends thereof. That is, the cell groups 26-1 to 26-3 are connected in parallel.

  The buffer arrangement unit 53 refers to the clock tree 2 on the arrangement information file 61 and determines the number of stages of the clock buffer for driving the clock CLK. The buffer placement unit 53 clocks the block 10 according to the number of branch points (branch point 6, common branch point 9, branch point 14) placed in the cell groups 16-1 and 16-2 from the input terminal IN. Recognize that three stages of buffers are required. The buffer arrangement unit 53 connects the clock buffer 4-1 as the first clock buffer on the common wiring (3, 5), and connects the clock buffer 4-2 as the second clock buffer to the common wiring (7, 8). ) And a clock buffer 12 as a third clock buffer is connected on the relay wiring (11, 13).

  In this case, the common wires (3, 5) are divided into common wires 3, 5. The common line 3 has one end connected to the input end IN and the other end connected to the input of the clock buffer 4-1. The common wire 5 has one end connected to the output of the clock buffer 4-1 and the other end connected to the branch point 6. The common wiring (7, 8) is divided into common wirings 7, 8. The common wiring 7 has one end connected to the branch point 6 and the other end connected to the input of the clock buffer 4-2. The common wire 8 has one end connected to the output of the clock buffer 4-2 and the other end connected to the common branch point 9. The relay wiring (11, 13) is divided into relay wirings 11, 13. The relay wire 11 has a common branch point 9 connected to one end thereof and an input of the clock buffer 12 connected to the other end thereof. The relay wiring 13 has one end connected to the output of the clock buffer 12 and the other end connected to the branch point 14.

  In addition, the buffer arrangement unit 53 depends on the number of branch points (branch point 6, common branch point 9, branch point 24) arranged from the input terminal IN to the cell groups 26-1 to 26-3 with respect to the block 20. Recognize that three stages of clock buffers are required. The first and second clock buffers correspond to the clock buffers 4-1 and 4-2, respectively. The buffer arrangement unit 53 connects the clock buffer 22 as a third clock buffer on the relay wiring (21, 23).

  In this case, the relay wiring (21, 23) is divided into the relay wirings 21, 23. The relay wire 21 has one end connected to the common branch point 9 and the other end connected to the input of the clock buffer 22. The relay wire 23 has one end connected to the output of the clock buffer 22 and the other end connected to the branch point 24.

  The delay time calculation unit 54 receives the clock CLK from the common branch point 9 to the cell groups 16-1 and 16-2 based on the delay caused by the relay wirings 11 and 13, the wiring groups 15-1 and 15-2, and the clock buffer 12. The delay time t10 until it is transmitted to is calculated. Further, the delay time calculation unit 54 receives the clock CLK from the common branch point 9 to the cell groups 26-1 to 26-26 based on the delays caused by the relay wirings 21 and 23, the wiring groups 25-1 to 25-3 and the clock buffer 22. -Delay time t20 until it is transmitted to -3.

  A known method is used as a method of calculating the delay times t10 and t20. For example, a preset delay time set in advance and a variation delay time due to variations in temperature, voltage, and manufacturing are taken into consideration for the wiring and clock buffer. The set delay time in the wiring is proportional to the length of the wiring.

  The delay time calculation unit 54 stores the coordinates from the common branch point 9 to the cell groups 16-1 and 16-2 and the delay time t10 in the delay information file 62. In addition, the delay time calculation unit 54 stores the coordinates from the common branch point 9 to the cell groups 26-1 to 26-3 and the delay time t 20 in the delay information file 62.

  The skew adjustment unit 55 refers to the delay information file 62 and executes a skew adjustment process for adjusting the delay time t10 and the delay time t20 to the same delay time. In the skew adjustment processing, the skew adjustment unit 55 connects the skew adjustment wirings 17 and 27 to the branch points 14 and 24, respectively, and connects the inputs of the dummy clock buffers 18 and 28 to the skew adjustment wirings 17 and 27, respectively. The outputs of the dummy clock buffers 18 and 28 are not connected.

  The skew adjustment wires 17 and 27 have a capacity for adjusting a clock skew generated between the branch points 14 and 24. For this reason, the clock skew can be reduced by executing the skew adjustment processing.

  For example, as shown in FIG. 6, the target cell 16-2 as one cell of the cell groups 16-1 and 16-2 and the target cell as one of the cell groups 26-1 to 26-3. It is assumed that the cell 26-1 exchanges data. Further, the target cells 16-2 and 26-1 are adjacent to each other. Since the target cells 16-2 and 26-1 are connected to the branch points 14 and 24, respectively, the delay time until the clock CLK is transmitted from the common branch point 9 to the target cell 16-2, and the clock CLK The delay time from the common branch point 9 to the transmission to the target cell 26-1 becomes large, and there may be a large clock skew due to delay variation. This clock skew is called a different path clock skew.

Therefore, the user designates the target cells 16-2 and 26-1 by operating the input device 43 of the user in order to check whether or not there is a different path clock skew. The target cell 16-2 is connected to the wiring 15-2 as a change candidate wiring in the wiring groups 15-1 and 15-2, and the target cell 26-1 is included in the wiring groups 25-1 to 25-3. The change candidate wiring is connected to the wiring 25-1. At this time, the target delay time calculation unit 56 transmits the clock CLK from the common branch point 9 to the target cell 16-2 based on the delays caused by the relay wirings 11 and 13, the change candidate wiring 15-2, and the clock buffer 12. The target delay time t10 _16-2 is calculated. Further, the target delay time calculation unit 56 transmits the clock CLK from the common branch point 9 to the target cell 26-1 based on the delays caused by the relay wirings 21 and 23, the change candidate wiring 25-1, and the clock buffer 22. The target delay time t20 _26-1 until is calculated.

As a calculation method of the target delay times t10 _16-2 and t20 _26-1 , a known method is used as in the calculation method of the delay times t10 and t20. As described above, for example, the above set delay time and variation delay time are considered in the above wiring and clock buffer, and the set delay time in the wiring is proportional to the length of the wiring.

The target delay time calculation unit 56 stores the coordinates from the common branch point 9 to the target cell 16-2 and the target delay time t10 _16-2 in the delay information file 62. In addition, the target delay time calculation unit 56 stores the coordinates from the common branch point 9 to the target cell 26-1 and the target delay time t 20 _26-1 in the delay information file 62.

As illustrated in FIG. 7, the connection changing unit 57 refers to the delay information file 62 and when the delay time difference between the target delay time t10 _16-2 and the target delay time t20 _26-1 is larger than the set time difference, Execute connection change processing. In the connection change process, the connection change unit 57 separates the target cell 26-1 from the other end of the change candidate wiring 25-1. Next, the connection changing unit 57 connects the input of the connection changing dummy clock buffer 29 as a dummy clock buffer to the other end of the change candidate wiring 25-1. The connection changing dummy clock buffer 29 has the same input capacity as that of the target cell 26-1. Further, the connection changing unit 57 connects the target cell 26-1 to the dummy clock buffer 18.

As described above, since the paths are different for the target cells 16-2 and 26-1, the above-mentioned different path clock skew is caused by different delay fluctuations for each path. Before the connection change process is executed, the common branch point is the common branch point 9 for the target cells 16-2 and 26-1. In this case, the non-common part with respect to each of the target cells 16-2 and 26-1 is from the common branch point 9 to the wirings 15-2 and 25-1. Therefore, the target delay time t10 _16-2 until the clock CLK is transmitted from the common branch point 9 to the target cell 16-2, and the time until the clock CLK is transmitted from the common branch point 9 to the target cell 26-1. The target delay time t20 _26-1 becomes large.

On the other hand, when the connection change process is executed, common branch points are the common branch point 9 and the branch point 14 for the target cells 16-2 and 26-1. In this case, a non-common part with respect to each of the target cells 16-2 and 26-1 is from the branch point 14 to the wirings 15-2 and 17. Therefore, the improvement target delay time t10 _16-2 ′ until the clock CLK is transmitted from the branch point 14 to the target cell 16-2 and the time until the clock CLK is transmitted from the branch point 14 to the target cell 26-1. The improvement target delay time t20 _26-1 ′ is significantly shorter than the above delay time. As a result, the different path clock skew caused by different delay fluctuations with respect to the non-common part is significantly shortened as compared with the above.

For example, before the connection change process is executed, the set delay time until the clock CLK is transmitted from the common branch point 9 to the target cell 16-2 as the target delay time t10 _16-2 is 3.0 [ns]. Suppose that Further, it is assumed that the set delay time until the clock CLK is transmitted from the common branch point 9 to the target cell 26-1 is 3.4 [ns] as the target delay time t20 _26-1 . In this case, the delay time difference between the target delay time t10 _16-2 and the target delay time t20 _26-1 is 3.4-3.0 = 0.4 [ns]. Therefore, when the range of the variation delay time is 90% to 110% of the set delay time, the maximum delay time difference including the influence of the variation is 3.4 × 1.1−3.0 × 0.9 = 1.04 [ns].

On the other hand, when the connection change process is executed, the set delay time until the clock CLK is transmitted from the branch point 14 to the target cell 16-2 is 1.0 [ns] as the improvement target delay time t10 _16-2 ′. Suppose that Also, it is assumed that the set delay time until the clock CLK is transmitted from the branch point 14 to the target cell 26-1 is 1.4 [ns] as the improvement target delay time t20 _26-1 '. In this case, the delay time difference between the target delay time t10 _16-2 and the target delay time t20 _26-1 is 1.4−1.0 = 0.4 [ns]. Therefore, when the range of the variation delay time is 90% to 110% of the set delay time, the maximum delay time difference including the influence of the variation is 1.4 × 1.1−1.0 × 0.9 = 0.64 [ns]. In this case, the difference between the maximum delay time difference including the effect of variation when the connection change process is executed and the maximum delay time difference including the effect of variation before the connection change process is executed is 1.04−. 0.64 = 0.4. Thereby, when the connection change process is executed, the delay time difference is shortened by 0.4 [ns] at the maximum compared to before the connection change process is executed. In other words, the delay difference that does not include the influence of variation does not change before and after the execution of the connection change process, whereas the delay difference including the variation is shortened by this connection change process. Yes.

  Further, when the connection change process is executed, the capacity of the relay wiring 13 and the skew adjustment wiring 17 is not different from that before the connection change process, and the wiring 25-1 has the same input capacity as the target cell 26-1. By connecting the connection changing dummy clock buffer 29, the capacity of the relay wiring 23 and the wiring 25-1 is not changed from that before the connection changing process is executed. Thereby, the delay time until the clock CLK is transmitted from the input terminal IN to the cell groups 16-1 and 16-2 and the clock CLK from the input terminal IN to the cell groups 26-2 and 26-3 are transmitted. The delay time does not change. That is, the connection change process is performed while the delay time up to the cell group not involved in the connection change is maintained.

  As described above, according to the semiconductor integrated circuit design method of the present invention, the connection change that shortens the non-common portion with respect to the target cells 16-2 and 26-1 is performed, so that the difference due to the delay variation due to the variation is caused. The path clock skew can be reduced.

  FIG. 8 is a flowchart showing the operation of the computer 40, showing the semiconductor integrated circuit design method of the present invention.

  The cell placement unit 51 performs a cell placement process in response to an operation of the input device 43 by the user (step S1). In step S1, the cell placement unit 51 first creates a placement information file 61 in response to the user's operation of the input device 43, and outputs the coordinate area 1 of the placement information file 61 to the output device 44 (display device). To display. Next, the cell arrangement unit 51 arranges the plurality of cells 16-1, 16-2, 26-1 to 26-3,... In the coordinate area 1 according to the operation of the input device 43 by the user.

  The tree placement unit 52 executes a tree placement process for placing the clock tree 2 in the coordinate area 1 (step S2).

  In step S2, the network constituted by the common wirings 5 and 7 is referred to as an input net (5, 7). A network constituted by the common wiring 8 and the relay wirings 11 and 21 is referred to as a common net (8, 11, 21). A network constituted by the relay wiring 13, the wiring groups 15-1 and 15-2, and the skew adjustment wiring 17 is referred to as a non-common net (13, 15-1, 15-2, 17). A network composed of the relay wiring 23, the wiring groups 25-1 to 25-3, and the skew adjustment wiring 27 is referred to as a non-common net (23, 25-1 to 25-3, 27).

  The buffer arrangement unit 53 refers to the clock tree 2 on the arrangement information file 61 and executes tree arrangement processing (step S3).

  In step S3, the buffer arrangement unit 53 requires three stages of clock buffers for the block 10 depending on the number of branch points arranged from the input terminal IN to the terminal cells (cell groups 16-1 and 16-2). Recognize that there is. The buffer arrangement unit 53 connects the clock buffer 4-1 as the first clock buffer before the input net (5, 7), and the clock buffer 4-2 as the second clock buffer as the input net (5, 7). 7) and the common net (8, 11, 21), and the clock buffer 12 as a third clock buffer is connected to the common net (8, 11, 21) and the non-common net (13, 15-1, 15-2, 17).

  In step S3, the buffer placement unit 53 sets three stages of clock buffers for the block 20 depending on the number of branch points placed from the input terminal IN to the terminal cells (cell groups 26-1 to 26-3). Recognize that it is necessary. The first and second clock buffers correspond to the clock buffers 4-1 and 4-2, respectively. The buffer arrangement unit 53 connects the clock buffer 22 as a third clock buffer between the common net (8, 11, 21) and the non-common net (23, 25-1 to 25-3, 27).

  The delay time calculation unit 54 calculates delays (set delay time / variation delay time) caused by the common nets (8, 11, 21), non-common nets (13, 15-1, 15-2, 17), and the clock buffer 12. Based on this, a delay time t10 until the clock CLK is transmitted from the common net (8, 11, 21) to the cell groups 16-1, 16-2 is calculated. The delay time calculation unit 54 also includes delays (set delay time / variation delay time) caused by the common nets (8, 11, 21), the non-common nets (23, 25-1 to 25-3, 27), and the clock buffer 22. ) To calculate a delay time t20 until the clock CLK is transmitted from the common net (8, 11, 21) to the cell groups 26-1 to 26-3 (step S4).

  In step S 4, the delay time calculation unit 54 stores the coordinates from the common branch point 9 to the cell groups 16-1 and 16-2 and the delay time t 10 in the delay information file 62. The coordinates of the cell groups 26-1 to 26-3 and the delay time t20 are stored in the delay information file 62.

  The skew adjustment unit 55 refers to the delay information file 62 and executes a skew adjustment process in order to adjust the delay time t10 and the delay time t20 to the same delay time (step S5).

  In step S5, the skew adjustment unit 55 is a dummy for adjusting the clock skew generated between the non-common nets (13, 15-1, 15-2, 17) (23, 25-1 to 25-3, 27). The clock buffers 18 and 28 are connected to the non-common nets (13, 15-1, 15-2, 17) (23, 25-1 to 25-3, 27), respectively.

  Here, in the case where there is no cell in the cell groups 16-1 and 16-2 and the cell groups 26-1 to 26-3 that exchanges data through different paths (step S6-NO), the skew adjustment unit 55 Updates the arrangement information file 61 and ends the design of the semiconductor integrated circuit.

  On the other hand, when there is a cell for transferring data through a different path among the cell groups 16-1 and 16-2 and the cell groups 26-1 to 26-3 (step S6-YES), the user Is specified. As described above, it is assumed that the adjacent target cells 16-2 and 26-1 among the cell groups 16-1, 16-2, and 26-1 to 26-3 transfer data.

In this case, the user operates the input device 43 to specify the target cells 16-2 and 26-1. At this time, the target delay time calculation unit 56 determines the delay (set delay time / variation) caused by the common net (8, 11, 21), the non-common net (13, 15-1, 15-2, 17), and the clock buffer 12. Based on the delay time), the target delay time t10 _16-2 until the clock CLK is transmitted from the common net (8, 11, 21) to the target cell _16-2 is calculated. The target delay time calculation unit 56 is a delay (set delay time / variation delay time) caused by the common net (8, 11, 21), the non-common net (23, 25-1 to 25-3, 27), and the clock buffer 22. Based on, the target delay time t20 _26-1 until the clock CLK is transmitted from the common net (8, 11, 21) to the target cell _26-1 is calculated (step S7).

In step S <b> 7, the target delay time calculation unit 56 stores the coordinates from the common branch point 9 to the target cell 16-2 and the target delay time t < _b > 10 _16-2 in the delay information file 62. In addition, the target delay time calculation unit 56 stores the coordinates from the common branch point 9 to the target cell 26-1 and the target delay time t 20 _26-1 in the delay information file 62.

The connection changing unit 57 refers to the delay information file 62 and checks whether or not the delay time difference between the target delay time t10 _16-2 and the target delay time t20 _26-1 is larger than the set time (step S8).

Here, when the delay time difference between the target delay time t10 _16-2 and the target delay time t20 _26-1 is equal to or smaller than the set time (step S8—NO), the connection changing unit 57 updates the arrangement information file 61, The design of the semiconductor integrated circuit is completed.

On the other hand, when the delay time difference between the target delay time t10 _16-2 and the target delay time t20 _26-1 is larger than the set time (step S8—YES), the connection changing unit 57 adjusts the different path clock skew. A connection change process is executed (step S9). However, this connection change process (step S9) is executed when the clock skew including variation is improved by the connection change.

  In step S9, the connection changing unit 57 replaces the target cell 26-1 with the connection change dummy clock buffer 29 having the same input capacity as that of the target cell 26-1, by using the non-common net (23, 25-1). To 25-3, 27). Further, the connection changing unit 57 connects the target cell 26-1 to the dummy clock buffer 18.

  As described above, according to the method for designing a semiconductor integrated circuit of the present invention, it is possible to reduce the different path clock skew caused by the delay variation.

The reason is that the paths are different for the target cells 16-2 and 26-1, and therefore the above-mentioned different path clock skew is caused by different delay fluctuations for each path. Before the connection change process (step S9) is executed, the common net is the common net (8, 11, 21) and the non-common net is non-common for the target cells 16-2 and 26-1. Net (13, 15-1, 15-2, 17) (23, 25-1 to 25-3, 27). In this case, the non-common part for each of the target cells 16-2 and 26-1 is the non-common net (13, 15-1, 15-2, 17) (23, 25-1 to 25-3, 27). is there. Therefore, the target delay time t10 _16-2 until the clock CLK is transmitted from the common net (8, 11, 21) to the target cell 16-2, and the clock CLK from the common net (8, 11, 21). The target delay time t20 _26-1 until it is transmitted to the cell 26-1 becomes large.

On the other hand, when the connection change process (step S9) is executed, the common nets for the target cells 16-2 and 26-1 are the common nets (8, 11, 21), and the non-common nets are It is a non-common net (13, 15-1, 15-2, 17). In this case, the non-common part for each of the target cells 16-2 and 26-1 is only the non-common net (13, 15-1, 15-2, 17). Therefore, the improvement target delay time t10 _16-2 ′ until the clock CLK is transmitted from the non-common net (13, 15-1, 15-2, 17) to the target cell 16-2 and the clock CLK are not common. The improvement target delay time t20 _26-1 ′ from the net (13, 15-1, 15-2, 17) to the target cell 26-1 is significantly shorter than the above delay time. In this way, by changing the connection that shortens the non-common portion for the target cells 16-2 and 26-1, it is possible to reduce the different path clock skew caused by different delay fluctuations for the non-common portion. Can do.

  Further, when the connection change process (step S9) is executed, the capacity of the non-common net (13, 15-1, 15-2, 17) is not different from that before the connection change process (step S9) is executed. By connecting the connection changing dummy clock buffer 29 having the same input capacity as the target cell 26-1 to the non-common net (23, 25-1 to 25-3, 27), the non-common net (23, 25 The capacities of −1 to 25-3 and 27) are the same as before the connection change process (step S9). Thereby, the delay time until the clock CLK is transmitted from the input terminal IN to the cell groups 16-1 and 16-2 and the clock CLK from the input terminal IN to the cell groups 26-2 and 26-3 are transmitted. The delay time does not change. That is, the connection change process (step S9) is performed while the delay time to the cell group not involved in the connection change is maintained.

FIG. 1 shows the configuration of a design system to which a conventional semiconductor integrated circuit design method is applied. FIG. 2 shows a semiconductor integrated circuit arranged in a coordinate area 101 which is a predetermined coordinate area (X, Y). FIG. 3 shows the configuration of a design system to which the semiconductor integrated circuit design method of the present invention is applied. FIG. 4 shows the arrangement information file 61. FIG. 5 shows the delay information file 62. FIG. 6 shows a semiconductor integrated circuit arranged in the coordinate area 1 which is a predetermined coordinate area (X, Y). FIG. 7 shows a semiconductor integrated circuit arranged in the coordinate area 1 which is a predetermined coordinate area (X, Y). FIG. 8 is a flowchart showing the operation of the computer 40, showing the semiconductor integrated circuit design method of the present invention.

Explanation of symbols

1 coordinate area,
2 clock tree,
3 Common wiring,
4-1, 4-2 Clock buffer,
5 Common wiring,
6 branch point,
7, 8 Common wiring,
9 Common branch point,
10 blocks,
11 Relay wiring,
12 clock buffers,
13 Relay wiring,
14 branch point,
15-1, 15-2 wiring,
16-1, 16-2 cells,
17 Skew adjustment wiring,
18 Dummy clock buffer,
20 blocks,
21 Relay wiring,
22 clock buffer,
23 Relay wiring,
24 branch point,
25-1 to 25-3 wiring,
26-1 to 26-3 cells,
27 Wiring for skew adjustment,
28 dummy clock buffer,
29 Dummy clock buffer for connection change,
31-34 blocks,
40 computers,
41 storage unit,
42 CPU (execution unit),
43 input devices,
44 output device,
45 design tools,
50 computer programs,
51 cell placement section,
52 Tree placement section,
53 Buffer placement section,
54 delay time calculator,
55 Skew adjustment unit,
56 target delay time calculation unit,
57 Connection change part,
60 files,
61 Placement information file,
62 Delay information file,

Claims (13)

A cell placement step of placing a plurality of cells operating in accordance with a clock in a coordinate area;
The input net to which the clock is input, the first and second non-common nets in which the first and second cell groups as the plurality of cells are connected in parallel, the input net and the first and second non-nets, respectively. A tree placement step of placing a clock tree including a common net connected to the common net in the coordinate area;
A buffer placement step of connecting a clock buffer between the input net and the common net, and between the common net and the first and second non-common nets;
A skew adjusting step of connecting first and second dummy clock buffers for adjusting a clock skew generated between the first and second non-common nets to the first and second non-common nets, respectively;
When data is transferred between the first and second target cells as one cell of the first and second cell groups, the first and second target cells are respectively connected to the first and second non-common networks. In order to adjust the different path clock skew due to delay variation caused by being connected to
A first connection changing step of connecting a connection change dummy clock buffer to the second non-common net instead of the second target cell;
A method for designing a semiconductor integrated circuit, comprising: a second connection changing step for connecting the second target cell to the first dummy clock buffer. The method for designing a semiconductor integrated circuit according to claim 1,
Based on the delays caused by the common net, the first and second non-common nets, and the clock buffer, the first and second times until the clock is transmitted from the common net to the first and second cell groups, respectively. 2 delay time calculating step for calculating delay time;
Performing the skew adjustment step to adjust the first delay time and the second delay time to the same delay time as the clock skew adjustment; and
When data is exchanged between the first and second target cells, the clock is transferred from the common net based on the delays caused by the common net, the first and second non-common nets, and the clock buffer, respectively. A target delay time calculating step for calculating first and second target delay times until the first and second target cells are transmitted;
When the delay time difference between the first target delay time and the second target delay time is larger than a set time difference, the step of executing the first and second connection changing steps as the adjustment of the different path clock skew is further performed. A method for designing a semiconductor integrated circuit. A cell placement step of placing a plurality of cells operating in accordance with a clock in a coordinate area;
The clock is input to one end and the common branch point is connected to the other end, the common branch point is connected to the one end, and the first and second branch points are connected to the other end. First, second relay wiring, and the first and second branch points connected to the first and second branch points at one end thereof, and the first and second cell groups as the plurality of cells connected to the other end, respectively. A tree placement step of placing a clock tree including a wiring group in the coordinate area;
A buffer arrangement step of connecting a clock buffer on the common line and on the first and second relay lines;
First and second skew adjustment wirings having capacitances for adjusting clock skew generated between the first and second branch points are connected to the first and second branch points, respectively. A skew adjustment step of connecting the first and second dummy clock buffers to the skew adjustment wiring;
When the first and second target cells transfer data as one cell of the first and second cell groups, the first and second target cells are connected to the first and second branch points, respectively. In order to adjust the different path clock skew due to the delay variation caused by
In the second wiring group, the second target cell is disconnected from the other end of the change candidate wiring to which the second target cell is connected, and a connection change dummy clock buffer is provided at the other end of the change candidate wiring. A first connection changing step for connecting;
A method for designing a semiconductor integrated circuit, comprising: a second connection changing step for connecting the second target cell to the first dummy clock buffer. The method of designing a semiconductor integrated circuit according to claim 3,
Until the clock is transmitted from the common branch point to the first and second cell groups based on delays caused by the first and second relay wirings, the first and second wiring groups, and the clock buffer, respectively. A delay time calculating step for calculating the first and second delay times of
Performing the skew adjustment step to adjust the first delay time and the second delay time to the same delay time as the clock skew adjustment; and
When transferring data between the first and second target cells, the first and second relay wirings, the wiring of the first wiring group to which the first target cells are connected, and Targets for calculating the first and second target delay times until the clock is transmitted from the common branch point to the first and second target cells based on delays caused by the change candidate wiring and the clock buffer. A delay time calculating step;
When the delay time difference between the first target delay time and the second target delay time is larger than a set time difference, the step of executing the first and second connection changing steps as the adjustment of the different path clock skew is further performed. A method for designing a semiconductor integrated circuit. In the design method of the semiconductor integrated circuit in any one of Claims 1-4,
The method of designing a semiconductor integrated circuit, wherein the connection-changing dummy clock buffer has an input capacity that is the same as an input capacity of the second target cell. In the design method of the semiconductor integrated circuit in any one of Claims 1-5,
A method of designing a semiconductor integrated circuit in which the first and second target cells are adjacent to each other. A computer program installed in a computer for designing a semiconductor integrated circuit,
A cell placement step of placing a plurality of cells operating in accordance with a clock in a coordinate area;
The input net to which the clock is input, the first and second non-common nets in which the first and second cell groups as the plurality of cells are connected in parallel, the input net and the first and second non-nets, respectively. A tree placement step of placing a clock tree including a common net connected to the common net in the coordinate area;
A buffer placement step of connecting a clock buffer between the input net and the common net, and between the common net and the first and second non-common nets;
A skew adjusting step of connecting first and second dummy clock buffers for adjusting a clock skew generated between the first and second non-common nets to the first and second non-common nets, respectively;
When data is transferred between the first and second target cells as one cell of the first and second cell groups, the first and second target cells are respectively connected to the first and second non-common networks. In order to adjust the different path clock skew due to delay variation caused by being connected to
A first connection changing step of connecting a connection change dummy clock buffer to the second non-common net instead of the second target cell;
A computer program for causing the computer to execute each step of a second connection changing step of connecting the second target cell to the first dummy clock buffer. The computer program according to claim 7, wherein
Based on the delays caused by the common net, the first and second non-common nets, and the clock buffer, the first and second times until the clock is transmitted from the common net to the first and second cell groups, respectively. 2 delay time calculating step for calculating delay time;
Performing the skew adjustment step to adjust the first delay time and the second delay time to the same delay time as the clock skew adjustment; and
When data is transferred between the first and second target cells, the clock is shared by the common net, the delay by the first and second non-common nets, and the delay by the clock buffer, respectively. A target delay time calculating step of calculating first and second target delay times until the first and second target cells are transmitted from the net;
Each of the steps of executing the first and second connection changing steps as the adjustment of the different path clock skew when a delay time difference between the first target delay time and the second target delay time is larger than a set time difference. A computer program for causing the computer to further execute steps. A computer program installed in a computer for designing a semiconductor integrated circuit,
A cell placement step of placing a plurality of cells operating in accordance with a clock in a coordinate area;
The clock is input to one end and the common branch point is connected to the other end, the common branch point is connected to the one end, and the first and second branch points are connected to the other end. First, second relay wiring, and the first and second branch points connected to the first and second branch points at one end thereof, and the first and second cell groups as the plurality of cells connected to the other end, respectively. A tree placement step of placing a clock tree including a wiring group in the coordinate area;
A buffer arrangement step of connecting a clock buffer on the common line and on the first and second relay lines;
First and second skew adjustment wirings having capacitances for adjusting clock skew generated between the first and second branch points are connected to the first and second branch points, respectively. A skew adjustment step of connecting the first and second dummy clock buffers to the skew adjustment wiring;
When the first and second target cells transfer data as one cell of the first and second cell groups, the first and second target cells are connected to the first and second branch points, respectively. In order to adjust the different path clock skew due to the delay variation caused by
In the second wiring group, the second target cell is disconnected from the other end of the change candidate wiring to which the second target cell is connected, and a connection change dummy clock buffer is provided at the other end of the change candidate wiring. A first connection changing step for connecting;
A computer program for causing the computer to execute each step of a second connection changing step of connecting the second target cell to the first dummy clock buffer. The computer program according to claim 9,
Until the clock is transmitted from the common branch point to the first and second cell groups based on delays caused by the first and second relay wirings, the first and second wiring groups, and the clock buffer, respectively. A delay time calculating step for calculating the first and second delay times of
Performing the skew adjustment step to adjust the first delay time and the second delay time to the same delay time as the clock skew adjustment; and
When transferring data between the first and second target cells, the first and second relay wirings, the wiring of the first wiring group to which the first target cells are connected, and Targets for calculating the first and second target delay times until the clock is transmitted from the common branch point to the first and second target cells based on delays caused by the change candidate wiring and the clock buffer. A delay time calculating step;
Each of the steps of executing the first and second connection changing steps as the adjustment of the different path clock skew when a delay time difference between the first target delay time and the second target delay time is larger than a set time difference. A computer program for causing the computer to further execute steps. In the computer program in any one of Claims 7-10,
The connection change dummy clock buffer is a computer program having the same input capacity as that of the second target cell. The computer program according to any one of claims 7 to 11,
A computer program in which the first and second target cells are adjacent.   A computer in which the computer program according to any one of claims 7 to 12 is installed.

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