JP2008186116A - Internal register information recording device and image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To create history information showing in what manner a system is being operated during abnormality in a device without separately providing a CPU. <P>SOLUTION: A CPU 101 writes information preliminarily written in an internal register of each unit to a Back Up SRAM 105 on switching the operation mode of the image processor 1 between a general operation mode and an energy-saving mode. As a result, even if abnormality is caused in the processor 1, register information showing the operating state just before can be read and used to analyze the cause of the abnormality since the information is stored in the Back Up SRAM 105. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for generating a history of operating conditions of an electronic device.

In an electronic device, in order to reduce power consumption during a period when the electronic device is not used, there is a technique for stopping energization of the electronic device or stopping an operation of a functional module not used in the electronic device. At this time, the difference in the power consumption of the device between the energy saving mode and the normal operation mode becomes large, and the supply voltage supplied from the power supply fluctuates when switching between the modes, causing a failure in the operation of the electronic device. There is a risk.
In addition, in order to analyze the cause when an abnormality occurs in the control unit provided in the electronic device due to fluctuations in the supply voltage of the power supply, it is necessary to acquire information on the operation of the CPU and peripheral devices of the control unit when the abnormality occurs There is. However, if an abnormality occurs that prevents the CPU controlling the device from responding to external control, the device information could not be acquired and the cause of the abnormality could not be analyzed. .
In order to solve the above-described problems, Patent Document 1 provides a second CPU and memory in addition to the CPU responsible for control, and how the system operates immediately before an abnormality occurs. A technique for generating history information indicating whether or not using a second CPU and a memory is disclosed.
JP 2004-310514 A

However, with the technology disclosed in Patent Document 1, it is possible to acquire information on the CPU and peripheral devices of the control unit in which an abnormality has occurred using the other CPU, but what is the CPU responsible for control? Since a CPU and a memory are provided separately, there is a problem that costs increase.
In view of the above problems, an object of the present invention is to provide an internal register information recording apparatus that stores information indicating how the system was operating immediately before an abnormality occurred in the apparatus.

  A first configuration of an internal register information recording apparatus according to the present invention includes a CPU (Central Processing Unit) having one or a plurality of registers in which information being processed is recorded, a nonvolatile data recording unit, and an electronic device. Receiving means for receiving a notification signal indicating the operating status of the electronic device; a list for associating one or more operating statuses performed by the electronic device with the one or more registers; and the receiving means from the electronic device A register specifying unit for comparing the list with respect to the received notification signal to specify a corresponding register and recording information in the specified register in the data recording unit;

  A second configuration of the internal register information recording apparatus according to the present invention includes, in the first configuration, one or a plurality of peripheral devices having one or a plurality of registers in which information being processed is recorded. The written register includes a register of the peripheral device.

  According to a third configuration of the internal register information recording apparatus of the present invention, in the first configuration, the notification signal is a signal indicating that the electronic device is switched from a power mode with high energy consumption to an energy saving mode with low energy consumption. It is characterized by being.

  According to a fourth configuration of the internal register information recording apparatus of the present invention, in the first configuration, the notification signal is a signal indicating that the electronic device switches from an energy saving mode with low energy consumption to a power mode with high energy consumption. It is characterized by being.

  According to a fifth configuration of the internal register information recording apparatus of the present invention, in the first configuration, the list is stored in a DRAM (Dynamic Random Access Memory) that temporarily stores information when the CPU performs processing. The address is included as the register.

  According to a sixth configuration of the internal register information recording apparatus of the present invention, in the first configuration, there is provided time measuring means for measuring time, and the register specifying means timed the information in the register by the time measuring means. It is recorded in the data recording means together with time.

  A first configuration of an image processing device according to the present invention includes the internal register recording device according to any one of claims 1 to 6 and image processing means for processing an image, wherein the electronic device includes the image processing device. It is a processing means.

  According to a second configuration of the image processing apparatus of the present invention, in the image processing apparatus according to the first aspect, the notification signal is a signal indicating that the image processing unit starts forming an image. And

  According to the internal register information recording apparatus according to the present invention, it is possible to obtain history information indicating how the system was operating immediately before an abnormality occurred in the apparatus with a simple configuration without providing a separate CPU. Can be used to analyze the cause of abnormalities.

(A: Configuration)
The best mode for carrying out the present invention will be specifically described with reference to the drawings.
FIG. 1 is a diagram showing a configuration of an image processing apparatus 1 provided with an internal register information recording apparatus according to the present invention. The image processing apparatus 1 is a multi-function apparatus that provides functions such as copying, a scanner, a printer, and a FAX. The external power supply (5 V) is stepped down to 3.3 V by the DC / DC converter 2 and supplied to each part of the image processing apparatus 1.

A CPU 101 shown in the figure executes various programs stored in an HDD (Hard Disk Drive) 104 and controls the operation of other components. Note that the CPU 101 includes registers (registers A ₁ , A ₂ , A ₃ ...) As with a general CPU. These registers include an instruction register that holds the contents of instructions executed by the CPU 101, an accumulator that holds the results of operations performed by the CPU 101, an address register that holds addresses when reading and writing various memories, and the image processing apparatus 1. Peripheral control registers for holding information on the operation status and peripheral devices provided in the image processing apparatus 1 are included.

An RTC (Real-Time Clock) 102 is a clock that measures the current time and outputs the time information. The RTC 102 is supplied with a voltage from the DC / DC converter 2 and is separately provided with a power source (not shown), and continues to operate even when the voltage from the DC / DC converter 2 is stopped. ing. Note that the information represented by the RTC 102 may be information that can specify a time such as an elapsed time from power-on or a value representing standard time.
The DRAM 103 is used as a working area by the CPU 101 such as loading a program being executed. In other words, information handled by the CPU 101 when the CPU 101 performs various processes is temporarily stored in the DRAM 103.

The image processing chip 108 reads out image data acquired via an image data acquisition unit (not shown) or a communication network from the DRAM 103 and performs predetermined image processing. The image processing chip 108 has registers C ₁ , C ₂ , C ₃ ..., And various settings and processing contents when the image processing chip 108 performs processing are written in each register.
The I / O processing chip 107 receives an instruction input via an input / output device (not shown), transmits the instruction content to the CPU 101, and outputs image data subjected to image processing to the input / output device. The I / O processing chip 107 has registers B ₁ , B ₂ , B ₃ ..., And various settings and processing contents when the I / O processing chip 107 performs processing are written in each register. .

Here, power supply to the image processing apparatus 1 will be described. There are two modes of power supply: a normal operation mode and an energy saving mode.
The normal operation mode is a mode in which normal power is supplied when the image processing apparatus 1 performs various processes, and power is supplied to each unit of the image processing apparatus 1 via the DC / DC converter 2. On the other hand, the energy saving mode is a mode in which power is supplied to the image processing apparatus 1 but energy consumption is suppressed by stopping the supply of power to most of the components of the image processing apparatus 1. Even in the energy saving mode, electric power is supplied to some components (not shown) such as a portion that performs the process of returning to the normal operation mode. Thus, the normal operation mode is a power mode that normally consumes energy, and the energy saving mode is a power mode that consumes less energy.

  The operation mode is switched by the operation unit 106, the energy saving mode transition timer 109, and the like. The energy saving mode transition timer 109 does not receive any instruction to perform image processing via a communication network (not shown) without any operation on the operation unit 106 for a predetermined time when the image processing apparatus 1 is in the normal operation mode. In this case, a signal for instructing switching to the energy saving mode (hereinafter referred to as an energy saving mode transition request interrupt) is output. When the CPU 101 receives the energy saving mode transition request interrupt, the CPU 101 disconnects the circuit that supplies power to a predetermined part and switches the image processing apparatus 1 to the energy saving mode.

  When the CPU 101 is operated when the image processing apparatus 1 is in the energy saving mode or receives an instruction to perform image processing via a communication network (not shown), the power supply that was disconnected in the energy saving mode is supplied. The circuit is connected and the image processing apparatus 1 is switched to the normal operation mode.

Returning to FIG. 1 again, the HDD 104 is a storage means having a sufficient storage capacity, and stores various programs. Further, the HDD 104 is provided with an area for holding a register list to be recorded. Here, the recording target register list is a description in which the status of the operation (event) of the image processing apparatus 1 and the register used in the operation (event) are associated with each other. It is used to back up data in preparation for an abnormal operation. More specifically, in the register list to be recorded, in addition to various registers included in the CPU 101, various registers included in the I / O processing chip 107 and the image processing chip 108 that are peripheral devices are included in the operation status of the image processing apparatus 1. Correspondingly written. FIG. 3 shows an example of a register list to be recorded. For example, registers A ₁ , A ₂ , B ₂ , and C ₂ are associated with an operation (event) in which the image processing apparatus 1 switches the operation mode. ing. This means that the registers A ₁ , A ₂ , B ₂ , and C ₂ are used when the image processing apparatus 1 switches the operation mode.

A Back Up SRAM (Static Random Access Memory) 105 is a cache memory, and when an abnormal operation occurs in the image processing apparatus 1, information written in the registers listed in the recording target register list is written. Note that the Back Up SRAM 105 is supplied with a voltage from the DC / DC converter 2 and is provided with a separate power source (not shown), so that the memory is stored even when the voltage from the DC / DC converter 2 is stopped. -Make output possible.
Each unit of the image processing apparatus 1 described above is connected by a bus 110 and can exchange signals with each other.

(B: Operation)
Hereinafter, processing performed by the image processing apparatus 1 will be described. It is assumed that the recording target register list shown in FIG. It is assumed that the image processing apparatus 1 is performing image processing at the start of the following operation example. Accordingly, programs, data, operation statuses, and the like being processed are written in various memories and registers.

  FIG. 2 is a flowchart showing a flow of processing performed by the image processing apparatus 1. The CPU 101 determines whether or not an energy saving mode transition request interrupt has been received from the energy saving mode transition timer 109 (step SA100). While the image processing apparatus 1 is performing image processing, the determination result in step SA100 is “No”, and step SA100 is repeated. If the image processing apparatus 1 is not instructed to continue processing for a predetermined time, the energy saving mode transition timer 109 outputs an energy saving mode transition request interrupt. When the CPU 101 receives the energy saving mode transition request interrupt, the determination result in step SA100 is “Yes” and the process proceeds to step SA110.

In step SA <b> 110, the CPU 101 reads the recording target register list stored in the HDD 104, reads information written in the registers listed in the list, and writes the read information to the Back Up SRAM 105. In this operation example, in the register list to be recorded, since the registers A ₁ , A ₂ , B ₂ , and C ₂ are associated with the switching of the operation mode, the registers A ₁ , A ₂ , B ₂ , and Information written in C ₂ is written in the Back Up SRAM 105. At this time, the time information read from the RTC 102 is recorded in the Back Up SRAM 105 together with the register information.

  In subsequent step SA120, CPU 101 determines whether or not the process of writing the register information to back up SRAM 105 has been completed. If the determination result in step SA120 is “No”, the determination result in step SA120 is “No” and step SA120 is repeated until the process is completed. When the process is completed, the determination result in step SA120 is “Yes”, and the CPU 101 controls the power supply circuit to each unit of the image processing apparatus 1 and switches to the energy saving mode.

  In step SA130, the CPU 101 determines whether the operation unit 106 is operated or an instruction to perform some processing is received via a communication network (not shown). If the CPU 101 has not received any of the above instructions, the determination result of step SA130 is “No”, and the process of step SA130 is repeated. When the image processing apparatus 1 receives any instruction, the determination result in step SA130 is “Yes”, and the process proceeds to step SA140.

In step SA140, the CPU 101 reads the recording target register list, and writes the register information set in the list to the Back Up SRAM 105. In this operation example, in the register list to be recorded, since the registers A ₁ , A ₂ , B ₂ , and C ₂ are associated with the switching of the operation mode, the registers A ₁ , A ₂ , B ₂ , and Information written in C ₂ is written in the Back Up SRAM 105. At this time, the time information read from the RTC 102 is written in the Back Up SRAM 105 together with the time information.

  In step SA150, the CPU 101 determines whether or not the processing for writing the register information to the Back Up SRAM 105 is completed. If the determination result in step SA150 is “No”, step SA150 is repeated until the process is completed. When the process is completed, the determination result in step SA150 is “Yes”, and the CPU 101 connects the power supply circuit disconnected in the energy saving mode and switches to the normal operation mode.

  In step SA160, the CPU 101 determines whether the image processing apparatus 1 is powered off. When the power of the image processing apparatus 1 is turned off, the determination result in step SA160 is “Yes”, and the present process ends. On the other hand, if the determination result in step SA160 is “No”, the process is performed again from step SA100.

  By performing the above processing, the CPU 101 switches the operation mode after confirming that the register information written in the recording target register list is recorded in the Back Up SRAM 105. Therefore, even if some abnormality occurs at the time of switching the operation mode, register information reflecting the operation state of the image processing apparatus 1 immediately before the abnormality occurs is stored in the Back Up SRAM 105. The maintenance service person can analyze the recorded information later to help elucidate the cause of the failure.

(C: Modification)
As mentioned above, although one Embodiment of this invention was described, you may implement in the various aspects as described below.

(1) Although the case where the image processing apparatus is caused to perform processing characteristic of the present invention has been described in the above embodiment, the application target of the present invention is not limited to the image processing apparatus. The present invention can be applied to any device as long as it is an electronic device controlled by a CPU.

(2) In the above embodiment, the case has been described in which the image processing apparatus 1 has a function characteristic of the present invention. However, the apparatus according to the present invention has a function independent of the image processing apparatus 1 (hereinafter referred to as a specialized recording apparatus), and the specialized recording apparatus is connected to an apparatus specialized in image processing (hereinafter referred to as an image processing specialized apparatus). Thus, the present invention may be implemented. In that case, it is preferable to exchange signals between the image processing specialized device and the recording specialized device as follows. That is, the image processing specialized device outputs a signal indicating the operation mode to the recording specialized device. Then, the recording specialized apparatus selects a register corresponding to the operation mode in the recording target register list stored in the storage unit, and sends a signal to the image processing specialized apparatus to output the information of the register. The image processing specialized device reads information from the designated register and outputs the information to the recording specialized device. The specialized recording apparatus writes the received information in the storage unit. As described above, the present invention can be realized without applying a register information recording device to each electronic device by applying the specialized recording device to various electronic devices other than the image processing specialized device. Can be

(3) In the above embodiment, a case has been described in which most of the functions characteristic of the internal register information recording apparatus according to the present invention are realized by software modules. However, the hardware modules carrying the above functions are combined. You may make it comprise.

(4) In the above-described embodiment, a case has been described in which register information is recorded when the operation mode of the image processing apparatus 1 is switched. However, the opportunity to save the register information is not limited to switching of the operation mode. For example, the processing may be performed according to the type of processing executed by the image processing apparatus 1. Specifically, immediately after the image processing apparatus 1 is turned on, when starting image forming processing, when starting transmission or reception of a FAX document, when starting receiving print data from the outside of the image processing apparatus 1 When scanning is started, transmission of scan data may be started, and the processing contents and registers may be written in correspondence in the recording target register list.
Further, register information may be stored when the image processing apparatus 1 generates a system error. In such a case, the CPU 101 has a function of detecting the occurrence of a system error, and when the system error is detected, the register information may be saved.
When the electronic device to which the present invention is applied is an electronic device other than the image processing apparatus, register information may be recorded in accordance with the type of processing executed by the electronic device.

(5) In the above embodiment, the case where the register information is recorded in any direction when switching between the energy saving mode and the normal operation mode has been described. However, the register information may be recorded only for one of the transition from the energy saving mode to the normal operation mode or from the normal operation mode to the energy saving mode.

(6) In the above-described embodiment, the case has been described in which information in the internal register is written in the Back Up SRAM 105 that is driven by an independent power source, thereby preventing information loss when the operation is abnormal. However, the register information may be written in a nonvolatile storage device such as an HDD. In short, it is only necessary to record the register information in a storage device having such a feature that information is not lost even if a power failure of the image processing apparatus 1 occurs.

(7) In the above embodiment, the case of recording the internal register information of the CPU and peripheral devices has been described. However, the information to be recorded is not limited to the internal register, and may be information written in a working area of a CPU such as a DRAM.

(8) In the above embodiment, when writing the register list to the Back Up SRAM 105, the time at that time is read from the RTC 102 and written together with the data. In that case, the time when the writing process is completed may be written together.

It is a block diagram which shows the structure of the image processing apparatus which concerns on this invention. It is the flowchart which showed the process which an image processing apparatus performs. It is an example of a record object register list.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Image processing apparatus, 2 ... DC / DC converter, 101 ... CPU, 102 ... RTC, 103 ... DRAM, 104 ... HDD, 105 ... Back Up SRAM, 106 ... Operation part, 107 ... I / O processing chip, 108 ... Image processing chip 109 ... Energy saving mode transition timer 110 ... Bus

Claims (8)

A CPU (Central Processing Unit) having one or more registers in which information being processed is recorded;
Non-volatile data recording means;
Receiving means for receiving a notification signal indicating the operating status of the electronic device from the electronic device;
A list associating one or more operation states performed by the electronic device with the one or more registers;
A register identifying unit for identifying the corresponding register by collating the list with respect to the notification signal received from the electronic device by the receiving unit, and recording information in the identified register in the data recording unit. An internal register information recording device. Having one or more peripheral devices having one or more registers in which information being processed is recorded;
The internal register information recording apparatus according to claim 1, wherein the register written in the list includes a register included in the peripheral device. The internal register information recording apparatus according to claim 1, wherein the notification signal is a signal indicating that the electronic device is switched from a power mode with high energy consumption to an energy saving mode with low energy consumption. The internal register information recording apparatus according to claim 1, wherein the notification signal is a signal indicating that the electronic device is switched from an energy saving mode with low energy consumption to a power mode with high energy consumption. 2. The internal register information according to claim 1, wherein the list includes an address on a DRAM (Dynamic Random Access Memory) that temporarily stores information when the CPU performs processing as the register. Recording device. It has time measuring means to measure time,
The internal register information recording apparatus according to claim 1, wherein the register specifying unit records information in the register in the data recording unit together with a time measured by the time measuring unit. An internal register information recording device according to any one of claims 1 to 6,
Image processing means for processing an image,
An image processing apparatus, wherein the electronic device is the image processing means. The image processing apparatus according to claim 7, wherein the notification signal is a signal indicating that the image processing unit starts to form an image.

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