JP2008182196A - Electronic device package and its manufacturing method - Google Patents

Electronic device package and its manufacturing method Download PDF

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Publication number
JP2008182196A
JP2008182196A JP2007309578A JP2007309578A JP2008182196A JP 2008182196 A JP2008182196 A JP 2008182196A JP 2007309578 A JP2007309578 A JP 2007309578A JP 2007309578 A JP2007309578 A JP 2007309578A JP 2008182196 A JP2008182196 A JP 2008182196A
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substrate
electronic device
cover
electrode
device package
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JP2007309578A
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JP5072555B2 (en
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Kazuji Azuma
和司 東
Shinji Ishitani
伸治 石谷
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2007309578A priority Critical patent/JP5072555B2/en
Priority to US11/952,173 priority patent/US8077447B2/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

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Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic device package by which thinning and high reliability are attained. <P>SOLUTION: In the electronic device package, first and second plate-like cover substrates (15, 16) are joined on an upper and a lower parts of a plate-like sensor substrate 14 with the sensor substrate located between the first and the second cover substrates. The sensor substrate 14 includes: a first detecting portion 20A and a second detecting portion 20B as a detecting means 19; an outer peripheral portion of the sensor substrate 14 as a frame surrounding the detecting means 19 through space 17; at least two beams 18a, 18b joining the detecting means 19 with the outer peripheral portion of the sensor substrate 14; and an electrode 21 which is disposed at the outer peripheral portion of the sensor substrate 14, and is electrically connected to the detecting means 19. The first cover substrate 15 or the second cover substrate 16 includes a throughhole 25 in which an inner wall of its end face is brought into contact with at least one portion of the electrode 21 to attain such thinning and high reliability. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、加速度センサーなどの電子素子パッケージとその製造方法に関するものである。   The present invention relates to an electronic element package such as an acceleration sensor and a manufacturing method thereof.

図19に示す特許文献1などに記載されている電子素子パッケージは、凹部12を有したパッケージ内に加速度センサチップ1が収容され、加速度センサチップ1は、中央に基板2に固定された支持部3と、支持部3の周囲に配置された錘部4を有している。錘部4は、支持部3の上部に一端側が接続された検出ビーム5の他端側に結合して吊り下げられている。支持部3と錘部4および検出ビーム5はマイクロマシーン技術により、半導体基板で一体に形成されている。   In the electronic element package described in Patent Document 1 shown in FIG. 19 and the like, the acceleration sensor chip 1 is accommodated in a package having a recess 12, and the acceleration sensor chip 1 is supported by a substrate 2 fixed at the center. 3 and a weight portion 4 disposed around the support portion 3. The weight portion 4 is suspended by being coupled to the other end side of the detection beam 5 whose one end side is connected to the upper portion of the support portion 3. The support portion 3, the weight portion 4, and the detection beam 5 are integrally formed of a semiconductor substrate by a micromachine technique.

検出ビーム5の上部には、錘部4に加わる加速度による歪みに対応して出力信号に変化を与える検出素子6が形成されている。基板2は接着剤7によりパッケージ内底面に固定されている。   A detection element 6 that changes the output signal corresponding to the distortion caused by the acceleration applied to the weight portion 4 is formed above the detection beam 5. The substrate 2 is fixed to the inner bottom surface of the package with an adhesive 7.

支持部3の上端面に形成されたボンディングパッド8と検出素子6は、図示しないリードにより電気的に接続されている。ボンディングパッド8は、パッケージ側に形成されている外部引出端子9に金線10により接続されている。外部引出端子9はパッケージ壁に沿って形成された導電膜によりパッケージ底面に形成された電極端子11と接続されている。13はキャップである。   The bonding pad 8 formed on the upper end surface of the support portion 3 and the detection element 6 are electrically connected by a lead (not shown). The bonding pad 8 is connected to an external lead terminal 9 formed on the package side by a gold wire 10. The external lead terminal 9 is connected to an electrode terminal 11 formed on the bottom surface of the package by a conductive film formed along the package wall. 13 is a cap.

また、特許文献2には、図20に示すように、電子素子51が形成された素子基板52の一方の面に、電子素子51を取り囲むように隔壁部53を形成し、貫通電極54を有するカバー基板55によって隔壁部53の開口を閉塞して電子素子51を封止している。56はカバー基板55の外側に形成された電極で、貫通電極54と導通して電子素子51の電極を外部に引き出しているものが記載されている。   Further, in Patent Document 2, as shown in FIG. 20, a partition wall 53 is formed on one surface of an element substrate 52 on which an electronic element 51 is formed so as to surround the electronic element 51, and a through electrode 54 is provided. The electronic device 51 is sealed by closing the opening of the partition wall portion 53 with the cover substrate 55. Reference numeral 56 denotes an electrode formed on the outside of the cover substrate 55, which is electrically connected to the through electrode 54 and leads out the electrode of the electronic element 51 to the outside.

また、図21と図22は特許文献3に記載されている電子素子パッケージを示す。図21は電子素子パッケージの下側ガラス基板81と上側ガラス基板82を貼り合わせる前の分解図、図22は貼り合わせた後の図21のX−X線に沿う断面図である。   21 and 22 show an electronic element package described in Patent Document 3. FIG. FIG. 21 is an exploded view before the lower glass substrate 81 and the upper glass substrate 82 are bonded together, and FIG. 22 is a cross-sectional view taken along the line XX of FIG. 21 after the bonding.

下側ガラス基板81に形成された角速度検出部83は、両端83a,83bが下側ガラス基板81に支持され、中間83cが下側ガラス基板81に接触していない可動側となっている。上側ガラス基板82は、下側ガラス基板81の外周部に設けられた枠部84に接合されてハーメチックシール(hermetic seal)されている。外部引き出し電極は、枠部84とは別に信号出力部85a,85b,85cが下側ガラス基板81に形成されており、信号出力部85a,85b,85cが上側ガラス基板82に張り合わされてビアホール86で外部に引き出されている。
特開2006−170856号公報 特開平6−318625号公報 特開2000−186931号公報
The angular velocity detection unit 83 formed on the lower glass substrate 81 is a movable side where both ends 83 a and 83 b are supported by the lower glass substrate 81 and the middle 83 c is not in contact with the lower glass substrate 81. The upper glass substrate 82 is bonded to a frame portion 84 provided on the outer peripheral portion of the lower glass substrate 81 to be hermetic sealed. In the external lead electrode, signal output portions 85 a, 85 b, 85 c are formed on the lower glass substrate 81 separately from the frame portion 84, and the signal output portions 85 a, 85 b, 85 c are bonded to the upper glass substrate 82 to form via holes 86. It is pulled out to the outside.
JP 2006-170856 A JP-A-6-318625 JP 2000-186931 A

特許文献1の構成では、支持部3と錘部4および検出ビーム5をマイクロマシーン技術によって半導体基板で一体に形成しても、薄型化が困難である。これに対して特許文献2,特許文献3の構成では、薄型化を実現できるが、ハーメチックシール構造の信頼性の向上が要求されているのが現状である。   In the configuration of Patent Document 1, it is difficult to reduce the thickness even if the support portion 3, the weight portion 4, and the detection beam 5 are integrally formed of a semiconductor substrate by a micromachine technique. On the other hand, in the configurations of Patent Documents 2 and 3, it is possible to reduce the thickness, but it is currently required to improve the reliability of the hermetic seal structure.

また、特許文献2の構成では予め貫通電極54が形成されたカバー基板55を用意し、このカバー基板55を素子基板52に貼り合わせることが必要である。特許文献3の構成でも、ビアホール86を形成しておくことが必要である。   Further, in the configuration of Patent Document 2, it is necessary to prepare a cover substrate 55 in which the through electrode 54 is formed in advance, and to bond the cover substrate 55 to the element substrate 52. Even in the configuration of Patent Document 3, it is necessary to form the via hole 86 in advance.

本発明は、薄型化することができ、しかも外部引き出し電極として貫通電極やビアホールの形成がいらない電子素子パッケージを提供することを目的とする。   An object of the present invention is to provide an electronic device package that can be thinned and does not require the formation of a through electrode or a via hole as an external lead electrode.

本発明の請求項1記載の電子素子パッケージは、検出手段が形成された板状のセンサー基板を中央にしてその上下に板状の第1,第2カバー基板を直接または間接的に接合した電子素子パッケージであって、前記センサー基板には、前記検出手段として少なくとも第1検出部と第2検出部と、空間を介して前記検出手段を取り囲む枠と、前記検出手段と前記枠を繋ぐ少なくとも2本の梁と、前記枠に配設され前記検出手段に電気接続された電極とを設け、前記第1カバー基板あるいは前記第2カバー基板には、端面の内壁が前記電極の少なくとも一部と接触する貫通孔を設けたことを特徴とする。   The electronic device package according to claim 1 of the present invention is an electronic device in which a plate-like sensor substrate on which detection means is formed is centered, and plate-like first and second cover substrates are directly or indirectly joined to the upper and lower sides thereof. In the element package, the sensor substrate includes at least a first detection unit and a second detection unit as the detection unit, a frame surrounding the detection unit via a space, and at least two connecting the detection unit and the frame. And an electrode disposed on the frame and electrically connected to the detection means, wherein the inner wall of the end surface of the first cover substrate or the second cover substrate is in contact with at least a part of the electrode. A through hole is provided.

本発明の請求項2記載の電子素子パッケージは、請求項1において、前記電極を、前記検出手段と空間を介して対向する前記枠の一部の辺と、前記枠の外周とで囲まれた領域に配設したことを特徴とする。   The electronic device package according to claim 2 of the present invention is the electronic device package according to claim 1, wherein the electrode is surrounded by a side of a part of the frame facing the detection unit through a space and an outer periphery of the frame. It is characterized by being disposed in the region.

本発明の請求項3記載の電子素子パッケージは、請求項1において、前記カバー基板の前記センサー基板との対向面で前記検出部に対応する位置に、凹部を形成したことを特徴とする。   According to a third aspect of the present invention, in the electronic device package according to the first aspect, a concave portion is formed at a position corresponding to the detection portion on a surface of the cover substrate facing the sensor substrate.

本発明の請求項4記載の電子素子パッケージは、請求項1において、前記センサー基板は、前記検出手段の部分がその周辺よりも厚みが薄く形成されていることを特徴とする。
本発明の請求項5記載の電子素子パッケージの製造方法は、検出手段が形成された板状のセンサー基板を中央にしてその上下に板状の第1,第2カバー基板を直接または間接的に接合した電子素子パッケージを製作するに際し、検出部が形成されたセンサー基板が多数取りされている第1のウエハを中央にしてその上下に、前記センサー基板に対応して第1,第2カバー基板が多数取りされている第2,第3のウエハを接合して接合ウエハを形成し、前記接合ウエハを切断して電子素子パッケージに個片化することを特徴とする。
According to a fourth aspect of the present invention, in the electronic device package according to the first aspect, the sensor substrate is formed such that a portion of the detection means is thinner than a periphery thereof.
According to a fifth aspect of the present invention, there is provided a method for manufacturing an electronic device package, wherein the plate-like sensor substrate on which the detecting means is formed is centered, and the plate-like first and second cover substrates are directly or indirectly provided above and below the plate-like sensor substrate. When the bonded electronic device package is manufactured, the first and second cover substrates corresponding to the sensor substrate are formed above and below the first wafer on which a large number of sensor substrates on which detection parts are formed are taken as the center. The second and third wafers in which a large number of wafers are removed are bonded to form a bonded wafer, and the bonded wafer is cut to be separated into electronic element packages.

本発明の請求項6記載の電子素子パッケージは、電子素子が形成された素子基板とカバー基板とを接合し、前記素子基板と前記カバー基板の隙間において隔壁部によって前記電子素子を取り囲んで封止するとともに、前記カバー基板には前記素子基板の第1電極に対応した導入穴を有し、前記導入穴の形状を、前記素子基板に向かって径が小さくなる形状に構成するとともに、前記導入穴の前記素子基板の側の端部が、前記カバー基板に形成された第2電極で閉塞されており、前記第1電極と前記第2電極が当接していることを特徴とする。   According to a sixth aspect of the present invention, there is provided an electronic element package in which an element substrate on which an electronic element is formed and a cover substrate are joined, and the electronic element is surrounded by a partition wall in a gap between the element substrate and the cover substrate. In addition, the cover substrate has an introduction hole corresponding to the first electrode of the element substrate, and the shape of the introduction hole is configured to have a diameter that decreases toward the element substrate. The end of the element substrate is closed by a second electrode formed on the cover substrate, and the first electrode and the second electrode are in contact with each other.

本発明の請求項7記載の電子素子パッケージは、請求項6において、前記導入穴の内周に素子基板に向かって延びる溝を形成したことを特徴とする。
本発明の請求項8記載の電子素子パッケージ実装方法は、電子素子が形成された素子基板とカバー基板とを接合し、前記素子基板と前記カバー基板の隙間において隔壁部によって前記電子素子を取り囲んで封止するとともに、前記カバー基板には前記素子基板の第1電極に対応して前記素子基板に向かって径が小さくなる形状の導入穴が形成された電子素子パッケージを、基板に形成されたランドに実装するに際し、前記基板の実装位置の前記ランドに導電性材料を盛り、前記導入穴を前記基板の側に向けて前記電子素子パッケージを前記基板の実装位置に押し付けて前記実装位置のランドに盛られた導電性材料を前記電子素子パッケージの前記導入穴から前記素子基板の前記第1電極の側に導いて前記導電性材料を介して前記基板のランドと前記素子基板の電子素子とを電気接続することを特徴とする。
According to a seventh aspect of the present invention, in the electronic device package according to the sixth aspect, a groove extending toward the device substrate is formed in the inner periphery of the introduction hole.
According to an eighth aspect of the present invention, there is provided an electronic device package mounting method comprising: joining an element substrate on which an electronic element is formed and a cover substrate; and surrounding the electronic element by a partition wall in a gap between the element substrate and the cover substrate. In addition to sealing, an electronic element package in which an introduction hole having a diameter decreasing toward the element substrate corresponding to the first electrode of the element substrate is formed on the cover substrate is formed on the land formed on the substrate. In mounting, a conductive material is placed on the land at the mounting position of the substrate, and the electronic element package is pressed against the mounting position of the substrate with the introduction hole directed toward the substrate, to the land at the mounting position. The stacked conductive material is guided from the introduction hole of the electronic element package to the first electrode side of the element substrate, and the land of the substrate is interposed through the conductive material. Characterized by electrically connecting the electronic element of the element substrate.

この構成によると、薄型化と高信頼性が可能な電子素子パッケージを実現できる。   According to this configuration, an electronic device package capable of being thinned and highly reliable can be realized.

以下、本発明の各実施の形態を図1〜図10,図11〜図18に基づいて説明する。なお、同様の作用を成すものには同一の符号を付けて説明する。
(実施の形態1)
図1〜図4は本発明の実施の形態1を示す。
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 10 and FIGS. 11 to 18. In addition, the same code | symbol is attached | subjected and demonstrated to what comprises the same effect | action.
(Embodiment 1)
1 to 4 show Embodiment 1 of the present invention.

図1(a)は本発明の実施の形態1における電子素子パッケージの断面図を示し、図1(b)は上面図、図1(c)は底面図を示している。図1(a)は図1(b)のA−AA断面図である。   1A is a cross-sectional view of an electronic element package according to Embodiment 1 of the present invention, FIG. 1B is a top view, and FIG. 1C is a bottom view. FIG. 1A is a cross-sectional view taken along the line A-AA in FIG.

この電子素子パッケージは、加速度センサーであって、板状のセンサー基板14を中央にして、センサー基板14の上側に板状の第1のカバー基板15、センサー基板14の下側に板状の第2のカバー基板16を設けて、この3枚を接合した構造である。   This electronic element package is an acceleration sensor, with a plate-like sensor substrate 14 in the center, a plate-like first cover substrate 15 above the sensor substrate 14, and a plate-like first substrate below the sensor substrate 14. Two cover substrates 16 are provided, and the three substrates are joined.

シリコンまたは石英製のセンサー基板14には、図2(a)とこのB−BB断面を示す図2(b)のようにドライエッチングなどで孔17A,17Bを形成して、中央がビーム18で外周部から支持された可動片19が形成されている。可動片19の前記ビーム18よりも右側の部分に第1の検出部20Aが構成され、ビーム18よりも左側の部分に第2の検出部20Bが構成されている。   Holes 17A and 17B are formed in the sensor substrate 14 made of silicon or quartz by dry etching or the like as shown in FIG. 2A and FIG. 2B showing the B-BB cross section. A movable piece 19 supported from the outer peripheral portion is formed. A first detection unit 20 </ b> A is configured on the right side of the movable piece 19 with respect to the beam 18, and a second detection unit 20 </ b> B is configured on the left side of the beam 18.

第1,第2の検出部20A,20Bには、図2(a)のC−CC断面を示す図2(c)のように可動片19の上に0.3μm厚のPt膜を形成し、その上に2.75μm厚のPZTを形成し、さらにその上に0.3μm厚のAu膜を形成して構成されている。   In the first and second detectors 20A and 20B, a Pt film having a thickness of 0.3 μm is formed on the movable piece 19 as shown in FIG. 2C showing the C-CC cross section of FIG. The PZT having a thickness of 2.75 μm is formed thereon, and the Au film having a thickness of 0.3 μm is further formed thereon.

センサー基板14の四隅の近傍には、図2(a)とこのD−DD断面を示す図2(d)のように内周に電極が形成されたスルホール21a,21b,21c,21dが形成されており、スルホール21a,21bはセンサー基板14上に形成された配線電極22a,22bによって第1の検出部20AのPt膜とAu膜に接続されている。スルホール21c,21dはセンサー基板14上に形成された配線電極22c,22dによって第2の検出部20BのPt膜とAu膜に接続されている。   In the vicinity of the four corners of the sensor substrate 14, through holes 21a, 21b, 21c, 21d having electrodes formed on the inner periphery are formed as shown in FIG. 2A and FIG. 2D showing the D-DD cross section. The through holes 21a and 21b are connected to the Pt film and the Au film of the first detection unit 20A by wiring electrodes 22a and 22b formed on the sensor substrate 14, respectively. The through holes 21c and 21d are connected to the Pt film and the Au film of the second detection unit 20B by wiring electrodes 22c and 22d formed on the sensor substrate 14.

シリコンまたは石英製の第1のカバー基板15には、図3(a)とこのE−EE断面を示す図3(b)に示すように第1,第2の検出部20A,20Bに対応した位置に凹部23がドライエッチングなどで形成されている。   The first cover substrate 15 made of silicon or quartz corresponds to the first and second detectors 20A and 20B as shown in FIG. 3A and FIG. 3B showing the E-EE cross section. A recess 23 is formed at the position by dry etching or the like.

シリコンまたは石英製の第2のカバー基板16には、図3(c)とこのF−FF断面を示す図3(d)に示すように第1,第2の検出部20A,20Bに対応した位置に凹部24がドライエッチングなどで形成されている。さらに、第2のカバー基板16には、図3(c)とこのF−FF断面を示す図3(d)、図3(c)のG−GG断面を示す図3(e)に示すようにセンサー基板14のスルホール21a,21b,21c,21dに対応して内周に電極が形成されたスルホール25a,25b,25c,25dが形成されている。   The second cover substrate 16 made of silicon or quartz corresponds to the first and second detectors 20A and 20B as shown in FIG. 3C and FIG. 3D showing the F-FF cross section. A recess 24 is formed at the position by dry etching or the like. Further, the second cover substrate 16 is shown in FIG. 3C, FIG. 3D showing the F-FF cross section, and FIG. 3E showing the G-GG cross section of FIG. 3C. In addition, through holes 25a, 25b, 25c, and 25d having electrodes formed on the inner periphery corresponding to the through holes 21a, 21b, 21c, and 21d of the sensor substrate 14 are formed.

センサー基板14と第1のカバー基板15、第2のカバー基板16との接合は、次に示す工程で実行されている。
図4(a)では、センサー基板14の上面の外周部と下面の外周部、センサー基板14の上面のスルホール21a〜21dの周り、ならびにセンサー基板14の下面のスルホール21a〜21dの周りに接着剤26を塗布する。
Bonding of the sensor substrate 14 to the first cover substrate 15 and the second cover substrate 16 is performed in the following steps.
In FIG. 4A, an adhesive is provided around the outer peripheral portion of the upper surface and the lower peripheral portion of the sensor substrate 14, around the through holes 21 a to 21 d on the upper surface of the sensor substrate 14, and around the through holes 21 a to 21 d on the lower surface of the sensor substrate 14. 26 is applied.

図4(b)では、センサー基板14と第1のカバー基板15、第2のカバー基板16とを貼り合わせて、その後に図4(c)に示すようにスルホール25a〜25dから半田27を供給してリフローして外部接続端子を形成して組み立てが完了する。   4B, the sensor substrate 14, the first cover substrate 15 and the second cover substrate 16 are bonded together, and then solder 27 is supplied from the through holes 25a to 25d as shown in FIG. 4C. Then, reflow is performed to form external connection terminals, and the assembly is completed.

なお、ここでは接着剤26を使用した接合の場合を例に挙げて説明したが、次のようにしても接合できる。具体的には、センサー基板14の上面と下面,第1のカバー基板15の下面、第2のカバー基板16の上面に対して、真空チャンバ内で例えばプラズマ、原子ビーム、光エネルギーなどのエネルギーを照射して表面清浄と活性化を実施した前処理の後に、同じ真空チャンバ内でセンサー基板14の上面と第1のカバー基板15の下面とを当接させて加圧して、常温接合プロセスで接合する。さらに、センサー基板14の下面と第2のカバー基板16の上面とを当接させて加圧して、常温接合プロセスで接合する。その後にスルホール25a〜25dから半田27を供給してリフローして外部接続端子を形成して組み立てが完了する。   Here, the case of bonding using the adhesive 26 has been described as an example, but bonding can also be performed as follows. Specifically, energy such as plasma, atomic beam, or light energy is applied to the upper and lower surfaces of the sensor substrate 14, the lower surface of the first cover substrate 15, and the upper surface of the second cover substrate 16 in a vacuum chamber. After the pre-treatment of performing surface cleaning and activation by irradiation, the upper surface of the sensor substrate 14 and the lower surface of the first cover substrate 15 are brought into contact with each other in the same vacuum chamber and pressed, and bonded by a room temperature bonding process. To do. Further, the lower surface of the sensor substrate 14 and the upper surface of the second cover substrate 16 are brought into contact with each other and pressurized, and bonded by a room temperature bonding process. Thereafter, the solder 27 is supplied from the through holes 25a to 25d and reflowed to form external connection terminals, thereby completing the assembly.

ここで、実施の形態1の構成と、従来例として挙げた図21,図22の構成と比較して説明する。
図21,図22に示した従来例では、下側ガラス基板81と上側ガラス基板82との貼り合わせによるシール構造は、下側ガラス基板81の外周部に設けられた幅の狭い枠部84と、一部に枠部84とは独立して島状に形成された信号出力部85a,85b,85cとの少ないエリアだけで上側ガラス基板82と張り合わされて電子素子パッケージの内部がシールされている。このようなシール構造では、枠部84と信号出力部85a,85b,85cの間にハーメチックシールに有効に作用していない隙間エリア87a,87b,87cが存在している。
Here, the configuration of the first embodiment will be described in comparison with the configurations of FIGS. 21 and 22 cited as conventional examples.
In the conventional example shown in FIGS. 21 and 22, the sealing structure by bonding the lower glass substrate 81 and the upper glass substrate 82 is a narrow frame portion 84 provided on the outer peripheral portion of the lower glass substrate 81. In addition, the interior of the electronic device package is sealed by adhering to the upper glass substrate 82 only in a small area with the signal output portions 85a, 85b, and 85c formed in an island shape independently of the frame portion 84. . In such a seal structure, gap areas 87a, 87b, 87c that do not effectively act on the hermetic seal exist between the frame portion 84 and the signal output portions 85a, 85b, 85c.

これに対して、実施の形態1の構成では、センサー基板14を中央にしてその上下に板状の第1,第2カバー基板15,16を直接または間接的に接合した電子素子パッケージであって、検出手段としての可動片19が形成された板状のセンサー基板14には、第1,第2検出部20A,20Bと、空間としての孔17A,17Bを介して第1,第2検出部20A,20Bを取り囲む枠であるセンサー基板14の外周部と、可動片19とセンサー基板14の外周部を繋ぐ少なくとも2本の梁としてのビーム18a,18bと、センサー基板14の外周部に配設され可動片19に電気接続された電極としてのスルホール21a〜21dとを設け、第1カバー基板15あるいは第2カバー基板16には、端面の内壁がスルホール21a〜21dの少なくとも一部と接触する貫通孔としてのスルホール25a〜25dを設けたため、センサー基板14の上面と第1のカバー基板15の下面との接合、ならびにセンサー基板14の下面と第2のカバー基板16との接合面積は、図1(b),図1(c)および図2(a)を見て分かるように、センサー基板14のスルホール21a〜21dが形成されているエリアも第1のカバー基板15との有効な接合面となっている。また、センサー基板14と第2のカバー基板16との接合も、図21と図22に見られたような幅の狭い枠部84だけの接合ではなく、センサー基板14のスルホール21a〜21dが形成されているエリアも第2のカバー基板16との有効な接合面となっている。   On the other hand, the configuration of the first embodiment is an electronic element package in which the sensor substrate 14 is centered and the plate-like first and second cover substrates 15 and 16 are directly or indirectly joined to the upper and lower sides thereof. The plate-shaped sensor substrate 14 on which the movable piece 19 as the detection means is formed has the first and second detection portions 20A and 20B and the first and second detection portions through the holes 17A and 17B as spaces. Arranged on the outer periphery of the sensor substrate 14, which is a frame surrounding 20 </ b> A and 20 </ b> B, at least two beams 18 a and 18 b that connect the movable piece 19 and the outer periphery of the sensor substrate 14, and the sensor substrate 14. The through holes 21a to 21d as electrodes electrically connected to the movable piece 19 are provided, and the inner walls of the end surfaces of the first cover substrate 15 or the second cover substrate 16 have through holes 21a to 21d. Since the through holes 25a to 25d as through holes that contact at least a part are provided, the upper surface of the sensor substrate 14 and the lower surface of the first cover substrate 15 are joined, and the lower surface of the sensor substrate 14 and the second cover substrate 16 are bonded. As shown in FIGS. 1B, 1C and 2A, the area where the through holes 21a to 21d of the sensor substrate 14 are formed is also the first cover substrate. 15 is an effective joint surface. Further, the sensor substrate 14 and the second cover substrate 16 are joined not only by the narrow frame portion 84 as shown in FIGS. 21 and 22, but through holes 21a to 21d of the sensor substrate 14 are formed. This area is also an effective joint surface with the second cover substrate 16.

したがって、実施の形態1ではセンサー基板14と第1,第2のカバー基板15,16との接合面積が、図21と図22に挙げた従来例に比べて大きくて、ハーメチックシールに有効に作用してシールの信頼性が極めて高いものである。   Therefore, in the first embodiment, the bonding area between the sensor substrate 14 and the first and second cover substrates 15 and 16 is larger than that of the conventional example shown in FIGS. 21 and 22 and effectively acts on the hermetic seal. Thus, the reliability of the seal is extremely high.

(実施の形態2)
図5は本発明の実施の形態2を示す。
実施の形態1では、センサー基板14と第1,第2のカバー基板15,16とを、電子素子パッケージ毎に接合したが、この実施の形態2では、図5(a)に示すように、センサー基板14が多数取りされている第1のウエハ28と、第1のウエハ28の各センサー基板14の部分に対応して第1のカバー基板15が多数取りされている第2のウエハ29と、第1のウエハ28の各センサー基板14の部分に対応して第2のカバー基板16が多数取りされている第3のウエハ30とを接合して接合ウエハ31を形成し、図5(b)では接合ウエハ31をダイシングソー32によって切断して、電子素子パッケージ33に個片化する。
(Embodiment 2)
FIG. 5 shows a second embodiment of the present invention.
In the first embodiment, the sensor substrate 14 and the first and second cover substrates 15 and 16 are joined for each electronic element package. In the second embodiment, as shown in FIG. A first wafer 28 in which a large number of sensor substrates 14 are taken, and a second wafer 29 in which a large number of first cover substrates 15 are taken corresponding to the portions of the sensor substrates 14 of the first wafer 28 Then, a bonded wafer 31 is formed by bonding the third wafer 30 having a large number of second cover substrates 16 corresponding to the portions of the sensor substrates 14 of the first wafer 28, as shown in FIG. ), The bonded wafer 31 is cut by a dicing saw 32 and separated into electronic element packages 33.

(実施の形態3)
上記の各実施の形態では、電子素子パッケージの四隅の近傍に外部接続端子が形成されていたが、図6に示す実施の形態3では、電子素子パッケージのコーナー部に外部接続端子が形成されている。
(Embodiment 3)
In each of the above embodiments, the external connection terminals are formed near the four corners of the electronic element package. However, in the third embodiment shown in FIG. 6, the external connection terminals are formed at the corners of the electronic element package. Yes.

図6(a)はこの場合のセンサー基板14を示しており、コーナー部に円弧状の電極34a,34b,34c,34dが形成されている。電極34a,34bはセンサー基板14上に形成された配線電極35a,35bによって第1の検出部20AのPt膜とAu膜に接続されている。電極34c,34dはセンサー基板14上に形成された配線電極35c,35dによって第2の検出部20BのPt膜とAu膜に接続されている。第2のカバー基板16には電極34a〜34dに対応して同様にコーナー部に電極36a,36b,36c,36dが形成されて、図6(b)に示すようにセンサー基板14と第1,第2のカバー基板15,16とを接合し、電極34bと電極36bに跨って半田27を付け、電極34cと電極36c,電極34aと電極36a,電極34dと電極36dについても半田27を付けて外部接続端子とした。   FIG. 6A shows the sensor substrate 14 in this case, and arc-shaped electrodes 34a, 34b, 34c, and 34d are formed at corner portions. The electrodes 34a and 34b are connected to the Pt film and the Au film of the first detection unit 20A by wiring electrodes 35a and 35b formed on the sensor substrate 14. The electrodes 34c and 34d are connected to the Pt film and the Au film of the second detection unit 20B by wiring electrodes 35c and 35d formed on the sensor substrate 14. Similarly, electrodes 36a, 36b, 36c, and 36d are formed at the corners corresponding to the electrodes 34a to 34d on the second cover substrate 16, and as shown in FIG. The second cover substrates 15 and 16 are joined, solder 27 is applied across the electrodes 34b and 36b, and solder 27 is also applied to the electrodes 34c and 36c, the electrodes 34a and 36a, and the electrodes 34d and 36d. External connection terminals.

なお、このような電子素子パッケージを図5に示したように接合ウエハ31をダイシングソー32によって切断して個片化して作成できる。この場合には、ダイシングソー32によって切断する前の接合ウエハ31の状態において、第3のウエハ30のスルホールの部分に半田を供給してリフローした後に、図6(c)に示すように外部接続端子となる部分を、切断線37の位置をダイシングソー32によって切断して個片化することによって図6(b)に示す電子素子パッケージ33を得ることができる。   Such an electronic device package can be formed by cutting the bonded wafer 31 by a dicing saw 32 into individual pieces as shown in FIG. In this case, in the state of the bonded wafer 31 before being cut by the dicing saw 32, after supplying solder to the through hole portion of the third wafer 30 and reflowing, external connection is performed as shown in FIG. 6B can be obtained by cutting the portion to be a terminal into pieces by cutting the position of the cutting line 37 with a dicing saw 32. The electronic device package 33 shown in FIG.

(実施の形態4)
実施の形態2では、接合ウエハ31をダイシングソー32によって切断して電子素子パッケージ33に個片化したが、この実施の形態4では、ダイシングソー32によって図7(a)と図7(b)に示すように第1のウエハ38を複数枚の集合体38a〜38nに切断し、第2,第3のウエハ39,40も集合体38a〜38nと同サイズの複数枚の集合体39a〜39n,40a〜40nに切断し、図7(c)に示す工程では、第1のウエハ38から切り出した各集合体38a〜38nをそれぞれ中央にして、第2のウエハ39から切り出した集合体39a〜39nと第3のウエハ40から切り出した集合体40a〜40nを接合して接合集合体41を作成し、この接合集合体41をダイシングソー32で個片化する。これにより、元のウエハサイズが大きくなっても接合プロセスは同一の装置で組み立てられる。
(Embodiment 4)
In the second embodiment, the bonded wafer 31 is cut by the dicing saw 32 and separated into the electronic element package 33. However, in the fourth embodiment, the dicing saw 32 is used to form FIGS. 7 (a) and 7 (b). As shown in FIG. 2, the first wafer 38 is cut into a plurality of aggregates 38a to 38n, and the second and third wafers 39 and 40 are also a plurality of aggregates 39a to 39n having the same size as the aggregates 38a to 38n. , 40a to 40n, and in the step shown in FIG. 7C, the aggregates 39a to 39n cut out from the second wafer 39 with the respective assemblies 38a to 38n cut out from the first wafer 38 as the center. 39 n and the aggregates 40 a to 40 n cut out from the third wafer 40 are joined to form a joined aggregate 41, and the joined aggregate 41 is separated into pieces by the dicing saw 32. Thereby, even if the original wafer size becomes large, the bonding process is assembled by the same apparatus.

(実施の形態5)
図8と図9は本発明の実施の形態5を示す。
上記の各実施の形態の第1のカバー基板15、第2のカバー基板16には、センサー基板14の第1,第2の検出部20A,20Bに対応した凹部23,24が形成されていたが、この実施の形態5のセンサー基板14Bでは、図9に示すように第1,第2のカバー基板15B,16Bには、凹部23,24が形成されていない。
(Embodiment 5)
8 and 9 show a fifth embodiment of the present invention.
In the first cover substrate 15 and the second cover substrate 16 of each of the above embodiments, the recesses 23 and 24 corresponding to the first and second detection units 20A and 20B of the sensor substrate 14 were formed. However, in the sensor substrate 14B of the fifth embodiment, as shown in FIG. 9, the first and second cover substrates 15B, 16B are not formed with the recesses 23, 24.

図8はこの場合のセンサー基板14Bを示す。
図8(b)は図8(a)のB−BB断面図、図8(c)は図8(a)のC−CC断面図、図8(d)は図8(a)のD−DD断面図であって、センサー基板14Bは図8(c)に示すように第1,第2の検出部20A,20Bがセンサー基板14の外周部42よりも薄く形成されている。
FIG. 8 shows the sensor substrate 14B in this case.
8B is a cross-sectional view taken along B-BB in FIG. 8A, FIG. 8C is a cross-sectional view taken along C-CC in FIG. 8A, and FIG. 8D is a cross-sectional view taken along D- in FIG. FIG. 8D is a sectional view of DD, and the sensor substrate 14B is formed such that the first and second detection portions 20A and 20B are thinner than the outer peripheral portion 42 of the sensor substrate 14 as shown in FIG.

実施の形態5の電子素子パッケージは、センサー基板14Bの上下面に図9に示すように凹部23,24が形成されていない第1,第2のカバー基板15B,16Bを接合し、半田27を供給してリフローして外部接続端子を形成して組み立てが完了する。   In the electronic device package according to the fifth embodiment, the first and second cover substrates 15B and 16B in which the recesses 23 and 24 are not formed are joined to the upper and lower surfaces of the sensor substrate 14B as shown in FIG. Supply and reflow to form external connection terminals and complete the assembly.

(実施の形態6)
上記の各実施の形態の電子素子パッケージのセンサー基板は、第1,第2の検出部20A,20Bの中央側の一端がビーム18で支持された片持ち構造であったが、図10(a)に示すように可動片19の両端をビーム43によってセンサー基板14の外周部42に連結して支持するように孔17A,17B,17C,17Dを形成しても同様に構成できる。また、図10(b)に示すように可動片19を複数のビーム43によってセンサー基板14の外周部42に連結して支持するように孔17を形成しても同様に構成できる。
(Embodiment 6)
The sensor substrate of the electronic device package of each of the above embodiments has a cantilever structure in which one end on the center side of the first and second detection units 20A and 20B is supported by the beam 18, but FIG. As shown in FIG. 5B, the same configuration can be obtained by forming the holes 17A, 17B, 17C, and 17D so that both ends of the movable piece 19 are connected to and supported by the outer peripheral portion 42 of the sensor substrate 14 by the beam 43. Further, as shown in FIG. 10B, the same configuration can be obtained by forming the hole 17 so that the movable piece 19 is connected to and supported by the outer peripheral portion 42 of the sensor substrate 14 by a plurality of beams 43.

(実施の形態7)
図11〜図14は本発明の実施の形態7を示す。
図11(a)は本発明の実施の形態7における電子素子パッケージの断面図を示し、図11(b)は底面図を示している。
(Embodiment 7)
11 to 14 show a seventh embodiment of the present invention.
FIG. 11A shows a cross-sectional view of an electronic device package according to Embodiment 7 of the present invention, and FIG. 11B shows a bottom view.

この電子素子パッケージAは、図12に示す素子基板58と図13に示すカバー基板59とを張り合わせて構成されている。
図12(a)と図12(b)に示すように素子基板58の一方の面には、電子素子60と第1電極としての配線電極61が形成されている。電子素子60の入出力ラインは 配線電極61に電気接続されている。
This electronic element package A is configured by laminating an element substrate 58 shown in FIG. 12 and a cover substrate 59 shown in FIG.
As shown in FIGS. 12A and 12B, an electronic element 60 and a wiring electrode 61 as a first electrode are formed on one surface of the element substrate 58. The input / output lines of the electronic element 60 are electrically connected to the wiring electrode 61.

図13(a)と図13(b)に示すようにカバー基板59には、素子基板58の配線電極61の位置に対応して第2電極としての電極62と、前記素子基板58の第1電極に対応した位置に前記素子基板58に向かって径が小さくなる例えばテーパー状の導入穴63が形成されている。導入穴63の前記素子基板58の側の端部は、前記カバー基板59に形成された電極62で閉塞されている。導入穴63は、レーザ、ケミカルエッチング法、ドライエッチング法、ブラスト法などにより形成できる。   As shown in FIGS. 13A and 13B, the cover substrate 59 has an electrode 62 as a second electrode corresponding to the position of the wiring electrode 61 of the element substrate 58, and the first of the element substrate 58. For example, a tapered introduction hole 63 whose diameter decreases toward the element substrate 58 is formed at a position corresponding to the electrode. An end of the introduction hole 63 on the element substrate 58 side is closed by an electrode 62 formed on the cover substrate 59. The introduction hole 63 can be formed by a laser, a chemical etching method, a dry etching method, a blast method, or the like.

さらに、素子基板58には、電極64が電子素子60を取り囲むように環状に形成されている。カバー基板59には、素子基板58の電極64に対応して電極65が環状に形成されている。この実施の形態では、配線電極61,電極62は同一材料の例えば金で形成されている。電極64,電極65は同一材料の例えば金で形成されている。   Further, the electrode 64 is formed in an annular shape on the element substrate 58 so as to surround the electronic element 60. On the cover substrate 59, electrodes 65 are formed in an annular shape corresponding to the electrodes 64 of the element substrate 58. In this embodiment, the wiring electrode 61 and the electrode 62 are made of the same material, for example, gold. The electrodes 64 and 65 are made of the same material, for example, gold.

なお、素子基板58とカバー基板59の貼り合わせに際しては、配線電極61の表面,電極64の表面,電極62の表面,電極65の表面に対して、真空チャンバ内で例えばプラズマ、原子ビーム、光エネルギーなどのエネルギーを照射して表面清浄と活性化を実施した前処理の後に、同じ真空チャンバ内で素子基板58の配線電極61の表面とカバー基板59の電極62の表面とを互いに当接させ、素子基板58の電極64の表面とカバー基板59の電極65の表面とを互いに当接させた状態で加圧して、常温接合プロセスで接合されている。   When the element substrate 58 and the cover substrate 59 are bonded to each other, for example, plasma, atomic beam, light in the vacuum chamber with respect to the surface of the wiring electrode 61, the surface of the electrode 64, the surface of the electrode 62, and the surface of the electrode 65. After the pretreatment in which surface cleaning and activation are performed by irradiating energy such as energy, the surface of the wiring electrode 61 of the element substrate 58 and the surface of the electrode 62 of the cover substrate 59 are brought into contact with each other in the same vacuum chamber. The surface of the electrode 64 of the element substrate 58 and the surface of the electrode 65 of the cover substrate 59 are pressed in a state where they are in contact with each other, and are bonded by a room temperature bonding process.

接合した環状の電極64と環状の電極65とは、電子素子60を取り囲んで封止する隔壁部66を形成している。
図14はこのようにして形成された電子素子パッケージAを、基板67に形成されたランド68に実装する過程を示している。
The joined annular electrode 64 and annular electrode 65 form a partition 66 that surrounds and seals the electronic element 60.
FIG. 14 shows a process of mounting the electronic device package A formed in this way on the land 68 formed on the substrate 67.

先ず、図14(a)に示すように、基板67のランド68に導電性材料としての半田69が盛られている。図14(b)では、半田69をリフローで溶融させた状態で、導入穴63を基板67の側に向けて電子素子パッケージAを、基板67の実装位置に押し付ける。   First, as shown in FIG. 14A, solder 69 as a conductive material is stacked on the land 68 of the substrate 67. In FIG. 14B, the electronic device package A is pressed against the mounting position of the substrate 67 with the introduction hole 63 facing the substrate 67 with the solder 69 melted by reflow.

これによって、溶融状態の半田69が、導入穴63によって素子基板58の配線電極61の側に導かれて、半田69がカバー基板59の電極62に接続される。この状態で半田69が固化することによって、基板67に形成されたランド68が、半田69と電極62と配線電極61を介して電子素子60と電気接続される。   As a result, the molten solder 69 is guided to the wiring electrode 61 side of the element substrate 58 through the introduction hole 63, and the solder 69 is connected to the electrode 62 of the cover substrate 59. When the solder 69 is solidified in this state, the land 68 formed on the substrate 67 is electrically connected to the electronic element 60 via the solder 69, the electrode 62, and the wiring electrode 61.

導入穴63や配線電極61の大きさや、溶融状態の半田69の粘度などの組み合わせによっては、リフロー時に導入穴の中の溶融半田に気泡が存在する場合がある。この溶融半田の中の気泡が電子素子60と基板のランド68との電気的接続を不安定にする可能性がある。この場合は、図示していないが導入穴63の側面に、溶融時の半田の中の気泡を逃がす空気逃がし穴を設けると、溶融半田の中の気泡の電気的接続への影響を少なくすることができる。   Depending on the combination of the size of the introduction hole 63 and the wiring electrode 61 and the viscosity of the molten solder 69, bubbles may be present in the molten solder in the introduction hole during reflow. The bubbles in the molten solder may make the electrical connection between the electronic device 60 and the board land 68 unstable. In this case, although not shown, if an air escape hole is provided on the side surface of the introduction hole 63 to release bubbles in the solder at the time of melting, the influence of the bubbles in the molten solder on the electrical connection is reduced. Can do.

また、この構成によると、基板67におけるランド68の大きさに比べてランド間の間隔76が小さい場合であっても、半田ブリッジが発生せずに良好な実装状態が得られた。
この実施の形態では導電性材料としての半田69を使用したが、導電性樹脂でも実施できる。この場合にはランド68の上に設けられた硬化前の導電性樹脂を、電子素子パッケージAの基板67の実装位置に押し付けることによって、硬化前の導電性樹脂が導入穴63の中に入って行き、基板67に形成されたランド68が、導電性樹脂と電極62と配線電極61を介して電子素子60と電気接続される。その後に熱をかけて前記導電性樹脂を硬化させる形態も有効である。
Further, according to this configuration, even when the distance 76 between the lands 68 is smaller than the size of the lands 68 on the substrate 67, a good mounting state can be obtained without generating a solder bridge.
In this embodiment, the solder 69 is used as the conductive material, but it can also be implemented with a conductive resin. In this case, the conductive resin before curing provided on the land 68 is pressed against the mounting position of the substrate 67 of the electronic element package A, so that the conductive resin before curing enters the introduction hole 63. The land 68 formed on the substrate 67 is electrically connected to the electronic element 60 through the conductive resin, the electrode 62 and the wiring electrode 61. A form in which the conductive resin is cured by applying heat is also effective.

(実施の形態8)
図15は本発明の実施の形態8を示す。
実施の形態7では、素子基板58の厚みが0.2〜0.3mm程度,カバー基板59の厚みが0.3mm以上の比較的厚みのある電子素子パッケージAの場合であったが、図15に示すようにカバー基板59の厚みが0.2mm以下の比較的厚みのある電子素子パッケージの場合にも同様に実施できる。
(Embodiment 8)
FIG. 15 shows an eighth embodiment of the present invention.
In the seventh embodiment, the thickness of the element substrate 58 is about 0.2 to 0.3 mm, and the cover substrate 59 is a relatively thick electronic element package A having a thickness of 0.3 mm or more. As shown, the cover substrate 59 can be implemented similarly in the case of a relatively thick electronic device package having a thickness of 0.2 mm or less.

(実施の形態9)
図16は本発明の実施の形態9を示す。
実施の形態7では、導入穴63は内周面が平滑であったが、この図16に示す実施の形態9では、導入穴63の内周面には、素子基板58に向かって延びる溝70が形成されている。このように溝70を設けることによって、毛細管現象によって半田濡れが向上し、より接合品質の安定した電子素子パッケージを得ることができる。
(Embodiment 9)
FIG. 16 shows Embodiment 9 of the present invention.
In the seventh embodiment, the inner peripheral surface of the introduction hole 63 is smooth. However, in the ninth embodiment shown in FIG. 16, a groove 70 extending toward the element substrate 58 is formed on the inner peripheral surface of the introduction hole 63. Is formed. By providing the groove 70 in this manner, the solder wettability is improved by the capillary phenomenon, and an electronic element package with more stable bonding quality can be obtained.

(実施の形態10)
図17は本発明の実施の形態10を示す。
この図17は電子素子パッケージの製造過程を示している。
(Embodiment 10)
FIG. 17 shows a tenth embodiment of the present invention.
FIG. 17 shows the manufacturing process of the electronic element package.

図17(a)に示すように、半導体ウエハ71には複数個の素子基板58が多数取りされており、カバーウエハ72には複数個のカバー基板59が同様に多数取りされている。
なお、隔壁部66の電極64,65は半導体ウエハ71とカバーウエハ72に、グリッド状のパターンとして、スパッタ、メッキプロセスにより金属材料で形成されている。
As shown in FIG. 17A, the semiconductor wafer 71 has a large number of element substrates 58, and the cover wafer 72 has a plurality of cover substrates 59 similarly.
The electrodes 64 and 65 of the partition wall 66 are formed of a metal material on the semiconductor wafer 71 and the cover wafer 72 as a grid pattern by a sputtering or plating process.

真空チャンバ内での清浄化と荷重を印加することにより活性化による常温接合プロセスで半導体ウエハ71とカバーウエハ72を接合して一体化した接合半導体ウエハ73を、図17(b)に示すようダイシングソー74によって切断して、電子素子パッケージAに個片化する。   A bonded semiconductor wafer 73 in which the semiconductor wafer 71 and the cover wafer 72 are bonded and integrated by a normal temperature bonding process by activation by applying cleaning and applying a load in a vacuum chamber is diced as shown in FIG. The electronic device package A is cut into pieces by cutting with a saw 74.

(実施の形態11)
実施の形態10では、1枚の接合半導体ウエハ73をダイシングソー74によって切断して、電子素子パッケージAに個片化したが、図18に示すように、1枚の半導体ウエハ71を複数枚の集合体75a〜75nに切断し、その集合体75a〜75nに対して、集合体75a〜75nと同サイズのカバーウエハ72Aを接合し、これをダイシングソー74で個片化する。これにより、元のウエハサイズが大きくなっても接合プロセスは同一の装置で組立てをすることができる。
(Embodiment 11)
In the tenth embodiment, one bonded semiconductor wafer 73 is cut by a dicing saw 74 and separated into electronic element packages A. However, as shown in FIG. The aggregates 75a to 75n are cut, the cover wafers 72A having the same size as the aggregates 75a to 75n are joined to the aggregates 75a to 75n, and the dicing saw 74 separates them. Thereby, even if the original wafer size becomes large, the bonding process can be assembled by the same apparatus.

上記の実施の形態9では、導入穴63の内周面の濡れ性を改善することを目的として、溝70を設けたが、導入穴63の内周面をマット面で構成して導電性材料に対する濡れ性を改善したり、導電性材料に対する濡れ性を改善する膜を導入穴63の内周面に形成して構成することもできる。   In Embodiment 9 described above, the groove 70 is provided for the purpose of improving the wettability of the inner peripheral surface of the introduction hole 63. However, the inner peripheral surface of the introduction hole 63 is formed of a mat surface and is made of a conductive material. It is also possible to form a film that improves the wettability with respect to the conductive material or improves the wettability with respect to the conductive material on the inner peripheral surface of the introduction hole 63.

(実施の形態12)
図1〜図10に示した各実施の形態では、センサー基板14の外周部に配設され可動片19に電気接続された電極としてのスルホール21a〜21dとを設け、第1カバー基板15あるいは第2カバー基板16には、端面の内壁がスルホール21a〜21dと接触する貫通孔としてのスルホール25a〜25dを設けたが、端面の内壁がスルホール21a〜21dと接触する貫通孔は、内側に導電膜が形成されたスルホール25a〜25dではなくて、図11〜図18に示した各実施の形態のテーパー状の導入穴63と同様に、基板14に向かって径が小さくなる貫通孔だけを形成しておいて、図14に示した場合と同様に、電子素子パッケージを実装位置に押し付けて前記実装位置のランドに盛られた導電性材料を前記電子素子パッケージの前記導入穴からセンサー基板14の電極の側に導いて電気接続するように構成することもできる。
(Embodiment 12)
In each of the embodiments shown in FIGS. 1 to 10, through holes 21 a to 21 d as electrodes disposed on the outer peripheral portion of the sensor substrate 14 and electrically connected to the movable piece 19 are provided, and the first cover substrate 15 or the first cover substrate 15 is provided. 2 The cover substrate 16 is provided with through holes 25a to 25d as through holes in which the inner walls of the end surfaces are in contact with the through holes 21a to 21d. The through holes in which the inner walls of the end surfaces are in contact with the through holes 21a to 21d Instead of the through-holes 25a to 25d formed, the through-holes whose diameter decreases toward the substrate 14 are formed in the same manner as the tapered introduction holes 63 of the embodiments shown in FIGS. In the same manner as in the case shown in FIG. 14, the electronic element package is pressed against the mounting position, and the conductive material stacked on the land at the mounting position is used as the electronic element package. It may be configured to electrically connect to lead to the side of the electrode of the sensor substrate 14 from the introduction hole.

(実施の形態13)
図1〜図10に示した各実施の形態ならびに実施の形態12では、センサー基板14を挟んでいる第1カバー基板15と第2カバー基板16のうちの第2カバー基板16の方にだけ、端面の内壁がスルホール21a〜21dと接触する貫通孔を形成したが、端面の内壁がスルホール21a〜21dと接触する貫通孔を第1カバー基板15と第2カバー基板16の両方に形成して構成することもできる。
(Embodiment 13)
In each of the embodiments and the twelfth embodiments shown in FIGS. 1 to 10, only the first cover substrate 15 and the second cover substrate 16 among the second cover substrates 16 sandwiching the sensor substrate 14 are arranged. Although the through hole in which the inner wall of the end surface is in contact with the through holes 21a to 21d is formed, the through hole in which the inner wall of the end surface is in contact with the through holes 21a to 21d is formed in both the first cover substrate 15 and the second cover substrate 16. You can also

本発明は、薄型化と高信頼性が可能な電子素子パッケージの実現に寄与できる。   The present invention can contribute to the realization of an electronic device package that can be thinned and highly reliable.

本発明の実施の形態1における電子素子パッケージの断面図と上面図および底面図Sectional drawing, the top view, and bottom view of the electronic device package in Embodiment 1 of this invention 同実施の形態のセンサー基板の平面図とB−BB断面図,C−CC断面図,D−DD断面図Plan view, B-BB sectional view, C-CC sectional view, D-DD sectional view of the sensor substrate of the same embodiment 同実施の形態の第1のカバー基板の底面図とE−EE断面図ならびに第2のカバー基板の底面図とF−FF断面図とG−GG断面図The bottom view and E-EE sectional view of the first cover substrate of the same embodiment, the bottom view, F-FF sectional view and G-GG sectional view of the second cover substrate 同実施の形態の接合過程の断面図Sectional view of the joining process of the embodiment 本発明の実施の形態2における製造工程図Manufacturing process diagram in Embodiment 2 of the present invention 本発明の実施の形態3におけるセンサー基板の平面図と組み立てが完了した電子素子パッケージの断面図および切断する前の集合体の底面図The top view of the sensor substrate in Embodiment 3 of this invention, sectional drawing of the electronic element package which assembly was completed, and bottom view of the aggregate | assembly before cut | disconnecting 本発明の実施の形態4における製造工程図Manufacturing process diagram according to Embodiment 4 of the present invention 本発明の実施の形態5におけるセンサー基板の平面図とB−BB断面図とC−CC断面図およびD−DD断面図Plan view, B-BB sectional view, C-CC sectional view, and D-DD sectional view of a sensor substrate in Embodiment 5 of the present invention 同実施の形態の電子素子パッケージの断面図Sectional drawing of the electronic device package of the embodiment 別の実施の形態のセンサー基板の平面図Plan view of sensor substrate of another embodiment 本発明の実施の形態7における電子素子パッケージの拡大断面図と底面図The expanded sectional view and bottom view of the electronic device package in Embodiment 7 of this invention 同実施の形態の素子基板58の断面図と平面図Sectional view and plan view of element substrate 58 of the same embodiment 同実施の形態のカバー基板59の断面図と平面図Sectional view and plan view of cover substrate 59 of the same embodiment 同実施の形態の実装過程の断面図Cross-sectional view of the mounting process of the same embodiment 本発明の実施の形態8における電子素子パッケージの拡大断面図The expanded sectional view of the electronic device package in Embodiment 8 of this invention 本発明の実施の形態9における電子素子パッケージの拡大底面図と断面図Enlarged bottom view and cross-sectional view of an electronic device package according to Embodiment 9 of the present invention 本発明の実施の形態10における電子素子パッケージの製造工程斜視図Manufacturing process perspective view of the electronic device package in Embodiment 10 of this invention 本発明の実施の形態11における電子素子パッケージの製造工程斜視図The manufacturing process perspective view of the electronic device package in Embodiment 11 of this invention 特許文献1の電子素子パッケージの拡大断面図Enlarged sectional view of the electronic device package of Patent Document 1 特許文献2の電子素子パッケージの拡大断面図Enlarged sectional view of the electronic device package of Patent Document 2 特許文献3の電子素子パッケージの分解斜視図The exploded perspective view of the electronic device package of patent document 3 特許文献3の電子素子パッケージの断面図Sectional view of electronic device package of Patent Document 3

符号の説明Explanation of symbols

14 センサー基板
15,16 第1,第2のカバー基板
17A〜17D 孔
18 ビーム
19 可動片
20A 第1の検出部
20B 第2の検出部
21a〜21d スルホール
22a〜22d 配線電極
23,24 凹部
25a〜25d スルホール
26 接着剤
27 半田
28 第1のウエハ
29 第2のウエハ
30 第3のウエハ
31 接合ウエハ
32 ダイシングソー
33 電子素子パッケージ
34a〜34d 電極
35a〜35d 配線電極
36a〜36d 電極
38a〜38n,39a〜39n,40a〜40n 集合体
41 接合集合体
42 センサー基板14の外周部
43 ビーム
A 電子素子パッケージ
58 素子基板
59 カバー基板
60 電子素子
61 配線電極(第1電極)
62 電極(第2電極)
63 テーパー状の導入穴
64 電極
65 電極
66 隔壁部
67 基板
68 ランド
69 半田(導電性材料)
70 溝
71 半導体ウエハ
72 カバーウエハ
73 接合半導体ウエハ
14 Sensor substrates 15 and 16 First and second cover substrates 17A to 17D Hole 18 Beam 19 Movable piece 20A First detector 20B Second detectors 21a to 21d Through holes 22a to 22d Wiring electrodes 23 and 24 Recesses 25a to 25d Through hole 26 Adhesive 27 Solder 28 First wafer 29 Second wafer 30 Third wafer 31 Bonded wafer 32 Dicing saw 33 Electronic element packages 34a to 34d Electrodes 35a to 35d Wiring electrodes 36a to 36d Electrodes 38a to 38n, 39a -39n, 40a-40n Assembly 41 Joint assembly 42 Outer peripheral portion 43 of sensor substrate 14 Beam A Electronic device package 58 Device substrate 59 Cover substrate 60 Electronic device 61 Wiring electrode (first electrode)
62 electrode (second electrode)
63 Tapered introduction hole 64 Electrode 65 Electrode 66 Partition part 67 Substrate 68 Land 69 Solder (conductive material)
70 Groove 71 Semiconductor wafer 72 Cover wafer 73 Bonded semiconductor wafer

Claims (8)

検出手段が形成された板状のセンサー基板を中央にしてその上下に板状の第1,第2カバー基板を直接または間接的に接合した電子素子パッケージであって、
前記センサー基板には、
前記検出手段として少なくとも第1検出部と第2検出部と、
空間を介して前記検出手段を取り囲む枠と、
前記検出手段と前記枠を繋ぐ少なくとも2本の梁と、
前記枠に配設され前記検出手段に電気接続された電極と
を設け、
前記第1カバー基板あるいは前記第2カバー基板には、
端面の内壁が前記電極の少なくとも一部と接触する貫通孔を設けた
電子素子パッケージ。
An electronic element package in which a plate-like sensor substrate on which detection means is formed is centered, and plate-like first and second cover substrates are directly or indirectly joined to the upper and lower sides thereof,
In the sensor substrate,
As the detection means, at least a first detection unit and a second detection unit,
A frame surrounding the detection means via a space;
At least two beams connecting the detection means and the frame;
An electrode disposed on the frame and electrically connected to the detection means;
In the first cover substrate or the second cover substrate,
An electronic device package having a through hole in which an inner wall of an end surface is in contact with at least a part of the electrode.
前記電極を、
前記検出手段と空間を介して対向する前記枠の一部の辺と、前記枠の外周とで囲まれた領域に配設した
請求項1記載の電子素子パッケージ。
The electrode;
The electronic device package according to claim 1, wherein the electronic element package is disposed in a region surrounded by a side of a part of the frame facing the detection unit via a space and an outer periphery of the frame.
前記カバー基板の前記センサー基板との対向面で前記検出部に対応する位置に、凹部を形成した
請求項1記載の電子素子パッケージ。
The electronic device package according to claim 1, wherein a concave portion is formed at a position corresponding to the detection portion on a surface of the cover substrate facing the sensor substrate.
前記センサー基板は、
前記検出手段の部分がその周辺よりも厚みが薄く形成されている
請求項1記載の電子素子パッケージ。
The sensor substrate is
The electronic device package according to claim 1, wherein a portion of the detecting means is formed to be thinner than its periphery.
検出手段が形成された板状のセンサー基板を中央にしてその上下に板状の第1,第2カバー基板を直接または間接的に接合した電子素子パッケージを製作するに際し、
検出部が形成されたセンサー基板が多数取りされている第1のウエハを中央にしてその上下に、前記センサー基板に対応して第1,第2カバー基板が多数取りされている第2,第3のウエハを接合して接合ウエハを形成し、
前記接合ウエハを切断して電子素子パッケージに個片化する
電子素子パッケージの製造方法。
When manufacturing an electronic device package in which the plate-like sensor substrate on which the detection means is formed is centered and the plate-like first and second cover substrates are directly or indirectly joined to the upper and lower sides thereof,
A first wafer having a large number of sensor substrates on which detection portions are formed is centered on the top and bottom of the first wafer, and second and second cover substrates corresponding to the sensor substrate are numerous. 3 wafers are bonded to form a bonded wafer,
A method of manufacturing an electronic device package, wherein the bonded wafer is cut into individual electronic device packages.
電子素子が形成された素子基板とカバー基板とを接合し、
前記素子基板と前記カバー基板の隙間において隔壁部によって前記電子素子を取り囲んで封止するとともに、
前記カバー基板には前記素子基板の第1電極に対応した導入穴を有し、前記導入穴の形状を、前記素子基板に向かって径が小さくなる形状に構成するとともに、
前記導入穴の前記素子基板の側の端部が、前記カバー基板に形成された第2電極で閉塞されており、前記第1電極と前記第2電極が当接している
電子素子パッケージ。
Bonding the element substrate on which the electronic element is formed and the cover substrate,
Surrounding and sealing the electronic element by a partition wall in the gap between the element substrate and the cover substrate,
The cover substrate has an introduction hole corresponding to the first electrode of the element substrate, and the shape of the introduction hole is configured to have a diameter that decreases toward the element substrate.
An electronic element package in which an end of the introduction hole on the element substrate side is closed by a second electrode formed on the cover substrate, and the first electrode and the second electrode are in contact with each other.
前記導入穴の内周に素子基板に向かって延びる溝を形成したことを特徴とする
請求項6記載の電子素子パッケージ。
The electronic device package according to claim 6, wherein a groove extending toward the device substrate is formed in an inner periphery of the introduction hole.
電子素子が形成された素子基板とカバー基板とを接合し、前記素子基板と前記カバー基板の隙間において隔壁部によって前記電子素子を取り囲んで封止するとともに、前記カバー基板には前記素子基板の第1電極に対応して前記素子基板に向かって径が小さくなる形状の導入穴が形成された電子素子パッケージを、基板に形成されたランドに実装するに際し、
前記基板の実装位置の前記ランドに導電性材料を盛り、
前記導入穴を前記基板の側に向けて前記電子素子パッケージを前記基板の実装位置に押し付けて前記実装位置のランドに盛られた導電性材料を前記電子素子パッケージの前記導入穴から前記素子基板の前記第1電極の側に導いて前記導電性材料を介して前記基板のランドと前記素子基板の電子素子とを電気接続する
電子素子パッケージ実装方法。
The element substrate on which the electronic element is formed and the cover substrate are joined, and the electronic element is surrounded and sealed by a partition wall in a gap between the element substrate and the cover substrate. When mounting an electronic element package in which an introduction hole having a shape whose diameter decreases toward the element substrate corresponding to one electrode is formed on a land formed on the substrate,
A conductive material is stacked on the land at the mounting position of the substrate,
The conductive material stacked on the land at the mounting position by pressing the electronic element package against the mounting position of the substrate with the introduction hole directed toward the substrate is transferred from the introduction hole of the electronic element package to the element substrate. A method for mounting an electronic device package, wherein the electronic device package is led to the first electrode and electrically connects a land of the substrate and an electronic device of the device substrate through the conductive material.
JP2007309578A 2006-12-12 2007-11-30 Electronic device package Expired - Fee Related JP5072555B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012227341A (en) * 2011-04-19 2012-11-15 Showa Denko Kk Heat radiation device
JP7455585B2 (en) 2019-01-10 2024-03-26 ティーイー コネクティビティ ソリューソンズ ゲーエムベーハー How to interconnect sensor units and substrates and carriers

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006046995A (en) * 2004-08-02 2006-02-16 Seiko Instruments Inc Sealed-type mems and manufacturing method for sealed-type mems
JP2006170856A (en) * 2004-12-16 2006-06-29 Fujitsu Media Device Kk Acceleration sensor
JP2006202974A (en) * 2005-01-20 2006-08-03 Sanyo Electric Co Ltd Electronic device and manufacturing method thereof
WO2006114832A1 (en) * 2005-04-06 2006-11-02 Murata Manufacturing Co., Ltd. Acceleration sensor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006046995A (en) * 2004-08-02 2006-02-16 Seiko Instruments Inc Sealed-type mems and manufacturing method for sealed-type mems
JP2006170856A (en) * 2004-12-16 2006-06-29 Fujitsu Media Device Kk Acceleration sensor
JP2006202974A (en) * 2005-01-20 2006-08-03 Sanyo Electric Co Ltd Electronic device and manufacturing method thereof
WO2006114832A1 (en) * 2005-04-06 2006-11-02 Murata Manufacturing Co., Ltd. Acceleration sensor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012227341A (en) * 2011-04-19 2012-11-15 Showa Denko Kk Heat radiation device
JP7455585B2 (en) 2019-01-10 2024-03-26 ティーイー コネクティビティ ソリューソンズ ゲーエムベーハー How to interconnect sensor units and substrates and carriers

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