JP2008182155A - Optical-coupling semiconductor relay - Google Patents

Optical-coupling semiconductor relay Download PDF

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JP2008182155A
JP2008182155A JP2007016118A JP2007016118A JP2008182155A JP 2008182155 A JP2008182155 A JP 2008182155A JP 2007016118 A JP2007016118 A JP 2007016118A JP 2007016118 A JP2007016118 A JP 2007016118A JP 2008182155 A JP2008182155 A JP 2008182155A
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light
semiconductor relay
emitting element
housing
light emitting
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Yoshihiro Fujiwara
嘉宏 藤原
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Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical-coupling semiconductor relay with an easy manufacturing method, an excellent accuracy in size between elements, and a small and thin configuration. <P>SOLUTION: The optical-coupling semiconductor relay 1 has a light emitter 3, a light receiver 4 oppositely disposed to the light emitter 3, and a switching element 5 receiving an output from the light receiver 4. These elements are mounted in the inner space of a housing 2 having an opening 2c. The housing 2 has a recess 2b formed in an inner bottom 2a, the light emitter 3 is mounted in the recess 2b in a flip-chip structure, and the light receiver 4 is in the flip-chip structure across the recess 2b with its light receiving side inclined downward. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、発光素子、受光素子を筐体内に実装して構成した光結合型半導体リレーの改良に関するものである。   The present invention relates to an improvement in an optically coupled semiconductor relay configured by mounting a light emitting element and a light receiving element in a housing.

従来より、電気的アイソレーションに優れた光結合型の半導体リレーが種々提案され、種々の用途に採用されている。
図7は従来の光結合型半導体リレーの一例を示す縦断面図で、リードフレームを使用したものである。
Conventionally, various optically coupled semiconductor relays excellent in electrical isolation have been proposed and employed in various applications.
FIG. 7 is a longitudinal sectional view showing an example of a conventional optically coupled semiconductor relay using a lead frame.

この半導体リレー100は、それぞれのリードフレーム101,102に設けた発光素子103と受光素子104とを対向配置させ、透光性樹脂106を充填させて光伝達空間108を形成し、外部光が入り込むことを防止するための黒色などの遮光性樹脂107で封止している。また通電経路を形成するために、発光素子103、受光素子104、スイッチング素子105は、リードフレーム101,102上にダイボンディングされ、さらにワイヤ109でボンディングされている。   In this semiconductor relay 100, a light emitting element 103 and a light receiving element 104 provided on each of the lead frames 101 and 102 are arranged to face each other, and a light transmitting space is formed by filling a translucent resin 106 so that external light enters. In order to prevent this, it is sealed with a light shielding resin 107 such as black. In order to form an energization path, the light emitting element 103, the light receiving element 104, and the switching element 105 are die-bonded on the lead frames 101 and 102 and further bonded by a wire 109.

また、次の特許文献1に示す半導体リレーは、リードフレームに代えて基板上に発光素子、受光素子を実装させたもので、基板に凹部を設けて発光素子をその凹部に実装し、受光素子を発光素子に対向させて凹部を跨ぐように配置させ、かつ受光素子をフリップチップ実装することによって、小型化、薄型化および素子間の寸法精度の向上を図っている。
特開2001−326381号公報
Further, the semiconductor relay shown in the following Patent Document 1 has a light emitting element and a light receiving element mounted on a substrate instead of a lead frame. The substrate is provided with a recess, and the light emitting element is mounted in the recess. Is arranged so as to face the light emitting element so as to straddle the concave portion, and the light receiving element is flip-chip mounted, thereby reducing the size and thickness and improving the dimensional accuracy between the elements.
JP 2001-326381 A

しかしながら、上記従来のものでは、少なくとも発光素子は金属ワイヤで配線する構成であるため、製造に手間がかかるという問題があった。   However, the conventional device has a problem that it takes time to manufacture because at least the light emitting element is configured to be wired with a metal wire.

本発明は、このような問題を解決すべく提案されたもので、製造が容易で、素子間の寸法精度がよく、かつ小型化、薄型化が可能な光結合型半導体リレーを提供すること目的としている。   The present invention has been proposed to solve such problems, and an object thereof is to provide an optically coupled semiconductor relay that is easy to manufacture, has good dimensional accuracy between elements, and can be reduced in size and thickness. It is said.

上記目的を達成するために、請求項1に記載の光結合型半導体リレーは、発光素子と、該発光素子に対向する状態に配置される受光素子と、該受光素子からの出力を受けるスイッチング素子とを、開口部を有した筐体の内空間に実装した光結合型半導体リレーであって、筐体は、内底に凹部を形成しており、発光素子は凹部にフリップチップ実装され、受光素子はその受光面を下方に向けた状態で、凹部を跨ぐようにフリップチップ実装されていることを特徴としている。   In order to achieve the above object, an optically coupled semiconductor relay according to claim 1 includes a light emitting element, a light receiving element disposed in a state facing the light emitting element, and a switching element that receives an output from the light receiving element. Is mounted in the inner space of the housing having an opening, the housing has a recess formed in the inner bottom, and the light emitting element is flip-chip mounted in the recess to receive light. The element is characterized in that it is flip-chip mounted so as to straddle the recess with its light receiving surface facing downward.

請求項2に記載の光結合型半導体リレーは、発光素子と受光素子との間の凹部を含む光伝達空間には透光性樹脂層が充填形成されている。   In the optically coupled semiconductor relay according to claim 2, a light transmitting space including a concave portion between the light emitting element and the light receiving element is filled with a translucent resin layer.

請求項3に記載の光結合型半導体リレーは、筐体の開口部に透光性樹脂層を含むようにして遮光性樹脂を封入している。   In the optically coupled semiconductor relay according to the third aspect, the light shielding resin is sealed so as to include a light transmitting resin layer in the opening of the housing.

請求項4に記載の光結合型半導体リレーは、筐体の開口部に遮光蓋を被せた構造としている。   The optically coupled semiconductor relay according to claim 4 has a structure in which a light-shielding lid is covered on the opening of the housing.

請求項5に記載の光結合型半導体リレーは、導電性のシールド膜が筐体の外周面に形成されている。   In the optically coupled semiconductor relay according to claim 5, a conductive shield film is formed on the outer peripheral surface of the casing.

本発明の光結合型半導体リレーによれば、次のような効果を奏する。   The optically coupled semiconductor relay of the present invention has the following effects.

すなわち、筐体の内部に凹部を設けて、受光素子、発光素子を上下に対向実装させているため寸法精度がきわめてよく、さらに、受光素子、発光素子ともにフリップチップ実装しているため、金属ワイヤによる配線が不要となる。   In other words, a concave portion is provided inside the housing, and the light receiving element and the light emitting element are mounted vertically opposite to each other so that the dimensional accuracy is very good. Further, since both the light receiving element and the light emitting element are flip-chip mounted, the metal wire Wiring by is unnecessary.

フリップチップ実装するため、各素子はワイヤで入出力するための配線スペースが不要となり、そのため小型化された素子を使用することができ、リレーそのものも小型化、薄型化できる。そしてさらに、受光素子、発光素子ともにフリップチップ実装する構成であるため、実装工程が格段に簡略化できる。また、フリップチップ実装することで配線を短くでき、電気的特性の向上も図れる。   Since flip-chip mounting is used, each element does not require a wiring space for inputting and outputting with a wire, so that a smaller element can be used, and the relay itself can be reduced in size and thickness. Furthermore, since both the light receiving element and the light emitting element are configured to be flip-chip mounted, the mounting process can be greatly simplified. In addition, the wiring can be shortened by flip chip mounting, and the electrical characteristics can be improved.

また、発光素子、受光素子は、側方を筐体によって囲まれているため、遮光性樹脂層あるいは遮光蓋で封止すれば、内部空間にほぼ密閉された状態で保護され得、そのため変形、損傷のおそれがきわめて低い。   In addition, since the light emitting element and the light receiving element are surrounded by a casing on the side, if sealed with a light shielding resin layer or a light shielding lid, the light emitting element and the light receiving element can be protected in a state of being almost sealed in the internal space. Very low risk of damage.

以下に、本発明の実施の形態について、添付図面を参照しながら説明する。   Embodiments of the present invention will be described below with reference to the accompanying drawings.

図1は、本発明の一例を示す光結合型半導体リレーの概略縦断面図である。   FIG. 1 is a schematic longitudinal sectional view of an optically coupled semiconductor relay showing an example of the present invention.

同半導体リレー1は、発光素子3、受光素子4およびスイッチング素子5を立体型の回路基板2を構成した筐体2の内方に実装したものである。   In the semiconductor relay 1, a light emitting element 3, a light receiving element 4, and a switching element 5 are mounted on the inner side of a housing 2 that constitutes a three-dimensional circuit board 2.

すなわち、この立体型回路基板2は、プリント基板、セラミック基板などよりなり、開口部2cを有した中空状の筐体2として形成され、周壁2dと底部2eとを有し、その内底2aには1つの凹部2bが形成されている。発光素子3はその凹部2b(下段)に実装され、受光素子4は受光面を下方に向けて凹部2bを跨ぐようにして内底2a(上段)に発光素子3と対向して実装され、さらに受光素子4からの電気的出力を受けて動作するスイッチング素子5は、内底2a(上段)の他の箇所に実装されている。   That is, the three-dimensional circuit board 2 is made of a printed board, a ceramic board, or the like, and is formed as a hollow casing 2 having an opening 2c, and has a peripheral wall 2d and a bottom 2e. Is formed with one recess 2b. The light emitting element 3 is mounted in the recess 2b (lower stage), and the light receiving element 4 is mounted on the inner bottom 2a (upper stage) facing the light emitting element 3 with the light receiving surface facing downward and straddling the recess 2b. The switching element 5 that operates in response to an electrical output from the light receiving element 4 is mounted at another location on the inner bottom 2a (upper stage).

筐体2内部の実装内底面には、所定の配線パターン(不図示)が形成され、各素子3,4,5がはんだ等のバンプ6を介して、配線パターンにフリップチップ実装されている。なお、筐体2の内底2a面と外底2f面とを電気的接続するためのスルーホール(不図示)も種々、形成されている。   A predetermined wiring pattern (not shown) is formed on the inner bottom surface of the mounting inside the housing 2, and each element 3, 4, 5 is flip-chip mounted on the wiring pattern via bumps 6 such as solder. Various through holes (not shown) for electrically connecting the inner bottom 2a surface and the outer bottom 2f surface of the housing 2 are also formed.

また、筐体2内部には、これらの3素子3,4,5を実装した状態で、光伝達空間9を確保するために透明シリコーンなどによる透光性樹脂(JCR:ジャンクション・コーティング・レジン)層7が形成され、さらにその上方を、開口部2cを塞ぐように黒色などのエポキシ系の遮光性樹脂層8で封止している。   In addition, a translucent resin (JCR: junction coating resin) made of transparent silicone or the like is provided in the housing 2 to secure the light transmission space 9 with these three elements 3, 4 and 5 mounted. A layer 7 is formed, and the upper portion thereof is further sealed with an epoxy-based light shielding resin layer 8 such as black so as to close the opening 2c.

図2は、同半導体リレー1の概略製造手順を示す図である。なお、図2(a)〜(e)には、平面図と断面図とを上下に対応させて示している。   FIG. 2 is a diagram showing a schematic manufacturing procedure of the semiconductor relay 1. 2A to 2E show a plan view and a cross-sectional view corresponding to each other vertically.

筐体2内に設ける凹部2bは、内底2aの一部をくりぬいたように形成されている。本例では対向端間を結ぶ凹溝のごとく形成されているが、孤立穴に形成してもよい。この凹部2bは、複数基板の重ね合わせ、底部2eの一部削り取りなどによって成形される。   The recessed part 2b provided in the housing | casing 2 is formed so that a part of inner bottom 2a may be hollowed out. In this example, the groove is formed as a concave groove connecting opposite ends, but may be formed in an isolated hole. The recess 2b is formed by overlapping a plurality of substrates, partially cutting off the bottom 2e, or the like.

この凹部2bに収容するように発光素子3をフリップチップ実装し、その上方に、つまり凹部2bを跨ぐように受光素子4を内底2a上段にフリップチップ実装し、さらに、受光素子3と同一実装面にスイッチング素子5をフリップチップ実装する(以上、図2(a)〜(c))。この状態で、発光素子3と受光素子4とは対向配置され、その間には光伝達空間9が確保される。   The light-emitting element 3 is flip-chip mounted so as to be accommodated in the recess 2b, and the light-receiving element 4 is flip-chip mounted above the light-receiving element 4 so as to straddle the recess 2b. The switching element 5 is flip-chip mounted on the surface (as described above, FIGS. 2A to 2C). In this state, the light emitting element 3 and the light receiving element 4 are arranged to face each other, and a light transmission space 9 is secured between them.

ついで、3素子3,4,5が実装された筐体2の内部空間に、透明シリコーンを粘性の低い液状化状態で注入してゆき、光伝達空間9に確実に充填し、さらに受光素子4、スイッチング素子5の高さの途中まで充填し、その後、熱や紫外線などを当てて、保形性を有する程度に硬化させて透光性樹脂層7を形成する(以上、図2(d))。   Next, transparent silicone is injected into the internal space of the housing 2 on which the three elements 3, 4, and 5 are mounted in a liquefied state having a low viscosity, and the light transmission space 9 is reliably filled. Then, the switching element 5 is filled in the middle of the height, and thereafter, heat, ultraviolet rays, etc. are applied and cured to the extent that it has a shape-retaining property to form the translucent resin layer 7 (see FIG. 2D). ).

そして、その上方空間にエポキシ系の遮光性樹脂を封入して、天面を露出された受光素子4、スイッチング素子5を含む空間を封止するとともに、筐体2の開口部2cを塞ぐ(以上。図2(e))。こうして、透光性樹脂層7、遮光性樹脂層8の2層を形成する。   Then, an epoxy-based light shielding resin is sealed in the upper space to seal the space including the light receiving element 4 and the switching element 5 with the top surface exposed, and close the opening 2c of the housing 2 (above). FIG. 2 (e)). In this way, two layers of the light transmitting resin layer 7 and the light shielding resin layer 8 are formed.

このように、発光素子3、受光素子4を、筐体2の内部空間の基板上に実装しているため、光伝達空間9の寸法精度は向上し、フリップチップ実装することともあいまって、リレーの小型化にも寄与できる。   As described above, since the light emitting element 3 and the light receiving element 4 are mounted on the substrate in the internal space of the housing 2, the dimensional accuracy of the light transmission space 9 is improved. Can also contribute to downsizing.

また、フリップチップ実装することにより、筐体2の内部空間では金属ワイヤを配線に使用する必要がなく、製造工程を短縮できる。また、フリップチップ実装することで配線を短くでき、電気的特性の向上も図れる。さらに、金属ワイヤを使用しないため、ヒートサイクルなどによる透明シリコーンの伸縮が要因となるワイヤ切れも当然に発生しない。   Further, by performing flip chip mounting, it is not necessary to use a metal wire for wiring in the internal space of the housing 2, and the manufacturing process can be shortened. In addition, the wiring can be shortened by flip chip mounting, and the electrical characteristics can be improved. Furthermore, since no metal wire is used, wire breakage due to expansion and contraction of the transparent silicone due to heat cycle or the like does not naturally occur.

また、発光素子3、受光素子4、スイッチング素子5は、全側方を筐体2の周壁2dによって囲まれているため、遮光性樹脂を封入して開口部2cを塞げば、筐体2の内部空間に、ほぼ密閉された状態で保護され得、変形、損傷するおそれがきわめて低い。   Further, since the light emitting element 3, the light receiving element 4, and the switching element 5 are surrounded on all sides by the peripheral wall 2d of the casing 2, if the light shielding resin is sealed to close the opening 2c, The inner space can be protected in an almost sealed state, and the risk of deformation or damage is extremely low.

図3は、上記の例で使用した筐体を用いた光結合型半導体リレーの他例を示す図である。平面図は省略する。   FIG. 3 is a diagram showing another example of the optically coupled semiconductor relay using the casing used in the above example. A plan view is omitted.

図3(a)、(b)は、遮光性樹脂に代えて、開口部2cの閉塞が可能な遮光蓋10で開口部2cに被せたもので、(a)では透明シリコーンによる透光性樹脂層7を充填、形成しており、(b)では透光性樹脂層7を形成しないようにしている。   3 (a) and 3 (b) show the case where the opening 2c is covered with a light shielding lid 10 capable of closing the opening 2c instead of the light shielding resin. In FIG. 3 (a), the transparent resin made of transparent silicone is used. The layer 7 is filled and formed. In (b), the translucent resin layer 7 is not formed.

このように、遮光蓋10を設けたものでは、塵、埃など光伝達空間に入り込まないように透明シリコーンによる透光性樹脂層7を形成して、光結合精度を高めてもよいし、製造工程を短縮するために、透明シリコーンを充填せずに光伝達空間9を確保するようにしてもよい。   Thus, in the case where the light-shielding lid 10 is provided, the light-transmitting resin layer 7 made of transparent silicone may be formed so as not to enter the light transmission space such as dust, dust, and the optical coupling accuracy may be improved. In order to shorten the process, the light transmission space 9 may be secured without filling with transparent silicone.

また、図1〜図3で示した光結合型半導体リレー1において、筐体2の外周面2gに、銅箔などの導電性のシールド膜による外皮を形成して、電磁波を遮断できる構造としてもよい。   Further, in the optically coupled semiconductor relay 1 shown in FIGS. 1 to 3, the outer peripheral surface 2 g of the housing 2 may be formed with a skin made of a conductive shield film such as a copper foil to block electromagnetic waves. Good.

図4(a)〜(c)はさらに他の例であり、これらは上記の3例とは筐体2の内部形状を異ならせている。   FIGS. 4A to 4C are still other examples, and these are different from the above three examples in the internal shape of the housing 2.

すなわち、これらの光結合型半導体リレー1は、図示するように、発光素子3を収容する凹部2bを2つの載置台11,11によって形成している。換言すれば、内底2aを凹凸交互となるように成形している。受光素子3は、その両端を2つの載置台11,11に載せ置いて、フリップチップ実装され、スイッチング素子5は、中央の載置台11を仕切りとして、発光素子4をフリップチップ実装した凹部2bの反対側にフリップチップ実装される。つまり、発光素子3は下段に、受光素子4は上段に、スイッチング素子5は下段に実装される。   That is, in these optically coupled semiconductor relays 1, as shown in the figure, a recess 2 b that accommodates the light emitting element 3 is formed by two mounting tables 11. In other words, the inner bottom 2a is formed so as to be alternately uneven. The light receiving element 3 is mounted on the two mounting bases 11 and 11 by flip chip mounting on both ends thereof, and the switching element 5 is formed in the recess 2b in which the light emitting element 4 is flip chip mounted using the central mounting base 11 as a partition. Flip chip mounted on the opposite side. That is, the light emitting element 3 is mounted on the lower stage, the light receiving element 4 is mounted on the upper stage, and the switching element 5 is mounted on the lower stage.

このような形状の筐体2の内底2aは、主基板と載置台11,11の重ね合わせ、あるいは底部2eの内底側の一部削り取りなどによって成形できる。   The inner bottom 2a of the housing 2 having such a shape can be formed by overlapping the main substrate and the mounting tables 11 and 11, or by partially scraping the inner bottom side of the bottom 2e.

図4(a)〜(c)に示した3例は、上記図1、図3(a)、(b)に対応したもので、(a)は透明シリコーンによる透光性樹脂層を形成して、さらに遮光性樹脂を封入したもの、(b)は透明シリコーンによる透光性樹脂層を形成して遮光蓋10で閉塞したもの、(c)は透明シリコーンを充填せずに遮光蓋10で閉塞したものである。   The three examples shown in FIGS. 4 (a) to 4 (c) correspond to FIGS. 1, 3 (a), and (b), and (a) forms a translucent resin layer made of transparent silicone. Further, a light-shielding resin encapsulated, (b) a transparent resin layer formed of transparent silicone and closed with a light-shielding lid 10, (c) is a light-shielding lid 10 without being filled with transparent silicone. It is obstructed.

なお、図4(a)、(b)のものでは、スイッチング素子5を下段に実装するため、スイッチング素子5の全体が透光性樹脂層7に包含される。   4A and 4B, since the switching element 5 is mounted in the lower stage, the entire switching element 5 is included in the translucent resin layer 7.

図4の3例は、上記図1、図3(a)、(b)に示した3例と同様の効果が期待でき、さらに、スイッチング素子は図1の例よりも薄厚の底に実装されるため、筐体2の外底面2fまでの配線パターンも短くすることができ、さらなる電気的特性の向上を図れる。   The three examples in FIG. 4 can be expected to have the same effect as the three examples shown in FIGS. 1, 3A, and 3B, and the switching element is mounted on a thinner bottom than the example in FIG. Therefore, the wiring pattern to the outer bottom surface 2f of the housing 2 can also be shortened, and the electrical characteristics can be further improved.

ついで、本発明に関する参考発明例について、図5、図6を参照しながら説明する。   Next, a reference invention example relating to the present invention will be described with reference to FIGS.

図5に示す3例は、筐体2に1つの凹部2bを形成したもので、凹部2b(下段)に発光素子3を金属ワイヤ12で実装し、凹部2bを跨ぐように受光素子4を上段にフリップチップ実装し、さらにスイッチング素子5を上段にフリップチップ実装している。図5(a)は透明シリコーンの充填と遮光性樹脂による封止をしたもの、(b)は透明シリコーンを充填して遮光蓋10で閉塞したもの、(c)は透明シリコーンを充填せずに遮光蓋10で閉塞したものである。   In the three examples shown in FIG. 5, one recess 2 b is formed in the housing 2, the light emitting element 3 is mounted on the recess 2 b (lower stage) with the metal wire 12, and the light receiving element 4 is placed on the upper stage so as to straddle the recess 2 b. The switching element 5 is flip-chip mounted on the upper stage. FIG. 5 (a) is a transparent silicone filled and sealed with a light shielding resin, (b) is filled with transparent silicone and closed with a light shielding lid 10, and (c) is not filled with transparent silicone. The light shielding lid 10 is closed.

また図6に示す3例は、2つの載置台11,11によって、発光素子3を実装するための凹部2bを形成したもので、凹部2b(下段)に発光素子3を金属ワイヤ12で実装し、凹部2bを跨ぐように受光素子4を上段にフリップチップ実装し、さらにスイッチング素子5を下段にフリップチップ実装している。図6(a)は透明シリコーンの充填と遮光性樹脂による封止をしたもの、(b)は透明シリコーンを充填して遮光蓋10で閉塞したもの、(c)は透明シリコーンを充填せずに遮光蓋10で閉塞したものである。   Further, in the three examples shown in FIG. 6, the recess 2 b for mounting the light emitting element 3 is formed by the two mounting tables 11, 11. The light emitting element 3 is mounted with the metal wire 12 in the recess 2 b (lower stage). The light receiving element 4 is flip-chip mounted on the upper stage so as to straddle the recess 2b, and the switching element 5 is flip-chip mounted on the lower stage. FIG. 6 (a) shows a transparent silicone filled and sealed with a light-shielding resin, (b) is filled with transparent silicone and closed with a light-shielding lid 10, and (c) is not filled with transparent silicone. The light shielding lid 10 is closed.

これら6例についても同様に、寸法精度、電気的特性の向上が図れる。また、発光素子3、受光素子4、スイッチング素子5は、側方を筐体2の周壁2dによって囲まれているため、遮光性樹脂層8あるいは遮光蓋10で封止すれば、内部空間にほぼ密閉された状態で保護され得、変形、損傷のおそれがきわめて低い。   Similarly, these six examples can improve dimensional accuracy and electrical characteristics. Further, since the light emitting element 3, the light receiving element 4, and the switching element 5 are surrounded on the sides by the peripheral wall 2d of the housing 2, if sealed with the light shielding resin layer 8 or the light shielding lid 10, the inner space is almost completely filled. It can be protected in a sealed state and has a very low risk of deformation and damage.

なお、図5、図6における上記以外の構成部については、図1〜図4のものと同様であるため、それらについて同一の符号を付して、その説明を省略する。   In addition, since it is the same as that of the thing of FIGS. 1-4 about the structure part other than the above in FIG. 5, FIG. 6, it attaches | subjects the same code | symbol about them, and abbreviate | omits the description.

本発明の一例を示す光結合型半導体リレーの概略縦断面図である。It is a schematic longitudinal cross-sectional view of the optical coupling type semiconductor relay which shows an example of this invention. 同光結合型半導体リレーの製造手順を示す図である。It is a figure which shows the manufacture procedure of the optical coupling type semiconductor relay. (a)、(b)は本発明の光結合型半導体リレーの他例を示す図である。(A), (b) is a figure which shows the other example of the optical coupling type semiconductor relay of this invention. (a)〜(c)は本発明の光結合型半導体リレーのさらなる他例を示す図である。(A)-(c) is a figure which shows the further another example of the optical coupling type semiconductor relay of this invention. (a)〜(c)は本発明に関する参考発明例を示す図である。(A)-(c) is a figure which shows the reference invention example regarding this invention. (a)〜(c)は本発明に関する参考発明例を示す図である。(A)-(c) is a figure which shows the reference invention example regarding this invention. 従来の光結合型半導体リレーの一例を示す縦断面図である。It is a longitudinal cross-sectional view which shows an example of the conventional optical coupling type semiconductor relay.

符号の説明Explanation of symbols

1 光結合型半導体リレー
2 立体回路基板(筐体)
2a 内底
2b 凹部
2c 開口部
2d 周壁
2e 底部
2f 外底
2g 外周面
3 発光素子
4 受光素子
5 スイッチング素子
6 バンプ
7 透光性樹脂層
8 遮光性樹脂層
9 光伝達空間
10 遮光蓋
11 載置台
1 Optical coupling type semiconductor relay 2 3D circuit board (housing)
2a inner bottom 2b recess 2c opening 2d peripheral wall 2e bottom 2f outer bottom 2g outer peripheral surface 3 light emitting element 4 light receiving element 5 switching element 6 bump 7 translucent resin layer 8 light shielding resin layer 9 light transmission space 10 light shielding lid 11 mounting base

Claims (5)

発光素子と、該発光素子に対向配置された受光素子と、該受光素子からの出力を受けるスイッチング素子とを、開口部を有した筐体の内空間に実装した光結合型半導体リレーであって、
上記筐体は、内底に凹部を形成しており、
上記発光素子は、上記凹部にフリップチップ実装されるとともに、
上記受光素子は、その受光面を下方に向けた状態で、上記凹部を跨ぐようにフリップチップ実装されていることを特徴とする光結合型半導体リレー。
An optically coupled semiconductor relay in which a light emitting element, a light receiving element disposed opposite to the light emitting element, and a switching element that receives an output from the light receiving element are mounted in an inner space of a housing having an opening. ,
The casing has a recess in the inner bottom,
The light emitting element is flip-chip mounted in the recess,
The optically coupled semiconductor relay, wherein the light receiving element is flip-chip mounted so as to straddle the concave portion with the light receiving surface facing downward.
請求項1において、
上記発光素子と上記受光素子との間の上記凹部を含む光伝達空間には、透光性樹脂層が充填形成されていることを特徴とする光結合型半導体リレー。
In claim 1,
An optically coupled semiconductor relay, wherein a light transmitting space including the concave portion between the light emitting element and the light receiving element is filled with a translucent resin layer.
請求項2において、
上記筐体の開口部には、上記透光性樹脂層を含むようにして遮光性樹脂を封入していることを特徴とする光結合型半導体リレー。
In claim 2,
A light-coupled semiconductor relay, wherein a light-shielding resin is sealed in the opening of the housing so as to include the light-transmitting resin layer.
請求項1、2のいずれか1項において、
上記筐体の開口部に、遮光蓋を被せていることを特徴とする光結合型半導体リレー。
In any one of Claims 1, 2,
An optically coupled semiconductor relay, wherein an opening of the housing is covered with a light shielding lid.
請求項1〜4のいずれか1項において、
上記筐体は、導電性のシールド膜が外周面に形成されていることを特徴とする光結合型半導体リレー。
In any one of Claims 1-4,
An optically coupled semiconductor relay, wherein the casing is formed with a conductive shield film on an outer peripheral surface.
JP2007016118A 2007-01-26 2007-01-26 Optical-coupling semiconductor relay Withdrawn JP2008182155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017157799A (en) * 2016-03-04 2017-09-07 浜松ホトニクス株式会社 Semiconductor light receiving module and method of manufacturing the same
WO2018046216A1 (en) * 2016-09-06 2018-03-15 Siemens Aktiengesellschaft Optocoupler having an optical transmission link and electrical connections, and electronic module in which such an optocoupler is installed

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017157799A (en) * 2016-03-04 2017-09-07 浜松ホトニクス株式会社 Semiconductor light receiving module and method of manufacturing the same
WO2017150044A1 (en) * 2016-03-04 2017-09-08 浜松ホトニクス株式会社 Semiconductor light receiving module and method for manufacturing semiconductor light receiving module
WO2018046216A1 (en) * 2016-09-06 2018-03-15 Siemens Aktiengesellschaft Optocoupler having an optical transmission link and electrical connections, and electronic module in which such an optocoupler is installed

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