JP2008181558A5 - - Google Patents
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- JP2008181558A5 JP2008181558A5 JP2008090853A JP2008090853A JP2008181558A5 JP 2008181558 A5 JP2008181558 A5 JP 2008181558A5 JP 2008090853 A JP2008090853 A JP 2008090853A JP 2008090853 A JP2008090853 A JP 2008090853A JP 2008181558 A5 JP2008181558 A5 JP 2008181558A5
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- multiprocessor
- memory
- shared memory
- data
- data transfer
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Claims (7)
前記各プロセッシングエレメントに接続され、前記各プロセッシングエレメントによって共有される集中共有メモリと、を備えるマルチプロセッサであって、
前記マルチプロセッサ用のコンパイラがタスクのスケジューリングをし、
前記スケジューリングの結果に基づいて、前記分散共有メモリとの間でデータを転送することによって、前記マルチプロセッサで共通に必要とされるデータを前記各ＣＰＵへ必要とされるとき以前に提供することを特徴とするマルチプロセッサ。 CPU, network interface connected to the CPU, distributed shared memory for storing data, local data memory accessible only from the processing element, and data transfer connected to one port of the distributed shared memory A plurality of processing elements comprising a controller;
A multi-processor comprising: a centralized shared memory connected to each processing element and shared by each processing element;
The multiprocessor compiler schedules tasks,
Based on the result of the scheduling, by transferring data to and from the distributed shared memory, the data that is commonly required by the multiprocessor is provided to each CPU before it is needed. A featured multiprocessor.
前記分散共有メモリの一つのポートには、前記データ転送コントローラが接続され、
前記分散共有メモリの他のポートには、前記ＣＰＵが接続されることを特徴とする請求項１に記載のマルチプロセッサ。 The distributed shared memory is composed of a dual port memory,
The data transfer controller is connected to one port of the distributed shared memory,
The multiprocessor according to claim 1, wherein the CPU is connected to another port of the distributed shared memory.
前記ローカルデータメモリの一つのポートには、前記データ転送コントローラが接続され、
前記ローカルデータメモリの他のポートには、前記ＣＰＵが接続されることを特徴とす
る請求項１又は２に記載のマルチプロセッサ。 The local data memory is a dual port memory,
The data transfer controller is connected to one port of the local data memory,
The multiprocessor according to claim 1, wherein the CPU is connected to another port of the local data memory.
前記アジャスタブルプリフェッチ命令キャッシュは、将来実行される命令列を事前読み出しできるエリアとして複数のウェイを使用し、 The adjustable prefetch instruction cache uses a plurality of ways as an area where an instruction sequence to be executed in the future can be read in advance,
通常のキャッシュエリアとして複数のウェイを使用することを特徴とする請求項１から４のいずれか一つに記載のマルチプロセッサ。 5. The multiprocessor according to claim 1, wherein a plurality of ways are used as a normal cache area.
前記集中共有メモリは、第１集中共有メモリと第２集中共有メモリとを含み、 The centralized shared memory includes a first centralized shared memory and a second centralized shared memory;
前記第１集中共有メモリは、前記マルチプロセッサ内に設けられ、当該マルチプロセッサ内の各プロセッシングエレメントに接続され、前記各プロセッシングエレメントによって共有されるものであって、 The first centralized shared memory is provided in the multiprocessor, is connected to each processing element in the multiprocessor, and is shared by the processing elements,
前記第２集中共有メモリは、前記マルチプロセッサ外に設けられ、各マルチプロセッサに接続され、前記各マルチプロセッサ内のプロセッシングエレメントによって共有されるものであって、 The second central shared memory is provided outside the multiprocessor, connected to each multiprocessor, and shared by processing elements in each multiprocessor,
前記各ローカルデータメモリ、前記各分散共有メモリ、前記各第１集中共有メモリ及び前記第２集中共有メモリが、各プロセッシングエレメントから直接読み書きできるように配置されていることを特徴とするマルチプロセッサシステム。 Each of the local data memory, each of the distributed shared memory, each of the first centralized shared memory, and the second centralized shared memory is arranged so as to be directly readable and writable from each processing element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008090853A JP4784842B2 (en) | 2008-03-31 | 2008-03-31 | Multiprocessor and multiprocessor system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008090853A JP4784842B2 (en) | 2008-03-31 | 2008-03-31 | Multiprocessor and multiprocessor system |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP36370299A Division JP4784792B2 (en) | 1999-12-22 | 1999-12-22 | Multiprocessor |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008118007A Division JP4304347B2 (en) | 2008-04-30 | 2008-04-30 | Multiprocessor |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008181558A JP2008181558A (en) | 2008-08-07 |
| JP2008181558A5 true JP2008181558A5 (en) | 2008-10-09 |
| JP4784842B2 JP4784842B2 (en) | 2011-10-05 |
Family
ID=39725341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008090853A Expired - Lifetime JP4784842B2 (en) | 2008-03-31 | 2008-03-31 | Multiprocessor and multiprocessor system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4784842B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015038646A (en) * | 2010-11-30 | 2015-02-26 | 株式会社東芝 | Information processing apparatus and information processing method |
| KR102082859B1 (en) | 2013-01-07 | 2020-02-28 | 삼성전자주식회사 | System on chip including a plurality of heterogeneous cores and operating method therof |
| JP6018022B2 (en) | 2013-06-14 | 2016-11-02 | 株式会社デンソー | Parallel compilation method, parallel compiler, parallel compilation device, and in-vehicle device |
-
2008
- 2008-03-31 JP JP2008090853A patent/JP4784842B2/en not_active Expired - Lifetime
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