JP2008181558A5 - - Google Patents

Download PDF

Info

Publication number
JP2008181558A5
JP2008181558A5 JP2008090853A JP2008090853A JP2008181558A5 JP 2008181558 A5 JP2008181558 A5 JP 2008181558A5 JP 2008090853 A JP2008090853 A JP 2008090853A JP 2008090853 A JP2008090853 A JP 2008090853A JP 2008181558 A5 JP2008181558 A5 JP 2008181558A5
Authority
JP
Japan
Prior art keywords
multiprocessor
memory
shared memory
data
data transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008090853A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008181558A (ja
JP4784842B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2008090853A priority Critical patent/JP4784842B2/ja
Priority claimed from JP2008090853A external-priority patent/JP4784842B2/ja
Publication of JP2008181558A publication Critical patent/JP2008181558A/ja
Publication of JP2008181558A5 publication Critical patent/JP2008181558A5/ja
Application granted granted Critical
Publication of JP4784842B2 publication Critical patent/JP4784842B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

JP2008090853A 2008-03-31 2008-03-31 マルチプロセッサ及びマルチプロセッサシステム Expired - Lifetime JP4784842B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008090853A JP4784842B2 (ja) 2008-03-31 2008-03-31 マルチプロセッサ及びマルチプロセッサシステム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008090853A JP4784842B2 (ja) 2008-03-31 2008-03-31 マルチプロセッサ及びマルチプロセッサシステム

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP36370299A Division JP4784792B2 (ja) 1999-12-22 1999-12-22 マルチプロセッサ

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2008118007A Division JP4304347B2 (ja) 2008-04-30 2008-04-30 マルチプロセッサ

Publications (3)

Publication Number Publication Date
JP2008181558A JP2008181558A (ja) 2008-08-07
JP2008181558A5 true JP2008181558A5 (de) 2008-10-09
JP4784842B2 JP4784842B2 (ja) 2011-10-05

Family

ID=39725341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008090853A Expired - Lifetime JP4784842B2 (ja) 2008-03-31 2008-03-31 マルチプロセッサ及びマルチプロセッサシステム

Country Status (1)

Country Link
JP (1) JP4784842B2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015038646A (ja) * 2010-11-30 2015-02-26 株式会社東芝 情報処理装置及び情報処理方法
KR102082859B1 (ko) 2013-01-07 2020-02-28 삼성전자주식회사 복수의 이종 코어들을 포함하는 시스템 온 칩 및 그 동작 방법
JP6018022B2 (ja) 2013-06-14 2016-11-02 株式会社デンソー 並列化コンパイル方法、並列化コンパイラ、並列化コンパイル装置、及び、車載装置

Similar Documents

Publication Publication Date Title
TWI628594B (zh) 用戶等級分叉及會合處理器、方法、系統及指令
US10725919B2 (en) Processors having virtually clustered cores and cache slices
TWI603207B (zh) 用於最大預測的效能增益之異質多處理器運算平台中之應用程式排程
US9996487B2 (en) Coherent fabric interconnect for use in multiple topologies
JP2010102719A5 (de)
JP2010532905A5 (de)
US10031888B2 (en) Parallel memory systems
WO2007092528A9 (en) Thread optimized multiprocessor architecture
JP2008176699A5 (de)
McCalpin Memory bandwidth and system balance in hpc systems
WO2005081105A3 (en) Methods and apparatus for task management in a multi-processor system
JP2007156824A5 (de)
Talpes et al. Dojo: The microarchitecture of tesla’s exa-scale computer
EP3186704B1 (de) Verarbeitungskern für mehrfache, gruppierte very-long-instruction-words
JP2014503103A (ja) 階層的キャッシュ設計におけるキャッシュ間の効率的通信のための方法および装置
JP2008181558A5 (de)
CN103902502B (zh) 一种可扩展的分离式异构千核系统
Islam et al. Improving node-level mapreduce performance using processing-in-memory technologies
Woolley GPU optimization fundamentals
US20170300330A1 (en) Isa extensions for synchronous coalesced accesses
Ottaviano et al. ControlPULP: a RISC-V power controller for HPC processors with parallel control-law computation acceleration
Melot et al. Investigation of main memory bandwidth on Intel Single-Chip Cloud Computer.
Munir et al. High-performance optimizations on tiled many-core embedded systems: a matrix multiplication case study
Saidi et al. Optimizing two-dimensional DMA transfers for scratchpad Based MPSoCs platforms
He et al. A 98 GMACs/W 32-core vector processor in 65 nm CMOS