JP2008177716A - Multiplex transmission device, and bus capacity setting or changing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiplex transmission device, and a bus capacity setting or changing method thereof such that various interface boards differing in speed can be inserted into arbitrary slots without providing dedicated mount slots respectively and without causing a decrease in transmission efficiency of a low-speed system interface board. <P>SOLUTION: A plurality of sub-ports (Sub-Port) of constant transmission capacity is connected to main ports (Main-Port) where a plurality of kinds of interface boards 1-1 to 1-5 differing in speed, and each of the main ports performs speed conversion and format conversion of main data with multiplicity corresponding to the number of the connected sub-ports. Connection configurations between the main ports and sub-ports are determined by an FPGA etc., so that they can be set or changed through external programming, and the number of the sub-ports connected to the respective main ports is set or changed according to transmission speeds of the interface boards to be mounted on the respective main ports. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention includes an Ethernet (registered trademark) standardized as IEEE 802.3 in addition to a typical synchronous communication interface board such as a telephone communication interface board of 64 Kbps or an interface board of a transmission rate of 1.5 Mbps or 6.3 Mbps. Used in SDH hybrid multiplex transmission equipment that accommodates connection type interface boards and multiplexes and transmits main data transmitted and received by these various interface boards to an SDH (Synchronous Digital Hierarchy) optical interface. The bus capacity to send and receive main data is variable for each interface board, and it is efficient for low-speed (eg, 64 kbps to 6.3 Mbps) data to high-speed (eg, 200 Mbps to 2.4 Gbps) data lines. Accommodates various transmission systems Set or to change the method of multiplex transmission apparatus and a bus capacity that can correspond to Temu.

  FIG. 8 shows a configuration example of a conventional multiplex transmission apparatus. A conventional multiplex transmission apparatus accommodates various interface boards mounted on a back wiring board (BWB) connected to ports (Ports 0 to 15) each having four main data buses.

  An input port (port where main data is input) and an output port (port where main data is input) of ports (Ports 0 to 15) to which various interface boards are connected are connected via a space switch (SSW). The input and output ports of each port (Port 0 to 15) are connected by a space switch (SSW) so that main data input from any input port is connected and output to any output port. Connected selectively.

  A low-speed data system (64 kbps to 6.3 Mbps) interface board and a high-speed data system (150 Mbps / 600 Mbps) interface board are mixed so that each port (Port 0 to 15) can accommodate any type of interface board. Therefore, the bus capacity of each port (Port 0 to 15) is fixed according to the maximum transmission speed of the interface board to be accommodated, or the interface board has a transmission speed exceeding the bus capacity of each port (Port 0 to 15). On the other hand, the physical capacity of the rear wiring board (BWB) is devised to connect to a plurality of ports to increase the bus capacity of the rear wiring board (BWB).

  In the configuration example of FIG. 8, the bus capacity of the main data bus of each port (Port 0 to 15) to which various interface boards 8-1 to 8-5 are connected is 200 Mbps using four buses having a bus capacity of 50 Mbps. The bus capacity is one or more, depending on the transmission speed of the interface boards 8-1 to 8-5 that accommodate the ports (Ports 0 to 15).

  That is, one port (for each of the low-speed interface boards (64 Kbps to 6.3 Mbps) 8-1, 8-2 and the high-speed interface boards (150 Mbps to 200 Mbps) 8-3 having a transmission speed of 200 Mbps or less. Port 0, Port 1 and Port 2) are connected and accommodated only. This is because each port has a bus capacity of 200 Mbps, and an interface board having a transmission speed of 200 Mbps or less can be accommodated in one port.

  The high-speed interface board (600 Mbps) 8-4 exceeding the transmission capacity of 200 Mbps is connected to and accommodated by a plurality (four in this example) of ports (Port 8, Port 10, Port 12, Port 14), and the high-speed interface board Similarly, (600 Mbps) 8-5 is accommodated by connecting to a plurality (four in this example) of ports (Port 9, Port 11, Port 13, and Port 15).

  Actually, the connection between each port (Port 0 to 15) and each interface board 8-1 to 8-5 is different in bus capacity in which a predetermined number of ports (Port 0 to 15) are wired in advance. Multiple types of mounting slots are prepared on the rear wiring board (BWB), and each interface board 8-1 to 8-5 is connected to a mounting slot having a suitable bus capacity. It was.

As a prior art document related to the present invention, in Patent Document 1 below, in a multiplex transmission apparatus such as an SDH transmission method, a plurality of actually mounted slots are mounted in slots for mounting communication interface boards provided in each shelf. Communication interface board mounting abnormality detection method that determines whether the total communication speed determined by the combination of communication interface boards is acceptable in the device configuration, and if not, outputs a mounting abnormality signal Is described.
JP-A-11-234236

  In the conventional multiplex transmission device, the bus capacity of each port to which the interface board is connected is fixed, so to install a high-speed data system interface board, the high-speed data system interface board must be connected to multiple ports. Because it is necessary to physically wire the buses of multiple ports with the rear wiring board (BWB), etc., it cannot be flexibly handled, and for high-speed data system (200 Mbps or higher) interface boards However, it was necessary to place restrictions on the mounting, such as disabling other than the dedicated mounting slot.

  If the bus capacity of all ports in the device is increased in accordance with the maximum transmission capacity of the high-speed data interface board, most of the transmission bandwidth of the ports connected to the low-speed data interface board is unused. As a result, the transmission efficiency is very poor and the cost is increased.

  The present invention can flexibly cope with the mounting of the high-speed data system interface board without providing a dedicated mounting slot, and further reduces the transmission efficiency of the low-speed data system interface board without causing a decrease in transmission efficiency. An object of the present invention is to provide a multiplex transmission apparatus that can easily cope with a high-speed data system interface board and a method for setting or changing the bus capacity thereof.

  The multiplex transmission apparatus of the present invention is connected to a main port to which a plurality of types of interface boards having different transmission speeds are connected, to a subport of a certain transmission capacity connected to the main port, to the subports, and from each interface board A space switch that outputs main data input through the main port and the sub port to an arbitrary interface board through the sub port and the main port, and a connection configuration between the main port and the sub port is set by programming given from the outside Alternatively, an LSI that can be changed is used, and the number of subports connected to each main port is set or changed according to the transmission speed of the interface panel mounted on each main port, The main port is connected to each of the connected sub-ports. In multiplicity corresponding to the number of bets, characterized in that a function of the speed conversion and format conversion of the main data.

  Also, the method for setting or changing the bus capacity of the multiplex transmission apparatus of the present invention comprises connecting a subport having a fixed transmission capacity to a main port to which a plurality of types of interface boards having different transmission speeds are connected, The interface board is connected in a multiplex transmission apparatus that outputs main data input from each interface board through the main port and sub port to an arbitrary interface board through the sub port and main port by the space switch. Sub-port connected to each main port using an LSI that can set or change the connection configuration of the main port and the sub-port by external programming. Implemented on each main port Setting or changing each according to the transmission speed of the interface board, and each main port performing speed conversion and format conversion of the main data at a multiplicity corresponding to the number of the connected sub-ports, respectively. It is characterized by including.

  According to the present invention, the bus capacity of the main port to which the interface board is connected can be changed by connecting an arbitrary number of subports to the main port, so that the physical capacity of the rear wiring board (BWB) or the like can be changed. The bus capacity of the main port to which the interface board is connected can be changed according to the transmission speed of the interface board to be mounted without changing the number of wires, as in the low-speed data system interface board and the high-speed data system interface board It is possible to accommodate multiple types of interface boards with different transmission speeds at any mounting position, increase the number of sub-ports connected to the main port, and use multiple main ports to install the interface board. By connecting, a higher speed interface (eg 1.2 Gbps / 2.4 Gbps) Also it can accommodate, it is possible to flexibly cope with accommodation of various interface board, it is not caused a decrease in transmission efficiency of low-speed data-interface board.

  FIG. 1 shows a configuration example of a multiplex transmission apparatus according to the present invention. As shown in the figure, sub-ports (Sub-Ports 1, 2,...) Are provided between a main port (Main-Port 0 to 9) to which various interface boards are connected and a space switch (SSW).

  The main port (Main-Port), sub-port (Sub-Port), and space switch, such as an FPGA (Field Programmable Gate Array), can be set or changed by external programming. Integration).

  Each main port (Main-Port) can be connected to one or more arbitrary number of sub-ports (Sub-Port) by external programming. Alternatively, a predetermined number of sub-ports (Sub-Ports) may be connected in advance to each main port (Main-Port), and only the sub-ports (Sub-Port) to be used may be validated by external programming. it can.

  Here, it is assumed that each subport (Sub-Port) has a main data bus using four data buses having a transmission capacity of 50 Mbps, and has a transmission capacity of 200 Mbps for the four main data buses. The main port (Main-Port) multiplexes data of the main data bus of each connected sub-port (Sub-Port), and transmits / receives data to / from the four main data buses connected to the interface board.

  That is, the transmission capacity of the four main data buses on the interface board side in the main port (Main-Port) is doubled by the number of connected subports (Sub-Port). Therefore, the transmission capacity (processing speed) of the main data bus of the main port (Main-Port) can be changed by increasing / decreasing the number of sub-ports (Sub-Port) connected to the main port (Main-Port).

  Furthermore, by connecting a high-speed data system interface board using a plurality of the main ports (Main-Ports) described above, the capacity of the bus to which the interface board is connected can be reduced by the number of physical wires of the main data bus and the processing speed. It can be configured to be variable within the range of the capacity expressed as a product.

The relationship between the data capacity of the interface board to be accommodated, the processing speed of the main port (Main-Port), the number of bus wires, etc. is shown in a list in FIG. As shown in the table,
(1) When the transmission speed (data capacity) of the interface board to be accommodated is 64 k to 200 Mbps (see 1-1 and 1-2 in FIG. 1), one sub-port (Sub-Port) for the main port (Main-Port) (Hereinafter also referred to as an internal port), and a bus capacity of 200 Mbps is established by four main data buses with a processing speed of 50 MHz. Since the connection between the sub-port (Sub-Port) and the space switch (SSW) is connected by eight buses, the multiplication number is doubled with respect to the processing speed of the space switch (SSW).

(2) When the data volume of the interface board to be accommodated is 600 Mbps (see 1-3 in FIG. 1), the multi-plicity is obtained by connecting three sub-ports (Sub-Port) (internal ports) to the main port (Main-Port). 3 and a bus capacity of 600 Mbps with four main data buses with a processing speed of 150 MHz. The multiplication factor is 6 times the processing speed of the space switch (SSW).

(3) When the data volume of the interface board to be accommodated is 1.2 Gbps (see 1-4 in FIG. 1), six sub-ports (Sub-Port) (internal ports) are connected to the main port (Main-Port). The multiplicity is 6, and the bus capacity is 1.2 Gbps by four main data buses with a processing speed of 300 MHz. The multiplication factor is 12 times the processing speed of the space switch (SSW).

(4) When the data amount of the interface board to be accommodated is 2.4 Gbps (see 1-5 in FIG. 1), two main ports (Main-Port) are used, and six are provided for each main port (Main-Port). Sub-ports (Sub-Ports) (internal ports) are connected, the multiplicity is 6, and the bus capacity is 2.4 Gbps by 8 main data buses with a processing speed of 300 MHz.

  In the above embodiment (4), the limit of the processing speed of the rear wiring board (BWB) bus is 300 MHz, and the main data bus is used. However, the rear wiring board (BWB) bus is used. If the limit of the processing speed is 600 MHz which is twice that of the processing speed, it can be constituted by four main data buses.

  Hereinafter, speed conversion and format conversion for each type of interface board in the main port (Main-Port) will be described with reference to FIGS. FIG. 3 shows the case of the interface board of the low-speed data system of 64 k to 200 Mbps and the high-speed data system up to 200 Mbps (see 1-1 and 1-2 in FIG. 1).

  As shown in the figure, the main port (Main-Port 0) has main data transmitted to and received from the interface board via the four external data buses data_1 to data_4 at the same speed and in the same format, that is, speed conversion and format. Without conversion, the data is transmitted to and received from the internal buses p0_data_1_s1 to p0_data_4_s1 connected to the subport (Sub-Port1).

  FIG. 4 shows the case of the interface board of the above-mentioned (2) 600 Mbps high-speed data system (see 1-3 in FIG. 1). The main port (Main-Port2) reduces the speed of data transmitted to and received from the interface board via the four external data buses data_1 to data_4 to 1/3, and the main data of the time slot TS1 of the external data buses data_1 to data_4. Transfer to the internal bus p2_data_1_s1 to p2_data_4_s1 of the subport (Sub-Port1), and transfer the main data of the time slot TS2 of the external data bus data_1 to data_4 to the internal bus p2_data_1_s2 to p2_data2 of the subport (Sub-Port2) The main data of the time slot TS3 of ~ data_4 is transferred to the internal bus p2_data_1_s3 to p2_data_4_s of the subport (Sub-Port3) Instead to send and receive put on. Similarly, the main data after the time slot TS4 is transferred to and transmitted from the internal buses of the three subports (Sub-Ports 1 to 3).

  FIG. 5 shows the case of the interface board of the above-mentioned (3) 1.2 Gbps high-speed data system (see 1-4 in FIG. 1). The main port (Main-Port 7) reduces the speed of data transmitted to and received from the interface board via the four external data buses data_1 to data_4 to 1/6, and the main data of the time slot TS1 of the external data buses data_1 to data_4. Transfer to the internal bus p7_data_1_s1 to p7_data_4_s1 of the subport (Sub-Port1), and transfer the main data of the time slot TS2 of the external data bus data_1 to data_4 to the internal bus p7_data_1_s2 to p7_s2 and the same to the internal bus p7_data_1_s2 to p7_s2 of the subport (Sub-Port2) The main data of the time slot TS6 of the external data bus data_1 to data_4 is transferred to the internal bus p7_data_1_s6 to p7_da of the subport (Sub-Port6). Instead to send and receive put on a_4_s6. Similarly, the main data after the time slot TS7 is transferred to and transmitted from the internal buses of the three subports (Sub-Ports 1 to 3).

  FIG. 6 shows the case of the 2.4 Gbps high-speed data interface board (see 1-5 in FIG. 1). The main port (Main-Port 9) reduces the speed of the main data transmitted to and received from the interface board via the four external data buses data_1 to data_4 to 1/6, and the time slot TS1 of the first external data buses data_1a to data_4a. Main data is transferred to the internal bus p9_data_1_s1 to p9_data_4_s1 of the subport (Sub-Port1), and the main data of the time slot TS2 of the second external data bus data_1b to data_4b is transferred to the internal bus p9_data_1_2 In the same manner, the time slots TS3 to TS11 are sequentially changed in the same manner, and the time slots TS12 of the second external data buses data_1b to data_4b are sequentially transferred. Sort put the data to the internal bus p9_data_1_s12~p9_data_4_s12 of the sub-port (Sub-Port12). The subsequent time slot TS13 is also sent and received after the format conversion for the same transfer.

  FIG. 7 shows a configuration of an embodiment of a multiplex transmission apparatus according to the present invention. In the figure, the space switch board 7-1 includes a main port (Main-Port 1 to 9) to which various interface boards are connected, and a sub-port (Sub-Port1, Sub-Port 1, connected to the main port (Main-Port 1 to 9)). 2) and a space switch (SSW), and a duplex configuration consisting of a 0 system and a 1 system.

  The space switch board 7-1 has a transmission speed such as a high-speed interface board 7-2 and a low-speed interface board 7-3 via an internal bus such as a rear wiring board (BWB) bus. Different types of interface boards are connected. When the number of main ports in the space switch board 7-1 is 9, up to nine high-speed interface boards 7-2 and low-speed interface boards 7-3 can be connected.

  A clock signal is supplied from the clock board 7-4 to the space switch board 7-1, the high-speed interface board 7-2, and the low-speed interface board 7-3, and format conversion and main data are synchronized with the clock signal. Sending and receiving are performed. The space switch board 7-1, the high-speed interface board 7-2, the low-speed interface board 7-3, and the clock board 7-4 are monitored and controlled by the control / monitoring board 7-5 via the monitoring / control bus. .

  The control / monitoring board 7-5 receives various setting / control information from the operation device 7-6 such as an external personal computer, and performs setting / control of each internal device according to the setting / control information. The setting or changing of the sub-port connection configuration or the sub-port validation / invalidation in the space switch board 7-1 can be arbitrarily performed from the operation device 7-6. Also, monitoring information such as the operating state in the apparatus is sent to the operation apparatus 7-6.

It is a figure which shows the structural example of the multiplex transmission apparatus by this invention. It is a figure which shows the relationship between the data capacity of an interface board, the processing speed of a main port, the number of bus wirings, etc. It is a figure which shows the speed conversion and format conversion in the case of a low-speed data system and an interface board to 200 Mbps. It is a figure which shows the speed conversion and format conversion in the case of a 600Mbps interface board. It is a figure which shows the speed conversion and format conversion in the case of a 1.2Gbps interface board. It is a figure which shows the speed conversion and format conversion in the case of a 2.4Gbps interface board. It is a figure which shows the structure of the Example of the multiplex transmission apparatus by this invention. It is a figure which shows the structural example of the conventional multiplex transmission apparatus.

Explanation of symbols

1-1 Low-speed interface board (64 Kbps to 6.3 Mbps)
1-2 High-speed interface board (150 Mbps to 200 Mbps)
1-3 High-speed interface board (600Mbps)
1-4 High-speed interface board (1.2 Gbps)
1-5 High-speed interface board (2.4 Gbps)
Main-Port 0 to 9 Main port Sub-Port 1, 2,... Sub port SSW Space switch

Claims (2)

A main port to which multiple types of interface boards with different transmission speeds are connected;
A subport of a certain transmission capacity connected to the main port;
A spatial switch connected to the subport and outputting main data input from each interface board through the main port and the subport to an arbitrary interface board through the subport and the main port;
Using an LSI that can set or change the connection configuration between the main port and the sub-port by programming given from the outside, the number of sub-ports connected to each main port is the number of interface boards mounted on each main port. It has a configuration that is set or changed according to the transmission speed,
Each of the main ports is provided with a function of performing speed conversion and format conversion of main data at a multiplicity according to the number of the sub-ports connected thereto. A subport having a certain transmission capacity is connected to a main port to which a plurality of types of interface boards having different transmission speeds are connected, the subport and a space switch are connected, and a main input from each interface board through the main port and the subport. A method of setting or changing a bus capacity of a main port to which the interface board is connected in a multiplex transmission apparatus that outputs data to an arbitrary interface board through the subport and the main port by the space switch,
Using an LSI that can set or change the connection configuration between the main port and the sub-port by external programming, the number of sub-ports connected to each main port is transmitted to the interface board mounted on each main port. A step of setting or changing each according to the speed;
Each main port includes a step of performing speed conversion and format conversion of main data at a multiplicity corresponding to the number of subports connected to each other, and setting or changing the bus capacity of the multiplex transmission apparatus, Method.

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