JP2008176399A - Integrated circuit design support program, integrated circuit design support system, and integrated circuit design support method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a system enabling a user to personally determine whether or not a given master is compatible to his/her desired condition, regarding a gate array. <P>SOLUTION: A design support program includes: a means for acquiring a used register total bit number and circuit type information; a gate required amount estimation computation means for computing a gate required amount estimation based on the received used register total bit number and information on the circuit type; a means for acquiring physical specification information including the kind of the master and a wiring layer number of an integrated circuit; a master information storage means for storing master information including gate capacity information corresponding to the kind of the master and use efficiency information corresponding to the kind of the master and the wiring layer number; and a mountable gate number computation means for obtaining gate capacity corresponding to the kind of the master, and use efficiency corresponding to the kind of the master and the wiring layer number, on the basis of the physical specification information related to the kind of the master and the wiring layer number and the master information, and computing a mountable gate number based the obtained gate capacity and use efficiency. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an integrated circuit design support program, an integrated circuit design support system, and an integrated circuit design support method.

In LSI design using a gate array, we prepare a number of basic gate array products called masters that have different gate capacities, etc., and manufacture slice masks consisting of different metal layers for each user. Semi-custom products are being made.
Japanese Patent Laid-Open No. 2002-7496

  In producing such a slice, it is important to select an optimum master for the conditions desired by the user.

  In the past, it was common for technical data to be used as a guideline for examination to be presented and for the user to set conditions based on this, and for the engineer to manually select the gate array master considering the layout and other factors. It was.

  A gate array is a logic LSI. Basically, a master that is likely to be applicable can be estimated from the four conditions of the number of logic gates, the gate usage efficiency, the power supply voltage, and the number of bins, and can be given as candidates.

  However, in recent years, RTL design has become common, and when the user performs RTL design, there are more cases where the number of logic gates is unknown, and the above estimation method has become difficult. In addition, the number of cases in which memory is integrated into a logic LSI is increased, and in such cases, it is necessary to consider layout aspects such as memory block layout and wiring, and this is not possible for general users other than semiconductor designers. It is getting more and more difficult.

  The present invention has been made in view of the technical problems as described above. The purpose of the present invention is to provide a given master for a user-desired condition for an integrated circuit including at least a part of a gate array. It is to provide an integrated circuit design support program, an integrated circuit design support system, and an integrated circuit design support method that allow a user to determine whether it is conforming or not.

(1) The present invention
An integrated circuit design support program including at least a part of a gate array,
Logical specification information acquisition means for acquiring logical specification information including the total number of used registers and circuit type;
An estimated gate requirement calculation means for calculating an estimated gate requirement based on the received total number of used registers and information on the circuit type;
And making the computer function.

  The integrated circuit including at least a part of the gate array may be a gate array or an integrated circuit including a gate array such as an embedded array. In addition to the gate array, an integrated circuit including a standard cell, a hard macro (CPU or the like) for a specific application, a RAM, or the like may be used.

  The circuit type may be, for example, either a control circuit or an arithmetic circuit, and there may be a case where the arithmetic circuit and the control circuit are mixed. In this case, a plurality of circuits are used depending on the proportion of each circuit. The type may be set so that it can be selected.

  The estimated gate requirement calculation means sets or selects a gate number conversion constant or function based on the received information regarding the circuit type, and sets or selects the gate number conversion constant or function and the total number of used registers based on the selected or selected gate number. An estimated gate requirement may be calculated.

  Since the correlation and correspondence between the total number of bits in the register used and the total number of gates in the logic vary depending on the circuit type, the gate number conversion constant or function is a heuristic value for the statistical usage efficiency data of past cases. May be set in consideration of the above.

  In this way, even if the user is only the source of the hardware description language and the number of gates is unknown, the estimated gate requirements can be calculated with high reliability by specifying the total number of register bits and the circuit type. be able to.

(2) An integrated circuit design support program according to the present invention includes:
Physical specification information acquisition means for acquiring physical specification information including the type of integrated circuit master including at least a part of the gate array and the number of wiring layers;
Master information storage means for storing master information including gate capacity information corresponding to the master type, usage efficiency information corresponding to the master type and the number of wiring layers,
Based on the physical specification information on the master type and the number of wiring layers and the master information, the gate capacity corresponding to the master type, the usage efficiency corresponding to the master type and the number of wiring layers are obtained, and the obtained gate capacity and usage efficiency. The number of mountable gate number calculating means for calculating the number of mountable gates based on
And making the computer function.

The number of gates that can be installed is
The gate capacity corresponding to the master type is obtained based on the input master type and the stored gate capacity information, and input based on the input master type and the number of wiring layers and the stored usage efficiency information. The use efficiency corresponding to the master type and the number of wiring layers may be obtained, and the number of mountable gates may be calculated based on the obtained gate capacity and use efficiency.

  The usage efficiency may be set as the estimated usage efficiency by using the number of wiring layers that can be used on the physical wiring as a parameter, and adding the heuristic value as a margin to the statistical usage efficiency data of past cases.

  According to the present invention, an appropriate number of mountable gates can be obtained according to the number of wiring layers used by the user.

(3) An integrated circuit design support program according to the present invention includes:
Internal memory information acquisition means for acquiring internal memory information regarding the capacity, quantity, and location of the internal memory;
Built-in memory arrangement simulation means for performing a built-in memory arrangement simulation based on the master type and built-in memory information;
And making the computer function.

  The capacity of the built-in memory can be specified by the bit width and depth of the built-in memory, for example. The built-in memory is, for example, a RAM.

  The layout simulation means may perform area estimation or layout simulation in consideration of the layout, such as physical layout of the memory and width of a necessary wiring area, based on the built-in memory information regarding the capacity, quantity, and layout position of the built-in memory. .

(4) An integrated circuit design support program according to the present invention includes:
The mountable gate number calculating means includes
Based on the input master type and built-in memory information, the built-in memory obtains the gate capacity excluding the part that cannot be used for the user's logic circuit, and the gate capacity can be corrected by having the built-in memory. The number of gates is obtained.

  The correction by having a built-in memory may be, for example, a correction that reduces a predetermined ratio or a predetermined amount with respect to the gate capacitance. For example, in the case where there is a built-in memory, the usage efficiency of the gate capacitance excluding the portion that cannot be used for the user's logic circuit may be subtracted by 10%.

(5) An integrated circuit design support program according to the present invention includes:
Based on the estimated gate requirement and the number of mountable gates, conformity determination means for determining whether or not the acquired logical specification can be mounted for the acquired master type,
And making the computer function.

  For example, when the estimated gate requirement falls within the number of mountable gates, it may be determined that the gate can be installed, or when the estimated gate requirement falls within a predetermined ratio of the number of mountable gates. You may make it judge that it can mount.

(6) An integrated circuit design support program according to the present invention includes:
A predicted layout image display control means for generating a predicted layout image based on the layout simulation result of the built-in memory and outputting it to the display unit;
And making the computer function.

  According to the present invention, since the predicted layout image of the built-in memory is displayed, the user can visually confirm the layout simulation result.

(7) An integrated circuit design support program according to the present invention includes:
The logical specification acquisition means includes
Input screen image display control means for displaying an input screen image for accepting user input for the logical specifications including the total number of used registers and circuit type, and the logical specifications including the total number of used registers and circuit type from the input screen Logical specification information receiving means for receiving information,
The physical specification acquisition means
Input screen image display control means for displaying an input screen image for accepting user input for physical specification information including the type of master and the number of wiring layers, and the type of master from the input screen and the physical including the number of wiring layers Physical specification receiving means for receiving specification information,
Built-in memory information acquisition means
Input screen image display control means for displaying an input screen image for accepting user input regarding the internal memory information regarding the internal memory information regarding the internal memory bit width, depth, number, and bit width and depth of the internal memory from the input screen And built-in memory information receiving means for receiving built-in memory information related to the number and arrangement position.

  According to the present invention, a user can input logical specifications, physical usage, and built-in memory information from an input screen image.

(8) An integrated circuit design support program according to the present invention includes:
Logical specification acquisition means
It includes hardware description language analysis means for receiving input of source code information of a hardware description language relating to the gate array and analyzing the received source code information to obtain the total number of used registers.

  A hardware description language (HDL (Hardware Description Language)) is a kind of computer language for designing digital circuits, particularly integrated circuits, and may be, for example, an RTL (Register Transfer Level) language. The RTL is a level in which a circuit is expressed by a flip-flop + combination logic circuit, and a circuit design by the current HDL mainly uses this level description.

  For example, in the case of the Verilog language, which is a typical RTL language, the hardware description language analysis means may analyze the register declaration portion and obtain the total number of used register bits from the number of bits declared in Registr.

  According to the present invention, even when the user has only the RTL source and the required number of gates is unknown, the system analyzes the RTL source and automatically obtains the total number of bits used in the register. Can be reduced.

(9) The present invention
An integrated circuit design support system including at least a part of a gate array,
Logical specification information acquisition means for acquiring logical specification information including the total number of used registers and circuit type;
Physical specification information acquisition means for acquiring physical specification information including the type of integrated circuit master including at least a part of the gate array and the number of wiring layers;
An estimated gate requirement calculation means for calculating an estimated gate requirement based on the received total number of used registers and information on the circuit type;
Master information storage means for storing master information including gate capacity information corresponding to the master type, usage efficiency information corresponding to the master type and the number of wiring layers,
Based on the physical specification information on the master type and the number of wiring layers and the master information, the gate capacity corresponding to the master type, the usage efficiency corresponding to the master type and the number of wiring layers are obtained, and the obtained gate capacity and usage efficiency. The number of mountable gate number calculating means for calculating the number of mountable gates based on
Based on the estimated gate requirement and the number of mountable gates, conformity determination means for determining whether or not the acquired logical specification can be mounted for the acquired master type,
It is characterized by including.

(10) The present invention
An integrated circuit design method comprising at least a part of a gate array,
Logical specification information acquisition step for acquiring logical specification information including the total number of used registers and circuit type;
A physical specification information acquisition step for acquiring physical specification information including the type of integrated circuit master including at least a part of the gate array and the number of wiring layers;
An estimated gate requirement calculation step for calculating an estimated gate requirement based on the received total number of used registers and information on the circuit type;
Master information storage step for storing master information including gate capacity information corresponding to the master type, usage efficiency information corresponding to the master type and the number of wiring layers,
Based on the physical specification information on the master type and the number of wiring layers and the master information, the gate capacity corresponding to the master type, the usage efficiency corresponding to the master type and the number of wiring layers are obtained, and the obtained gate capacity and usage efficiency. The number of mountable gates calculation step for calculating the number of mountable gates based on
Based on the estimated gate requirement and the number of mountable gates, a conformity determination step for determining whether or not the acquired logical specification can be mounted for the acquired master type,
It is characterized by including.

1. Configuration First, the configuration of an integrated circuit device design support system according to the present embodiment will be described with reference to FIG. The design support system for an integrated circuit device according to this embodiment may have a configuration in which some of the components (each unit) are omitted.

  The operation unit 160 is for inputting user operations and the like as data, and the function can be realized by hardware such as a keyboard and a mouse. The operation unit receives logical specification information receiving means for receiving logical specification information including the total number of used registers and circuit type from the input screen, and physical specification receiving means for receiving physical specification information including the type of master and the number of wiring layers from the input screen. It functions as a built-in memory information receiving means for receiving built-in memory information related to the bit width, depth, number, and arrangement position of the built-in memory from the input screen.

  The storage unit 170 serves as a work area for the processing unit 100, the communication unit 196, and the like, and the function can be realized by hardware such as a RAM.

  The storage unit 170 includes a master information storage unit 172.

  The master information storage unit 172 functions as a master information storage unit that stores master information including gate capacity information corresponding to the master type and usage efficiency information corresponding to the master type and the number of wiring layers.

  The information storage medium 180 (a computer-readable medium) stores programs, data, and the like, and functions as an optical disk (CD, DVD, etc.), a magneto-optical disk (MO), a magnetic disk, a hard disk, and a magnetic disk. It can be realized by hardware such as a tape or a memory (ROM).

  The information storage medium 280 stores auxiliary data (additional data) for a program that causes a computer to function as each unit of the present embodiment.

  The processing unit 100 performs various processes of the present embodiment based on a program (data) stored in the information storage medium 180, data read from the information storage medium 180, and the like. That is, the information storage medium 180 stores a program for causing a computer to function as each unit of the present embodiment (a program for causing a computer to execute processing of each unit).

  The display unit 190 outputs an image generated according to the present embodiment, and functions thereof are a CRT display, an LCD (liquid crystal display), an OELD (organic EL display), a PDP (plasma display panel), and a touch panel display. It can be realized by hardware such as.

  The sound output unit 192 outputs the sound generated according to the present embodiment, and its function can be realized by hardware such as a speaker or headphones.

  The communication unit 196 performs various controls for communicating with the outside (for example, a server device or another terminal), and functions thereof include hardware such as various processors or communication ASICs, It can be realized by a program.

  Note that a program (data) for causing a computer to function as each unit of the present embodiment is transferred from the information storage medium included in the host device (server device) to the information storage medium 180 (or storage unit 170) via the network and communication unit 196. You may make it deliver. Use of the information storage medium of such a host device (server device or the like) can also be included in the scope of the present invention.

  The processing unit 100 (processor) performs various processes based on operation data and programs from the operation unit 160. The processing unit 100 performs various processes using the storage unit 170 as a work area. The functions of the processing unit 100 can be realized by hardware such as various processors (CPU, DSP, etc.), ASIC (gate array, etc.), application programs, and OS (for example, general-purpose OS).

  The processing unit 100 includes an estimated gate requirement calculation unit 110, a mountable gate number calculation unit 112, a built-in memory arrangement simulation processing unit 114, a hardware description language analysis processing unit 116, a suitability determination processing unit 118, and a display control unit 120. Including. The display control unit 120 includes an expected layout image display control unit 122 and an input screen display control unit 124.

  The estimated gate requirement calculation unit 110 calculates the estimated gate requirement based on the received total number of used registers and information on the circuit type.

  The mountable gate number calculation unit 112 obtains the gate capacity corresponding to the master type, the master type, and the usage efficiency corresponding to the number of wiring layers based on the physical specification information regarding the master type and the number of wiring layers and the master information. The number of gates that can be mounted is calculated based on the obtained gate capacity and usage efficiency.

  The built-in memory arrangement simulation processing unit 114 performs a built-in memory arrangement simulation based on the master type and the built-in memory information.

  The mountable gate number calculation unit 112 obtains a gate capacity excluding a part that cannot be used for a user's logic circuit by the built-in memory based on the input master type and built-in memory information. The number of gates that can be mounted may be obtained by performing a correction based on the above.

  The conformity determination processing unit 118 determines whether or not the acquired logical specification can be mounted on the acquired master type based on the estimated gate requirement and the number of mountable gates.

  The predicted placement image display control unit 122 performs control to generate a predicted placement image based on the placement simulation result of the built-in memory and output it to the display unit.

  The hardware description language analysis processing unit 116 receives input of source code information of the hardware description language related to the gate array, analyzes the received source code information, and performs processing for obtaining the total number of used registers.

  The input screen display control unit 124 includes an input screen image display control means for displaying an input screen image for accepting a user input for a logical specification including the total number of used registers and a circuit type, the type of the master, and wiring Input screen image display control means for displaying an input screen image for accepting user input for physical specification information including the number of layers, and user input for built-in memory information regarding the bit width, depth, number, and arrangement position of the built-in memory It functions as an input screen image display control means for displaying an input screen image for accepting.

  Note that a program (data) for causing a computer to function as each unit of the present embodiment is distributed from the information storage medium of the host device (server) to the information storage medium 180 (storage unit 170) via the network and communication unit 196. May be. Use of the information storage medium of such a host device (server) can also be included in the scope of the present invention.

  FIGS. 2A and 2B and FIGS. 3A and 3B are diagrams for explaining the master information of the present embodiment.

  In the master size table 210 of FIG. 2A, the gate capacity 214 corresponding to the master type 212 is stored. The master type 212 only needs to represent the master product type. The gate capacity 214 is the total number of physical gates mounted on the master type 212.

  The usage efficiency table 220 in FIG. 2B stores usage efficiency corresponding to the master type 222 and the number of wiring layers 224 to 228. For example, when the master type is “M0001”, the specification efficiency is x1 when the number of wiring layers is 1, the specification efficiency is y1 when the number of wiring layers is 2, and the specification efficiency is 3 when the number of wiring layers is 3. z1.

  The master information may be stored as a data table that can be read from the program as shown in FIGS. 2A and 2B, or the program (installation of the processing unit) as shown in FIGS. This is a program for realizing the possible gate number calculation unit, and may be in a form embedded in the source code of Java (registered trademark), for example. FIG. 3A shows an example in which the contents of the master size table 210 are embedded in the source code of Java (registered trademark), and FIG. 3B shows the specification efficiency table 220 in the source code of Java (registered trademark). The example which embeds the contents of is shown.

2. Interface In the present embodiment, integrated circuit design support is implemented as an execution program in Java (registered trademark) applet format in which necessary specification data is taken into a program for a master subject to suitability determination (however, actual data cannot be seen by a user) The program is installed on a Web server. The integrated circuit design support program is downloaded to a user terminal (see FIG. 1) in response to a user request and can be executed on the Internet browser screen of the user terminal.

  FIG. 4 is a diagram for explaining an input screen for accepting user input according to the present embodiment. When the user makes an input screen browsing request, an input screen as shown in FIG. 4 is displayed on the display unit of the user terminal.

  A physical specification information receiving unit 310 includes a gate array series designating unit 312, a gate array master designating unit 314, and a gate array wiring total number designating unit 316. Both are pull-down formats, and data is selected and input. The gate array series designating unit 312 and the gate array master designating unit 314 are configured to designate a desired gate array master product, and the system can acquire master type information from this input information. Further, the gate array wiring total number designating unit 316 is configured to designate a desired number of wiring layers, and the system can acquire the number of wiring layers by this input information.

  Reference numeral 320 denotes a logical specification information receiving unit, which includes a register total bit number specifying unit 322, a gate total number specifying unit 324, a circuit type (control system or arithmetic system) specifying unit 316, and a memory BIST built-in presence / absence specifying unit 328. The register total bit number designating unit 322 and the gate total number designating unit 324 are portions for inputting the required number of gates of the user logic, and the user selects either the register total bit number designating unit 322 or the gate total number designating unit 324. Can be entered. For example, when the user knows the total number of gates of the user logic, the gate total number designation unit 324 is selected and the grasped value is input. If the user has only RTL (an example of hardware description language) source and the number of gates required is unknown, the user selects the register total bit number designating section 322 and the number of register bits used in the RTL source. (For example, in the case of the Verilog language, which is a typical RTL language, the total number of bits of the register may be obtained and input from the register.) The system can acquire information related to the number of logic gates of the user logic by acquiring input information from either the register total bit number specifying unit 322 or the gate total number specifying unit 324.

  The circuit type designation unit 326 designates whether the circuit type is a control circuit or an arithmetic circuit. The circuit type is a circuit format to be formed by the RTL source of the user logic. Here, the circuit type is selected from two types of control circuit and arithmetic circuit. When an arithmetic circuit such as an adder, subtractor, multiplier, or divider is included, the arithmetic circuit is specified by the circuit type. When the control circuit does not include the arithmetic circuit, the control circuit is specified by the circuit type. specify. However, since the arithmetic circuit and the control circuit may be mixed, in that case, either one may be selected according to the proportion of each circuit. The system can acquire information related to the circuit type of the user logic by acquiring input information of the circuit type designation unit 326.

  Reference numeral 330 denotes a RAM information designation unit (an example of a built-in memory information reception unit), which includes a bit width designation unit 332, a bit depth designation unit 334, a number designation unit 336, and an arrangement position (arrangement row) designation unit 338 for the built-in RAM. . The internal RAM bit width specifying unit 332 specifies the internal RAM bit width (vertical), the bit depth specifying unit 334 specifies the internal RAM bit depth (horizontal), and the number specifying unit 336 specifies first. Specify the number of built-in RAMs with the specified bit width and bit depth, and specify the placement row where the specified number of built-in RAMs with the bit width and bit depth specified earlier in the placement position (placement row) designation unit 338 is set. The system can acquire the built-in memory information from this input information.

  Reference numeral 340 denotes an estimation result image display unit which displays an arrangement prediction image based on whether or not the input logical specification can be mounted for the input master type and the internal memory arrangement simulation result. This will be specifically described with reference to FIGS.

  FIG. 5 is a diagram for explaining a result display screen (a case where user logic is adapted to a selected master) according to the present embodiment. From the input screen, the user can select a gate array series specifying unit 312, a gate array master specifying unit 314, a gate array wiring total number specifying unit 316, a register total bit number specifying unit 322 or a gate total number specifying unit 324, a circuit type (control system or arithmetic system). ) Designation unit 316, memory BIST built-in presence / absence designation unit 328, built-in RAM bit width designation unit 332, bit depth designation unit 334, number designation unit 336, and arrangement position (arrangement row) designation unit 338 are designated to determine suitability. Is executed, the determination result is displayed on the determination result display unit 370, and the determination result display image is displayed on the estimation result image display unit 340.

  The determination result display unit 370 displays the determination result (OK or NG) for each of the logic part (352) and the macro part (RAM blocks 354-1, 354-2, 354-3).

  The determination result display image includes a shape of a logic unit 352 and individual RAM blocks 354-1, 354-2, and 354-3 as shown in 350, and is a temporary layout layout diagram on the master layout of the gate array. To display a graphic. At this time, the applicable color (blue color) is displayed in the applicable case (in the case of OK), and the second color (red color) is displayed in the non-applicable case (in the case of NG). Was filled.

  The determination result of the logic unit shown in 370 is OK, and the logic unit 352 shown in the estimation result image display unit 340 is displayed in the first color (blue system color). This means that the user logic (determined by the content specified by the logical specification information receiving unit 320) can be mounted on the specified master (determined by the content specified by the physical specification information receiving unit 310). . For example, when the estimated gate requirement calculated based on the content received by the logical specification information receiving unit 320 falls within the number of mountable gates calculated based on the content received by the physical specification information receiving unit 310 and the RAM information specifying unit 330 It may be determined that the device can be mounted on.

  In addition, the determination result of the macro portion (RAM block) indicated by 370 is OK, and the RAM blocks 354-1, 354-2, and 354-3 indicated by the estimation result image display unit 340 are the first color (blue system color). Is displayed. This means that the built-in RAM (determined by the content specified by the internal RAM information receiving unit 330) can be mounted on the specified master (determined by the content specified by the physical specification information receiving unit 310). . For example, based on the content received by the internal RAM information receiving unit 320, the internal RAM placement simulation is performed, and when the internal RAM fits into the type of master specified by the physical information specifying unit 310 as a result of the placement simulation (the master and the internal RAM Based on the area and shape, a placement simulation may be performed to determine that the device can be mounted.

  For example, as shown in 360, the logic total (estimated gate required amount) 364 calculated based on the content received by the logical specification information receiving unit 320, and the content received by the physical specification information receiving unit 310 and the RAM information specifying unit 330 You may make it display the gate number (number of gates which can be mounted) 362 of the usable area calculated based on. As shown in the figure, the calculation contents may also be displayed.

  FIG. 6 is a diagram for explaining a result display screen (a case where the user logic does not match the selected master) according to the present embodiment.

  The determination result of the logic unit shown in 370 is NG, and the logic unit 352 shown in the estimation result image display unit 340 is displayed in the second color (red color). This means that the user logic (determined by the content specified by the logical specification information receiving unit 320) cannot be mounted on the specified master (determined by the content specified by the physical specification information receiving unit 310). For example, the estimated gate requirement calculated based on the content received by the logical specification information receiving unit 320 did not fit within the number of mountable gates calculated based on the content received by the physical specification information receiving unit 310 and the RAM information specifying unit 330. In some cases, it may be determined that it cannot be mounted.

  The determination result of the macro part (RAM block) shown in 370 is NG, and the RAM blocks 354-1 and 354-2 shown in the estimation result image display unit 340 are displayed in the first color (blue system color). The RAM block 354-3 is displayed in the second color (red color). This is mounted on the specified master (determined by the content specified by the physical specification information receiving unit 310) 354-1, 354-2 is installed in the internal RAM (determined by the content specified by the internal RAM information receiving unit 330). Although it is possible, the built-in RAM (determined based on the content specified by the internal RAM information receiving unit 330) 354-3 can be mounted on the specified master (determined based on the content specified by the physical specification information receiving unit 310). Means not.

  FIG. 7 is a flowchart for explaining the flow of processing of the present embodiment.

  It is assumed that the integrated circuit design support program of the present embodiment has been downloaded to the user terminal.

  When a user input screen browsing request is received (step S10), the user input screen is output to the display unit (step S20). A user input screen as shown in FIG. 3 is displayed on the display unit.

  Next, user input information relating to the circuit type (control system / arithmetic system), the total number of bits of the register, the built-in RAM information, the master designation information, and the number of wiring layers is received from the user input screen (step S30).

  Next, an estimated gate required amount is calculated based on the received total number of used registers and information on the circuit type (step S40). For example, you may make it obtain | require using the following formula | equation.

Estimated gate requirement = total number of used registers x constant set according to circuit type
+ Number of built-in BIST (Equation 1)

  Here, the value input to the register total bit number designating unit 322 in FIG. The constant set according to the circuit type takes a value associated with the circuit type selected by the circuit type (control system or arithmetic system) designation unit 316 in FIG. For example, the first constant (α) may be used when the control circuit is selected, and the second constant (β) may be used when the arithmetic circuit is selected. If the total number of register bits is the same between the control circuit and the arithmetic circuit, the arithmetic circuit has a larger circuit scale. Therefore, the first constant (α) <the second constant (β) may be set. . As the number of built-in BISTs, when the memory BIST built-in presence / absence designating unit 328 in FIG. 4 is input, a preset number of BIST gates is used.

  Next, the number of mountable gates is calculated based on the built-in RAM information, master designation information, the number of wiring layers, the physical specifications relating to the type of master and the number of wiring layers, and the master information (step S50). You may make it ask.

Number of mountable gates = (Number of mounted gates-Number of macro gates) x Usage efficiency
× Circuit type rate × Macro rate (Equation 2)

  For example, the number of mounted gates corresponds to the master from the master size table shown in FIG. 2A by specifying the master based on the information selected by the gate array series specifying unit 312 and the gate array master specifying unit 314 in FIG. The value of the number of mounted gates to be read may be read out and used. The number of macro gates can be obtained by calculation based on the input values of the bit width specifying unit 332, the bit depth specifying unit 334, and the number specifying unit 336 of the built-in RAM of FIG. Further, the usage efficiency is determined by specifying the master based on the information selected by the gate array series specifying unit 312 and the gate array master specifying unit 314 in FIG. The usage efficiency value corresponding to the number of wiring layers of the master may be read out from the usage efficiency table shown in FIG. Further, the circuit type ratio takes the value of the circuit type ratio associated with the circuit type selected by the circuit type (control system or arithmetic system) designation unit 316 in FIG. The macro rate may be determined based on an input value of the internal RAM information receiving unit 330 in FIG. 4 to determine whether or not the internal RAM is used, and a value set according to the determination result may be used. For example, the present embodiment is configured to take a value of “0.9” when present and take a value of “1” when absent. When the built-in RAM is provided, the use efficiency is lower than when the built-in RAM is not provided. Therefore, when the built-in RAM is provided, the macro rate may be set lower than when the built-in RAM is not provided.

  Next, an internal memory layout simulation is performed based on the master type and the internal memory information (step S60).

  Next, based on the estimated gate requirement and the number of mountable gates, it is determined whether or not the acquired logical specification can be mounted for the acquired master type (step S70).

  For example, when there is no built-in RAM, the number of mounted gates corresponding to the specified master type and the usage efficiency corresponding to the specified master and the number of wiring layers are obtained, and the gates that can be mounted based on the obtained gate capacity and usage efficiency The number is calculated, and whether or not mounting is possible is determined based on the obtained number of mountable gates and the estimated number of gates.

  For example, if there is a built-in RAM, the number of mounted gates corresponding to the specified master type is excluded from the portion that cannot be used for the user's logic circuit due to the placement of the built-in memory. The number of mountable gates may be obtained by performing correction (multiplying the macro rate as shown in (Equation 2)).

  Next, a predicted layout image is generated based on the availability of the acquired logical specification for the acquired master type and the layout simulation result of the built-in memory, and is output to the display unit (step S80).

  According to the present embodiment, even when the user's design is not completed and the specifications are not completely determined, the optimum gate array master can be selected from limited information such as the master to be used, the total number of used registers and the total number of wires. Now you can choose.

  In addition, it is possible to estimate the physical mounting shape of the user's RTL code on the gate array and to determine whether the corresponding master can be used or not, in a way that makes it possible to visually display the layout information of the gate array that was previously difficult to see for the user. It was.

  At that time, by using an applet type program, it becomes possible for the user to make a trial and error decision at hand without showing any confidential information to the outside, and the convenience of the user is greatly enhanced.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  For example, in the above-described embodiment, the case where the total number of used register bits is input from the user input screen as shown in FIG. 4 has been described as an example.

  For example, the configuration may be such that input of hardware description language source code information (RTL source code, etc.) relating to the gate array is received, and the received source code information is analyzed to determine the total number of used registers.

The figure for demonstrating the structure of the design support system of the integrated circuit device of this embodiment. 2A and 2B are diagrams for explaining master information according to the present embodiment. 3A and 3B are diagrams for explaining the master information of the present embodiment. The figure for demonstrating the input screen for receiving a user input. The figure for demonstrating a result display screen (case where user logic matched the selected master). The figure for demonstrating a result display screen (case where user logic is not suitable for the selected master). The flowchart for demonstrating the flow of a process of this Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Integrated circuit design support system, 100 processing part, 110 estimated gate required amount calculating part, 112 mountable gate number calculating part, 114 built-in memory arrangement simulation processing part, 116 hardware description language analysis processing part, 118 compatibility judgment processing part , 120 display control unit, 122 expected arrangement image display control unit, 124 input screen display control unit 124 160 operation unit, 170 storage unit, 172 master information storage unit, 180 information storage medium, 190 display unit, 192 sound output unit, 196 Communication department

Claims (10)

An integrated circuit design support program including at least a part of a gate array,
Logical specification information acquisition means for acquiring logical specification information including the total number of used registers and circuit type;
An estimated gate requirement calculation means for calculating an estimated gate requirement based on the received total number of used registers and information on the circuit type;
An integrated circuit design support program characterized by causing a computer to function. In claim 1,
Physical specification information acquisition means for acquiring physical specification information including the type of integrated circuit master including at least a part of the gate array and the number of wiring layers;
Master information storage means for storing master information including gate capacity information corresponding to the master type, usage efficiency information corresponding to the master type and the number of wiring layers,
Based on the physical specification information on the master type and the number of wiring layers and the master information, the gate capacity corresponding to the master type, the usage efficiency corresponding to the master type and the number of wiring layers are obtained, and the obtained gate capacity and usage efficiency. The number of mountable gate number calculating means for calculating the number of mountable gates based on
An integrated circuit design support program characterized by causing a computer to function. In claim 2,
Internal memory information acquisition means for acquiring internal memory information regarding the capacity, quantity, and location of the internal memory;
Built-in memory arrangement simulation means for performing a built-in memory arrangement simulation based on the master type and built-in memory information;
An integrated circuit design support program characterized by causing a computer to function. In claim 3,
The mountable gate number calculating means includes
Based on the input master type and built-in memory information, the built-in memory obtains the gate capacity excluding the part that cannot be used for the user's logic circuit, and the gate capacity can be corrected by having the built-in memory. An integrated circuit design support program characterized by obtaining the number of gates. In any of claims 2 to 4,
Based on the estimated gate requirement and the number of mountable gates, conformity determination means for determining whether or not the acquired logical specification can be mounted for the acquired master type,
And an integrated circuit design support program for causing a computer to function. In any one of Claims 4 thru | or 5.
A predicted layout image display control means for generating a predicted layout image based on the layout simulation result of the built-in memory and outputting it to the display unit;
An integrated circuit design support program characterized by causing a computer to function. In any one of Claims 1 thru | or 6.
The logical specification acquisition means includes
Input screen image display control means for displaying an input screen image for accepting user input for the logical specifications including the total number of used registers and circuit type, and the logical specifications including the total number of used registers and circuit type from the input screen Logical specification information receiving means for receiving information,
The physical specification acquisition means
Input screen image display control means for displaying an input screen image for accepting user input for physical specification information including the type of master and the number of wiring layers, and the type of master from the input screen and the physical including the number of wiring layers Physical specification receiving means for receiving specification information,
Built-in memory information acquisition means
Input screen image display control means for displaying an input screen image for accepting user input regarding the internal memory information regarding the internal memory information regarding the internal memory bit width, depth, number, and bit width and depth of the internal memory from the input screen And a built-in memory information receiving means for receiving built-in memory information related to the number and arrangement position. In any one of Claims 1 thru | or 7,
Logical specification acquisition means
An integrated circuit comprising hardware description language analysis means for receiving input of source code information of a hardware description language related to a gate array and analyzing the received source code information to obtain a total number of used bits. Design support program. An integrated circuit design support system including at least a part of a gate array,
Logical specification information acquisition means for acquiring logical specification information including the total number of used registers and circuit type;
Physical specification information acquisition means for acquiring physical specification information including the type of integrated circuit master including at least a part of the gate array and the number of wiring layers;
An estimated gate requirement calculation means for calculating an estimated gate requirement based on the received total number of used registers and information on the circuit type;
Master information storage means for storing master information including gate capacity information corresponding to the master type, usage efficiency information corresponding to the master type and the number of wiring layers,
Based on the physical specification information on the master type and the number of wiring layers and the master information, the gate capacity corresponding to the master type, the usage efficiency corresponding to the master type and the number of wiring layers are obtained, and the obtained gate capacity and usage efficiency. The number of mountable gate number calculating means for calculating the number of mountable gates based on
Based on the estimated gate requirement and the number of mountable gates, conformity determination means for determining whether or not the acquired logical specification can be mounted for the acquired master type,
An integrated circuit design support system comprising: An integrated circuit design method comprising at least a part of a gate array,
Logical specification information acquisition step for acquiring logical specification information including the total number of used registers and circuit type;
A physical specification information acquisition step for acquiring physical specification information including the type of integrated circuit master including at least a part of the gate array and the number of wiring layers;
An estimated gate requirement calculation step for calculating an estimated gate requirement based on the received total number of used registers and information on the circuit type;
Master information storage step for storing master information including gate capacity information corresponding to the master type, usage efficiency information corresponding to the master type and the number of wiring layers,
Based on the physical specification information on the master type and the number of wiring layers and the master information, the gate capacity corresponding to the master type, the usage efficiency corresponding to the master type and the number of wiring layers are obtained, and the obtained gate capacity and usage efficiency. The number of mountable gates calculation step for calculating the number of mountable gates based on
Based on the estimated gate requirement and the number of mountable gates, a conformity determination step for determining whether or not the acquired logical specification can be mounted for the acquired master type,
An integrated circuit design support method comprising: