JP2008167494A5

JP2008167494A5 -

Info

Publication number: JP2008167494A5
Application number: JP2008067298A
Authority: JP
Filing date: 2008-03-17
Publication date: 2008-09-25

Claims

A carrier leak correction circuit including a first multiplier, a first adder, a second multiplier, a second adder, a third multiplier, a fourth multiplier, and a third adder; An I-phase first D / A converter, a Q-phase second D / A converter, an analog quadrature modulator, an amplifier composed of a power amplifier, an A / D converter, and a control unit A transmitter equipped with,
  When the I-phase component and Q-phase component of the digital signal to be transmitted are input to the carrier leak correction circuit,
  The first multiplier multiplies the input Q-phase component by tan θ as a correction value for correcting the orthogonality, and outputs the multiplication result to the first adder.
  The first adder adds the input I-phase component and the multiplication result input from the first multiplier and outputs the addition result to the second multiplier to correct the orthogonality. ,
  The second multiplier multiplies the addition result input from the first adder by a correction value for correcting the I-phase gain, and outputs the multiplication result to the second adder.
  The second adder adds the multiplication result input from the second multiplier and a correction value for correcting the I-phase DC offset, and outputs the addition result to the first D / A converter. ,
  The third multiplier multiplies the input Q-phase component by (1 / cos θ) as a correction value for correcting the orthogonality, and outputs the multiplication result to the fourth multiplier,
  The fourth multiplier multiplies the multiplication result input from the third multiplier by a correction value for correcting the gain of the Q phase, and outputs the multiplication result to the third adder.
  The third adder adds the multiplication result input from the fourth multiplier and the correction value for correcting the Q-phase DC offset and outputs the addition result to the second D / A converter. ,
  The first D / A converter converts the corrected I-phase component signal input from the second adder from a digital signal to an analog signal and outputs the converted signal to the quadrature modulator.
  The second D / A converter converts the corrected Q-phase component signal input from the third adder from a digital signal to an analog signal and outputs the converted signal to the quadrature modulator.
  The quadrature modulator performs quadrature modulation on the I-phase component input from the first D / A converter and the Q-phase component input from the second D / A converter, and outputs the signal of the quadrature modulation result to the amplifier And
  The amplifier amplifies and outputs the signal input from the quadrature modulator,
  Part of the signal output from the amplifier is acquired by a combiner and input to an A / D converter for feedback,
  The A / D converter converts the input feedback signal from an analog signal to a digital signal,
  The control unit detects the power value of the digital feedback signal acquired by the A / D converter as an amount reflecting the DC offset remaining after correction, and corrects the carrier leak so that the detected amount becomes small A transmitter characterized by changing an I-phase DC offset correction value and a Q-phase DC offset correction value in a circuit to set an I-phase DC offset correction value and a Q-phase DC offset correction value that minimize the power value. .